1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX10 %s
3
4# These violate the constant bus restriction pre-gfx10
5
6---
7name: uadde_s32_s1_vsv
8legalized: true
9regBankSelected: true
10
11body: |
12  bb.0:
13    liveins: $sgpr0, $vgpr0
14
15    ; GFX10-LABEL: name: uadde_s32_s1_vsv
16    ; GFX10: $vcc_hi = IMPLICIT_DEF
17    ; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
18    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
19    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
20    ; GFX10: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
21    ; GFX10: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY2]], [[V_MOV_B32_e32_]], implicit $exec
22    ; GFX10: [[V_ADDC_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADDC_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_ADDC_U32_e64 [[COPY]], [[COPY1]], [[V_CMP_EQ_U32_e64_]], 0, implicit $exec
23    ; GFX10: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
24    ; GFX10: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
25    ; GFX10: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_2]], 0, [[V_MOV_B32_e32_1]], [[V_ADDC_U32_e64_1]], implicit $exec
26    ; GFX10: S_ENDPGM 0, implicit [[V_ADDC_U32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
27    %0:sgpr(s32) = COPY $sgpr0
28    %1:vgpr(s32) = COPY $vgpr0
29    %2:vgpr(s32) = COPY $vgpr2
30    %3:vgpr(s32) = G_CONSTANT i32 0
31    %4:vcc(s1) = G_ICMP intpred(eq), %2, %3
32    %5:vgpr(s32), %6:vcc(s1) = G_UADDE %0, %1, %4
33    %7:vgpr(s32) = G_CONSTANT i32 0
34    %8:vgpr(s32) = G_CONSTANT i32 1
35    %9:vgpr(s32) = G_SELECT %6, %7, %8
36    S_ENDPGM 0, implicit %5, implicit %9
37...
38
39---
40name: uadde_s32_s1_vvs
41legalized: true
42regBankSelected: true
43
44body: |
45  bb.0:
46    liveins: $sgpr0, $vgpr0
47
48    ; GFX10-LABEL: name: uadde_s32_s1_vvs
49    ; GFX10: $vcc_hi = IMPLICIT_DEF
50    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
51    ; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
52    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
53    ; GFX10: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
54    ; GFX10: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY2]], [[V_MOV_B32_e32_]], implicit $exec
55    ; GFX10: [[V_ADDC_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADDC_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_ADDC_U32_e64 [[COPY]], [[COPY1]], [[V_CMP_EQ_U32_e64_]], 0, implicit $exec
56    ; GFX10: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
57    ; GFX10: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
58    ; GFX10: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_2]], 0, [[V_MOV_B32_e32_1]], [[V_ADDC_U32_e64_1]], implicit $exec
59    ; GFX10: S_ENDPGM 0, implicit [[V_ADDC_U32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
60    %0:vgpr(s32) = COPY $vgpr0
61    %1:sgpr(s32) = COPY $sgpr0
62    %2:vgpr(s32) = COPY $vgpr2
63    %3:vgpr(s32) = G_CONSTANT i32 0
64    %4:vcc(s1) = G_ICMP intpred(eq), %2, %3
65    %5:vgpr(s32), %6:vcc(s1) = G_UADDE %0, %1, %4
66    %7:vgpr(s32) = G_CONSTANT i32 0
67    %8:vgpr(s32) = G_CONSTANT i32 1
68    %9:vgpr(s32) = G_SELECT %6, %7, %8
69    S_ENDPGM 0, implicit %5, implicit %9
70...
71