1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s 3# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s 4 5--- | 6 define amdgpu_kernel void @load_global_v8i32_non_uniform(<8 x i32> addrspace(1)* %in) { 7 %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() #0 8 %global.not.uniform.v8i32 = getelementptr <8 x i32>, <8 x i32> addrspace(1)* %in, i32 %tmp0 9 %tmp2 = load <8 x i32>, <8 x i32> addrspace(1)* %global.not.uniform.v8i32 10 ret void 11 } 12 13 define amdgpu_kernel void @load_global_v4i64_non_uniform(<4 x i64> addrspace(1)* %in) { 14 %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() #0 15 %global.not.uniform.v4i64 = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i32 %tmp0 16 %tmp2 = load <4 x i64>, <4 x i64> addrspace(1)* %global.not.uniform.v4i64 17 ret void 18 } 19 define amdgpu_kernel void @load_global_v16i32_non_uniform(<16 x i32> addrspace(1)* %in) { 20 %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() #0 21 %global.not.uniform.v16i32 = getelementptr <16 x i32>, <16 x i32> addrspace(1)* %in, i32 %tmp0 22 %tmp2 = load <16 x i32>, <16 x i32> addrspace(1)* %global.not.uniform.v16i32 23 ret void 24 } 25 define amdgpu_kernel void @load_global_v8i64_non_uniform(<8 x i64> addrspace(1)* %in) { 26 %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() #0 27 %global.not.uniform.v8i64 = getelementptr <8 x i64>, <8 x i64> addrspace(1)* %in, i32 %tmp0 28 %tmp2 = load <8 x i64>, <8 x i64> addrspace(1)* %global.not.uniform.v8i64 29 ret void 30 } 31 define amdgpu_kernel void @load_global_v8i32_uniform() {ret void} 32 define amdgpu_kernel void @load_global_v4i64_uniform() {ret void} 33 define amdgpu_kernel void @load_global_v16i32_uniform() {ret void} 34 define amdgpu_kernel void @load_global_v8i64_uniform() {ret void} 35 define amdgpu_kernel void @load_constant_v8i32_non_uniform(<8 x i32> addrspace(4)* %in) { 36 %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() #0 37 %constant.not.uniform.v8i32 = getelementptr <8 x i32>, <8 x i32> addrspace(4)* %in, i32 %tmp0 38 %tmp2 = load <8 x i32>, <8 x i32> addrspace(4)* %constant.not.uniform.v8i32 39 ret void 40 } 41 42 define amdgpu_kernel void @load_constant_i256_non_uniform(i256 addrspace(4)* %in) { 43 %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() #0 44 %constant.not.uniform = getelementptr i256, i256 addrspace(4)* %in, i32 %tmp0 45 %tmp2 = load i256, i256 addrspace(4)* %constant.not.uniform 46 ret void 47 } 48 49 define amdgpu_kernel void @load_constant_v16i16_non_uniform(<16 x i16> addrspace(4)* %in) { 50 %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() #0 51 %constant.not.uniform = getelementptr <16 x i16>, <16 x i16> addrspace(4)* %in, i32 %tmp0 52 %tmp2 = load <16 x i16>, <16 x i16> addrspace(4)* %constant.not.uniform 53 ret void 54 } 55 56 define amdgpu_kernel void @load_constant_v4i64_non_uniform(<4 x i64> addrspace(4)* %in) { 57 %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() #0 58 %constant.not.uniform.v4i64 = getelementptr <4 x i64>, <4 x i64> addrspace(4)* %in, i32 %tmp0 59 %tmp2 = load <4 x i64>, <4 x i64> addrspace(4)* %constant.not.uniform.v4i64 60 ret void 61 } 62 define amdgpu_kernel void @load_constant_v16i32_non_uniform(<16 x i32> addrspace(4)* %in) { 63 %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() #0 64 %constant.not.uniform.v16i32 = getelementptr <16 x i32>, <16 x i32> addrspace(4)* %in, i32 %tmp0 65 %tmp2 = load <16 x i32>, <16 x i32> addrspace(4)* %constant.not.uniform.v16i32 66 ret void 67 } 68 define amdgpu_kernel void @load_constant_v8i64_non_uniform(<8 x i64> addrspace(4)* %in) { 69 %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() #0 70 %constant.not.uniform.v8i64 = getelementptr <8 x i64>, <8 x i64> addrspace(4)* %in, i32 %tmp0 71 %tmp2 = load <8 x i64>, <8 x i64> addrspace(4)* %constant.not.uniform.v8i64 72 ret void 73 } 74 75 define amdgpu_kernel void @load_constant_v8i32_uniform() {ret void} 76 define amdgpu_kernel void @load_constant_v16i16_uniform() {ret void} 77 define amdgpu_kernel void @load_constant_v4i64_uniform() {ret void} 78 define amdgpu_kernel void @load_constant_v16i32_uniform() {ret void} 79 define amdgpu_kernel void @load_constant_v8i64_uniform() {ret void} 80 define amdgpu_kernel void @load_local_uniform() { ret void } 81 define amdgpu_kernel void @load_region_uniform() { ret void } 82 define amdgpu_kernel void @extload_constant_i8_to_i32_uniform() { ret void } 83 define amdgpu_kernel void @extload_global_i8_to_i32_uniform() { ret void } 84 define amdgpu_kernel void @extload_constant_i16_to_i32_uniform() { ret void } 85 define amdgpu_kernel void @extload_global_i16_to_i32_uniform() { ret void } 86 define amdgpu_kernel void @load_constant_i32_uniform_align4() {ret void} 87 define amdgpu_kernel void @load_constant_i32_uniform_align2() {ret void} 88 define amdgpu_kernel void @load_constant_i32_uniform_align1() {ret void} 89 define amdgpu_kernel void @load_private_uniform_sgpr_i32() {ret void} 90 define amdgpu_kernel void @load_constant_v8i32_vgpr_crash() { ret void } 91 define amdgpu_kernel void @load_constant_v8i32_vgpr_crash_loop_phi() { ret void } 92 93 define amdgpu_kernel void @load_constant_v3i32_align4() { ret void } 94 define amdgpu_kernel void @load_constant_v3i32_align8() { ret void } 95 define amdgpu_kernel void @load_constant_v3i32_align16() { ret void } 96 97 define amdgpu_kernel void @load_constant_v6i16_align4() { ret void } 98 define amdgpu_kernel void @load_constant_v6i16_align8() { ret void } 99 define amdgpu_kernel void @load_constant_v6i16_align16() { ret void } 100 101 define amdgpu_kernel void @load_constant_i96_align4() { ret void } 102 define amdgpu_kernel void @load_constant_i96_align8() { ret void } 103 define amdgpu_kernel void @load_constant_i96_align16() { ret void } 104 105 declare i32 @llvm.amdgcn.workitem.id.x() #0 106 attributes #0 = { nounwind readnone } 107... 108 109--- 110name: load_global_v8i32_non_uniform 111legalized: true 112 113body: | 114 bb.0: 115 liveins: $sgpr0_sgpr1 116 ; CHECK-LABEL: name: load_global_v8i32_non_uniform 117 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1 118 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p1) = COPY [[COPY]](p1) 119 ; CHECK: [[LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load 16 from %ir.global.not.uniform.v8i32, align 32, addrspace 1) 120 ; CHECK: [[C:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 16 121 ; CHECK: [[PTR_ADD:%[0-9]+]]:vgpr(p1) = G_PTR_ADD [[COPY]], [[C]](s64) 122 ; CHECK: [[LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[PTR_ADD]](p1) :: (load 16 from %ir.global.not.uniform.v8i32 + 16, align 32, addrspace 1) 123 ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[LOAD]](<4 x s32>), [[LOAD1]](<4 x s32>) 124 %0:_(p1) = COPY $sgpr0_sgpr1 125 %1:_(<8 x s32>) = G_LOAD %0 :: (load 32 from %ir.global.not.uniform.v8i32) 126... 127 128--- 129name: load_global_v4i64_non_uniform 130legalized: true 131 132body: | 133 bb.0: 134 liveins: $sgpr0_sgpr1 135 136 ; CHECK-LABEL: name: load_global_v4i64_non_uniform 137 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1 138 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p1) = COPY [[COPY]](p1) 139 ; CHECK: [[LOAD:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[COPY]](p1) :: (load 16 from %ir.global.not.uniform.v4i64, align 32, addrspace 1) 140 ; CHECK: [[C:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 16 141 ; CHECK: [[PTR_ADD:%[0-9]+]]:vgpr(p1) = G_PTR_ADD [[COPY]], [[C]](s64) 142 ; CHECK: [[LOAD1:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[PTR_ADD]](p1) :: (load 16 from %ir.global.not.uniform.v4i64 + 16, align 32, addrspace 1) 143 ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<4 x s64>) = G_CONCAT_VECTORS [[LOAD]](<2 x s64>), [[LOAD1]](<2 x s64>) 144 %0:_(p1) = COPY $sgpr0_sgpr1 145 %1:_(<4 x s64>) = G_LOAD %0 :: (load 32 from %ir.global.not.uniform.v4i64) 146... 147 148--- 149name: load_global_v16i32_non_uniform 150legalized: true 151 152body: | 153 bb.0: 154 liveins: $sgpr0_sgpr1 155 ; CHECK-LABEL: name: load_global_v16i32_non_uniform 156 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1 157 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p1) = COPY [[COPY]](p1) 158 ; CHECK: [[LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load 16 from %ir.global.not.uniform.v16i32, align 64, addrspace 1) 159 ; CHECK: [[C:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 16 160 ; CHECK: [[PTR_ADD:%[0-9]+]]:vgpr(p1) = G_PTR_ADD [[COPY]], [[C]](s64) 161 ; CHECK: [[LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[PTR_ADD]](p1) :: (load 16 from %ir.global.not.uniform.v16i32 + 16, align 64, addrspace 1) 162 ; CHECK: [[C1:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 32 163 ; CHECK: [[PTR_ADD1:%[0-9]+]]:vgpr(p1) = G_PTR_ADD [[COPY]], [[C1]](s64) 164 ; CHECK: [[LOAD2:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[PTR_ADD1]](p1) :: (load 16 from %ir.global.not.uniform.v16i32 + 32, align 64, addrspace 1) 165 ; CHECK: [[C2:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 48 166 ; CHECK: [[PTR_ADD2:%[0-9]+]]:vgpr(p1) = G_PTR_ADD [[COPY]], [[C2]](s64) 167 ; CHECK: [[LOAD3:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[PTR_ADD2]](p1) :: (load 16 from %ir.global.not.uniform.v16i32 + 48, align 64, addrspace 1) 168 ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x s32>) = G_CONCAT_VECTORS [[LOAD]](<4 x s32>), [[LOAD1]](<4 x s32>), [[LOAD2]](<4 x s32>), [[LOAD3]](<4 x s32>) 169 %0:_(p1) = COPY $sgpr0_sgpr1 170 %1:_(<16 x s32>) = G_LOAD %0 :: (load 64 from %ir.global.not.uniform.v16i32) 171... 172 173name: load_global_v8i64_non_uniform 174legalized: true 175 176body: | 177 bb.0: 178 liveins: $sgpr0_sgpr1 179 ; CHECK-LABEL: name: load_global_v8i64_non_uniform 180 ; CHECK: [[PTR:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1 181 ; CHECK: [[LOAD0:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[PTR]](p1) :: (load 16 from %ir.global.not.uniform.v8i64, align 64, addrspace 1) 182 ; CHECK: [[OFFSET16:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 16 183 ; CHECK: [[GEP16:%[0-9]+]]:vgpr(p1) = G_PTR_ADD [[PTR]], [[OFFSET16]](s64) 184 ; CHECK: [[LOAD16:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[GEP16]](p1) :: (load 16 from %ir.global.not.uniform.v8i64 + 16, align 64, addrspace 1) 185 ; CHECK: [[OFFSET32:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 32 186 ; CHECK: [[GEP32:%[0-9]+]]:vgpr(p1) = G_PTR_ADD [[PTR]], [[OFFSET32]](s64) 187 ; CHECK: [[LOAD32:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[GEP32]](p1) :: (load 16 from %ir.global.not.uniform.v8i64 + 32, align 64, addrspace 1) 188 ; CHECK: [[OFFSET48:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 48 189 ; CHECK: [[GEP48:%[0-9]+]]:vgpr(p1) = G_PTR_ADD [[PTR]], [[OFFSET48]](s64) 190 ; CHECK: [[LOAD48:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[GEP48]](p1) :: (load 16 from %ir.global.not.uniform.v8i64 + 48, align 64, addrspace 1) 191 ; CHECK: %1:vgpr(<8 x s64>) = G_CONCAT_VECTORS [[LOAD0]](<2 x s64>), [[LOAD16]](<2 x s64>), [[LOAD32]](<2 x s64>), [[LOAD48]](<2 x s64>) 192 %0:_(p1) = COPY $sgpr0_sgpr1 193 %1:_(<8 x s64>) = G_LOAD %0 :: (load 64 from %ir.global.not.uniform.v8i64) 194... 195 196--- 197name: load_global_v8i32_uniform 198legalized: true 199 200body: | 201 bb.0: 202 liveins: $sgpr0_sgpr1 203 ; CHECK-LABEL: name: load_global_v8i32_uniform 204 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1 205 ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<8 x s32>) = G_LOAD [[COPY]](p1) :: (invariant load 32, addrspace 1) 206 %0:_(p1) = COPY $sgpr0_sgpr1 207 %1:_(<8 x s32>) = G_LOAD %0 :: (invariant load 32, addrspace 1) 208... 209 210--- 211name: load_global_v4i64_uniform 212legalized: true 213 214body: | 215 bb.0: 216 liveins: $sgpr0_sgpr1 217 ; CHECK-LABEL: name: load_global_v4i64_uniform 218 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1 219 ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<4 x s64>) = G_LOAD [[COPY]](p1) :: (invariant load 32, addrspace 1) 220 %0:_(p1) = COPY $sgpr0_sgpr1 221 %1:_(<4 x s64>) = G_LOAD %0 :: (invariant load 32, addrspace 1) 222... 223 224--- 225name: load_global_v16i32_uniform 226legalized: true 227 228body: | 229 bb.0: 230 liveins: $sgpr0_sgpr1 231 ; CHECK-LABEL: name: load_global_v16i32_uniform 232 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1 233 ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<16 x s32>) = G_LOAD [[COPY]](p1) :: (invariant load 64, addrspace 1) 234 %0:_(p1) = COPY $sgpr0_sgpr1 235 %1:_(<16 x s32>) = G_LOAD %0 :: (invariant load 64, addrspace 1) 236... 237 238--- 239name: load_global_v8i64_uniform 240legalized: true 241 242body: | 243 bb.0: 244 liveins: $sgpr0_sgpr1 245 ; CHECK-LABEL: name: load_global_v8i64_uniform 246 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1 247 ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<8 x s64>) = G_LOAD [[COPY]](p1) :: (invariant load 64, addrspace 1) 248 %0:_(p1) = COPY $sgpr0_sgpr1 249 %1:_(<8 x s64>) = G_LOAD %0 :: (invariant load 64, addrspace 1) 250... 251 252--- 253name: load_constant_v8i32_non_uniform 254legalized: true 255 256body: | 257 bb.0: 258 liveins: $sgpr0_sgpr1 259 ; CHECK-LABEL: name: load_constant_v8i32_non_uniform 260 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 261 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4) 262 ; CHECK: [[LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[COPY]](p4) :: (load 16 from %ir.constant.not.uniform.v8i32, align 32, addrspace 4) 263 ; CHECK: [[C:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 16 264 ; CHECK: [[PTR_ADD:%[0-9]+]]:vgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64) 265 ; CHECK: [[LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[PTR_ADD]](p4) :: (load 16 from %ir.constant.not.uniform.v8i32 + 16, align 32, addrspace 4) 266 ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[LOAD]](<4 x s32>), [[LOAD1]](<4 x s32>) 267 %0:_(p4) = COPY $sgpr0_sgpr1 268 %1:_(<8 x s32>) = G_LOAD %0 :: (load 32 from %ir.constant.not.uniform.v8i32) 269... 270 271--- 272name: load_constant_i256_non_uniform 273legalized: true 274 275body: | 276 bb.0: 277 liveins: $sgpr0_sgpr1 278 ; CHECK-LABEL: name: load_constant_i256_non_uniform 279 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 280 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4) 281 ; CHECK: [[LOAD:%[0-9]+]]:vgpr(s128) = G_LOAD [[COPY]](p4) :: (load 16 from %ir.constant.not.uniform, align 32, addrspace 4) 282 ; CHECK: [[C:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 16 283 ; CHECK: [[PTR_ADD:%[0-9]+]]:vgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64) 284 ; CHECK: [[LOAD1:%[0-9]+]]:vgpr(s128) = G_LOAD [[PTR_ADD]](p4) :: (load 16 from %ir.constant.not.uniform + 16, align 32, addrspace 4) 285 ; CHECK: [[MV:%[0-9]+]]:vgpr(s256) = G_MERGE_VALUES [[LOAD]](s128), [[LOAD1]](s128) 286 %0:_(p4) = COPY $sgpr0_sgpr1 287 %1:_(s256) = G_LOAD %0 :: (load 32 from %ir.constant.not.uniform) 288... 289 290--- 291name: load_constant_v16i16_non_uniform 292legalized: true 293 294body: | 295 bb.0: 296 liveins: $sgpr0_sgpr1 297 298 ; CHECK-LABEL: name: load_constant_v16i16_non_uniform 299 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 300 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4) 301 ; CHECK: [[LOAD:%[0-9]+]]:vgpr(<8 x s16>) = G_LOAD [[COPY]](p4) :: (load 16 from %ir.constant.not.uniform, align 32, addrspace 4) 302 ; CHECK: [[C:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 16 303 ; CHECK: [[PTR_ADD:%[0-9]+]]:vgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64) 304 ; CHECK: [[LOAD1:%[0-9]+]]:vgpr(<8 x s16>) = G_LOAD [[PTR_ADD]](p4) :: (load 16 from %ir.constant.not.uniform + 16, align 32, addrspace 4) 305 ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x s16>) = G_CONCAT_VECTORS [[LOAD]](<8 x s16>), [[LOAD1]](<8 x s16>) 306 %0:_(p4) = COPY $sgpr0_sgpr1 307 %1:_(<16 x s16>) = G_LOAD %0 :: (load 32 from %ir.constant.not.uniform) 308... 309 310--- 311name: load_constant_v4i64_non_uniform 312legalized: true 313 314body: | 315 bb.0: 316 liveins: $sgpr0_sgpr1 317 ; CHECK-LABEL: name: load_constant_v4i64_non_uniform 318 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 319 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4) 320 ; CHECK: [[LOAD:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[COPY]](p4) :: (load 16 from %ir.constant.not.uniform.v4i64, align 32, addrspace 4) 321 ; CHECK: [[C:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 16 322 ; CHECK: [[PTR_ADD:%[0-9]+]]:vgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64) 323 ; CHECK: [[LOAD1:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[PTR_ADD]](p4) :: (load 16 from %ir.constant.not.uniform.v4i64 + 16, align 32, addrspace 4) 324 ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<4 x s64>) = G_CONCAT_VECTORS [[LOAD]](<2 x s64>), [[LOAD1]](<2 x s64>) 325 %0:_(p4) = COPY $sgpr0_sgpr1 326 %1:_(<4 x s64>) = G_LOAD %0 :: (load 32 from %ir.constant.not.uniform.v4i64) 327... 328 329--- 330name: load_constant_v16i32_non_uniform 331legalized: true 332 333body: | 334 bb.0: 335 liveins: $sgpr0_sgpr1 336 ; CHECK-LABEL: name: load_constant_v16i32_non_uniform 337 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 338 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4) 339 ; CHECK: [[LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[COPY]](p4) :: (load 16 from %ir.constant.not.uniform.v16i32, align 64, addrspace 4) 340 ; CHECK: [[C:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 16 341 ; CHECK: [[PTR_ADD:%[0-9]+]]:vgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64) 342 ; CHECK: [[LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[PTR_ADD]](p4) :: (load 16 from %ir.constant.not.uniform.v16i32 + 16, align 64, addrspace 4) 343 ; CHECK: [[C1:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 32 344 ; CHECK: [[PTR_ADD1:%[0-9]+]]:vgpr(p4) = G_PTR_ADD [[COPY]], [[C1]](s64) 345 ; CHECK: [[LOAD2:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[PTR_ADD1]](p4) :: (load 16 from %ir.constant.not.uniform.v16i32 + 32, align 64, addrspace 4) 346 ; CHECK: [[C2:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 48 347 ; CHECK: [[PTR_ADD2:%[0-9]+]]:vgpr(p4) = G_PTR_ADD [[COPY]], [[C2]](s64) 348 ; CHECK: [[LOAD3:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[PTR_ADD2]](p4) :: (load 16 from %ir.constant.not.uniform.v16i32 + 48, align 64, addrspace 4) 349 ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x s32>) = G_CONCAT_VECTORS [[LOAD]](<4 x s32>), [[LOAD1]](<4 x s32>), [[LOAD2]](<4 x s32>), [[LOAD3]](<4 x s32>) 350 %0:_(p4) = COPY $sgpr0_sgpr1 351 %1:_(<16 x s32>) = G_LOAD %0 :: (load 64 from %ir.constant.not.uniform.v16i32) 352... 353 354--- 355name: load_constant_v8i64_non_uniform 356legalized: true 357 358body: | 359 bb.0: 360 liveins: $sgpr0_sgpr1 361 ; CHECK-LABEL: name: load_constant_v8i64_non_uniform 362 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 363 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4) 364 ; CHECK: [[LOAD:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[COPY]](p4) :: (load 16 from %ir.constant.not.uniform.v8i64, align 64, addrspace 4) 365 ; CHECK: [[C:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 16 366 ; CHECK: [[PTR_ADD:%[0-9]+]]:vgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64) 367 ; CHECK: [[LOAD1:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[PTR_ADD]](p4) :: (load 16 from %ir.constant.not.uniform.v8i64 + 16, align 64, addrspace 4) 368 ; CHECK: [[C1:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 32 369 ; CHECK: [[PTR_ADD1:%[0-9]+]]:vgpr(p4) = G_PTR_ADD [[COPY]], [[C1]](s64) 370 ; CHECK: [[LOAD2:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[PTR_ADD1]](p4) :: (load 16 from %ir.constant.not.uniform.v8i64 + 32, align 64, addrspace 4) 371 ; CHECK: [[C2:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 48 372 ; CHECK: [[PTR_ADD2:%[0-9]+]]:vgpr(p4) = G_PTR_ADD [[COPY]], [[C2]](s64) 373 ; CHECK: [[LOAD3:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[PTR_ADD2]](p4) :: (load 16 from %ir.constant.not.uniform.v8i64 + 48, align 64, addrspace 4) 374 ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s64>) = G_CONCAT_VECTORS [[LOAD]](<2 x s64>), [[LOAD1]](<2 x s64>), [[LOAD2]](<2 x s64>), [[LOAD3]](<2 x s64>) 375 %0:_(p4) = COPY $sgpr0_sgpr1 376 %1:_(<8 x s64>) = G_LOAD %0 :: (load 64 from %ir.constant.not.uniform.v8i64) 377... 378 379--- 380name: load_constant_v8i32_uniform 381legalized: true 382 383body: | 384 bb.0: 385 liveins: $sgpr0_sgpr1 386 ; CHECK-LABEL: name: load_constant_v8i32_uniform 387 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 388 ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<8 x s32>) = G_LOAD [[COPY]](p4) :: (load 32, addrspace 4) 389 %0:_(p4) = COPY $sgpr0_sgpr1 390 %1:_(<8 x s32>) = G_LOAD %0 :: (load 32, addrspace 4) 391... 392 393--- 394name: load_constant_v16i16_uniform 395legalized: true 396 397body: | 398 bb.0: 399 liveins: $sgpr0_sgpr1 400 ; CHECK-LABEL: name: load_constant_v16i16_uniform 401 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 402 ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<16 x s16>) = G_LOAD [[COPY]](p4) :: (load 32, addrspace 4) 403 %0:_(p4) = COPY $sgpr0_sgpr1 404 %1:_(<16 x s16>) = G_LOAD %0 :: (load 32, addrspace 4) 405... 406 407--- 408name: load_constant_v4i64_uniform 409legalized: true 410 411body: | 412 bb.0: 413 liveins: $sgpr0_sgpr1 414 ; CHECK-LABEL: name: load_constant_v4i64_uniform 415 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 416 ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<4 x s64>) = G_LOAD [[COPY]](p4) :: (load 32, addrspace 4) 417 %0:_(p4) = COPY $sgpr0_sgpr1 418 %1:_(<4 x s64>) = G_LOAD %0 :: (load 32, addrspace 4) 419... 420 421--- 422name: load_constant_v16i32_uniform 423legalized: true 424 425body: | 426 bb.0: 427 liveins: $sgpr0_sgpr1 428 ; CHECK-LABEL: name: load_constant_v16i32_uniform 429 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 430 ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<16 x s32>) = G_LOAD [[COPY]](p4) :: (load 64, addrspace 4) 431 %0:_(p4) = COPY $sgpr0_sgpr1 432 %1:_(<16 x s32>) = G_LOAD %0 :: (load 64, addrspace 4) 433... 434 435--- 436name: load_constant_v8i64_uniform 437legalized: true 438 439body: | 440 bb.0: 441 liveins: $sgpr0_sgpr1 442 ; CHECK-LABEL: name: load_constant_v8i64_uniform 443 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 444 ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<8 x s64>) = G_LOAD [[COPY]](p4) :: (load 64, addrspace 4) 445 %0:_(p4) = COPY $sgpr0_sgpr1 446 %1:_(<8 x s64>) = G_LOAD %0 :: (load 64, addrspace 4) 447... 448 449--- 450name: load_local_uniform 451legalized: true 452body: | 453 bb.0: 454 liveins: $sgpr0 455 456 ; CHECK-LABEL: name: load_local_uniform 457 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0 458 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3) 459 ; CHECK: [[LOAD:%[0-9]+]]:vgpr(s32) = G_LOAD [[COPY1]](p3) :: (load 4, addrspace 3) 460 %0:_(p3) = COPY $sgpr0 461 %1:_(s32) = G_LOAD %0 :: (load 4, addrspace 3) 462 463... 464--- 465name: load_region_uniform 466legalized: true 467body: | 468 bb.0: 469 liveins: $sgpr0 470 471 ; CHECK-LABEL: name: load_region_uniform 472 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0 473 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3) 474 ; CHECK: [[LOAD:%[0-9]+]]:vgpr(s32) = G_LOAD [[COPY1]](p3) :: (load 4, addrspace 5) 475 %0:_(p3) = COPY $sgpr0 476 %1:_(s32) = G_LOAD %0 :: (load 4, addrspace 5) 477 478... 479 480--- 481name: extload_constant_i8_to_i32_uniform 482legalized: true 483 484body: | 485 bb.0: 486 liveins: $sgpr0_sgpr1 487 ; CHECK-LABEL: name: extload_constant_i8_to_i32_uniform 488 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 489 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4) 490 ; CHECK: [[LOAD:%[0-9]+]]:vgpr(s32) = G_LOAD [[COPY1]](p4) :: (load 1, addrspace 4) 491 %0:_(p4) = COPY $sgpr0_sgpr1 492 %1:_(s32) = G_LOAD %0 :: (load 1, addrspace 4, align 1) 493... 494 495--- 496name: extload_global_i8_to_i32_uniform 497legalized: true 498 499body: | 500 bb.0: 501 liveins: $sgpr0_sgpr1 502 503 ; CHECK-LABEL: name: extload_global_i8_to_i32_uniform 504 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 505 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4) 506 ; CHECK: [[LOAD:%[0-9]+]]:vgpr(s32) = G_LOAD [[COPY1]](p4) :: (load 1, addrspace 1) 507 %0:_(p4) = COPY $sgpr0_sgpr1 508 %1:_(s32) = G_LOAD %0 :: (load 1, addrspace 1, align 1) 509... 510 511--- 512name: extload_constant_i16_to_i32_uniform 513legalized: true 514 515body: | 516 bb.0: 517 liveins: $sgpr0_sgpr1 518 519 ; CHECK-LABEL: name: extload_constant_i16_to_i32_uniform 520 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 521 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4) 522 ; CHECK: [[LOAD:%[0-9]+]]:vgpr(s32) = G_LOAD [[COPY1]](p4) :: (load 2, addrspace 4) 523 %0:_(p4) = COPY $sgpr0_sgpr1 524 %1:_(s32) = G_LOAD %0 :: (load 2, addrspace 4, align 2) 525... 526 527--- 528name: extload_global_i16_to_i32_uniform 529legalized: true 530 531body: | 532 bb.0: 533 liveins: $sgpr0_sgpr1 534 535 ; CHECK-LABEL: name: extload_global_i16_to_i32_uniform 536 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 537 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4) 538 ; CHECK: [[LOAD:%[0-9]+]]:vgpr(s32) = G_LOAD [[COPY1]](p4) :: (load 2, addrspace 1) 539 %0:_(p4) = COPY $sgpr0_sgpr1 540 %1:_(s32) = G_LOAD %0 :: (load 2, addrspace 1, align 2) 541... 542 543--- 544name: load_constant_i32_uniform_align4 545legalized: true 546 547body: | 548 bb.0: 549 liveins: $sgpr0_sgpr1 550 ; CHECK-LABEL: name: load_constant_i32_uniform_align4 551 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 552 ; CHECK: [[LOAD:%[0-9]+]]:sgpr(s32) = G_LOAD [[COPY]](p4) :: (load 4, addrspace 4) 553 %0:_(p4) = COPY $sgpr0_sgpr1 554 %1:_(s32) = G_LOAD %0 :: (load 4, addrspace 4, align 4) 555... 556 557--- 558name: load_constant_i32_uniform_align2 559legalized: true 560 561body: | 562 bb.0: 563 liveins: $sgpr0_sgpr1 564 565 ; CHECK-LABEL: name: load_constant_i32_uniform_align2 566 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 567 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4) 568 ; CHECK: [[LOAD:%[0-9]+]]:vgpr(s32) = G_LOAD [[COPY1]](p4) :: (load 4, align 2, addrspace 4) 569 %0:_(p4) = COPY $sgpr0_sgpr1 570 %1:_(s32) = G_LOAD %0 :: (load 4, addrspace 4, align 2) 571... 572 573--- 574name: load_constant_i32_uniform_align1 575legalized: true 576 577body: | 578 bb.0: 579 liveins: $sgpr0_sgpr1 580 581 ; CHECK-LABEL: name: load_constant_i32_uniform_align1 582 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 583 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4) 584 ; CHECK: [[LOAD:%[0-9]+]]:vgpr(s32) = G_LOAD [[COPY1]](p4) :: (load 4, align 1, addrspace 4) 585 %0:_(p4) = COPY $sgpr0_sgpr1 586 %1:_(s32) = G_LOAD %0 :: (load 4, addrspace 4, align 1) 587... 588 589--- 590name: load_private_uniform_sgpr_i32 591legalized: true 592 593body: | 594 bb.0: 595 liveins: $sgpr0 596 597 ; CHECK-LABEL: name: load_private_uniform_sgpr_i32 598 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sgpr0 599 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p5) = COPY [[COPY]](p5) 600 ; CHECK: [[LOAD:%[0-9]+]]:vgpr(s32) = G_LOAD [[COPY1]](p5) :: (load 4, addrspace 5) 601 %0:_(p5) = COPY $sgpr0 602 %1:_(s32) = G_LOAD %0 :: (load 4, addrspace 5, align 4) 603... 604 605--- 606name: load_constant_v8i32_vgpr_crash 607legalized: true 608tracksRegLiveness: true 609 610body: | 611 bb.0: 612 liveins: $vgpr0_vgpr1 613 614 ; CHECK-LABEL: name: load_constant_v8i32_vgpr_crash 615 ; CHECK: liveins: $vgpr0_vgpr1 616 ; CHECK: [[COPY:%[0-9]+]]:vgpr(p4) = COPY $vgpr0_vgpr1 617 ; CHECK: [[LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[COPY]](p4) :: (load 16, align 32, addrspace 4) 618 ; CHECK: [[C:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 16 619 ; CHECK: [[PTR_ADD:%[0-9]+]]:vgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64) 620 ; CHECK: [[LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[PTR_ADD]](p4) :: (load 16 + 16, addrspace 4) 621 ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[LOAD]](<4 x s32>), [[LOAD1]](<4 x s32>) 622 %0:_(p4) = COPY $vgpr0_vgpr1 623 %1:_(<8 x s32>) = G_LOAD %0 :: (load 32, addrspace 4) 624... 625 626--- 627name: load_constant_v8i32_vgpr_crash_loop_phi 628legalized: true 629tracksRegLiveness: true 630 631body: | 632 ; CHECK-LABEL: name: load_constant_v8i32_vgpr_crash_loop_phi 633 ; CHECK: bb.0: 634 ; CHECK: successors: %bb.1(0x80000000) 635 ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3 636 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 637 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(p4) = COPY $sgpr2_sgpr3 638 ; CHECK: G_BR %bb.1 639 ; CHECK: bb.1: 640 ; CHECK: successors: %bb.1(0x80000000) 641 ; CHECK: [[PHI:%[0-9]+]]:vgpr(p4) = G_PHI [[COPY]](p4), %bb.0, %3(p4), %bb.1 642 ; CHECK: [[LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[PHI]](p4) :: (load 16, align 32, addrspace 4) 643 ; CHECK: [[C:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 16 644 ; CHECK: [[PTR_ADD:%[0-9]+]]:vgpr(p4) = G_PTR_ADD [[PHI]], [[C]](s64) 645 ; CHECK: [[LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[PTR_ADD]](p4) :: (load 16 + 16, addrspace 4) 646 ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[LOAD]](<4 x s32>), [[LOAD1]](<4 x s32>) 647 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(p4) = COPY [[COPY1]](p4) 648 ; CHECK: G_BR %bb.1 649 bb.0: 650 liveins: $sgpr0_sgpr1, $sgpr2_sgpr3 651 652 653 %0:_(p4) = COPY $sgpr0_sgpr1 654 %1:_(p4) = COPY $sgpr2_sgpr3 655 G_BR %bb.1 656 657 bb.1: 658 %2:_(p4) = G_PHI %0, %bb.0, %4, %bb.1 659 %3:_(<8 x s32>) = G_LOAD %2 :: (load 32, addrspace 4) 660 %4:_(p4) = COPY %1 661 G_BR %bb.1 662... 663 664--- 665name: load_constant_v3i32_align4 666legalized: true 667 668body: | 669 bb.0: 670 liveins: $sgpr0_sgpr1 671 ; CHECK-LABEL: name: load_constant_v3i32_align4 672 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 673 ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<2 x s32>) = G_LOAD [[COPY]](p4) :: (invariant load 8, align 4, addrspace 4) 674 ; CHECK: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 8 675 ; CHECK: [[PTR_ADD:%[0-9]+]]:sgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64) 676 ; CHECK: [[LOAD1:%[0-9]+]]:sgpr(s32) = G_LOAD [[PTR_ADD]](p4) :: (invariant load 4 + 8, addrspace 4) 677 ; CHECK: [[DEF:%[0-9]+]]:sgpr(<3 x s32>) = G_IMPLICIT_DEF 678 ; CHECK: [[INSERT:%[0-9]+]]:sgpr(<3 x s32>) = G_INSERT [[DEF]], [[LOAD]](<2 x s32>), 0 679 ; CHECK: [[INSERT1:%[0-9]+]]:sgpr(<3 x s32>) = G_INSERT [[INSERT]], [[LOAD1]](s32), 64 680 ; CHECK: S_ENDPGM 0, implicit [[INSERT1]](<3 x s32>) 681 %0:_(p4) = COPY $sgpr0_sgpr1 682 %1:_(<3 x s32>) = G_LOAD %0 :: (invariant load 12, addrspace 4, align 4) 683 S_ENDPGM 0, implicit %1 684... 685 686--- 687name: load_constant_v3i32_align8 688legalized: true 689 690body: | 691 bb.0: 692 liveins: $sgpr0_sgpr1 693 ; CHECK-LABEL: name: load_constant_v3i32_align8 694 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 695 ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<2 x s32>) = G_LOAD [[COPY]](p4) :: (invariant load 8, addrspace 4) 696 ; CHECK: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 8 697 ; CHECK: [[PTR_ADD:%[0-9]+]]:sgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64) 698 ; CHECK: [[LOAD1:%[0-9]+]]:sgpr(s32) = G_LOAD [[PTR_ADD]](p4) :: (invariant load 4 + 8, align 8, addrspace 4) 699 ; CHECK: [[DEF:%[0-9]+]]:sgpr(<3 x s32>) = G_IMPLICIT_DEF 700 ; CHECK: [[INSERT:%[0-9]+]]:sgpr(<3 x s32>) = G_INSERT [[DEF]], [[LOAD]](<2 x s32>), 0 701 ; CHECK: [[INSERT1:%[0-9]+]]:sgpr(<3 x s32>) = G_INSERT [[INSERT]], [[LOAD1]](s32), 64 702 ; CHECK: S_ENDPGM 0, implicit [[INSERT1]](<3 x s32>) 703 %0:_(p4) = COPY $sgpr0_sgpr1 704 %1:_(<3 x s32>) = G_LOAD %0 :: (invariant load 12, addrspace 4, align 8) 705 S_ENDPGM 0, implicit %1 706... 707 708--- 709name: load_constant_v3i32_align16 710legalized: true 711 712body: | 713 bb.0: 714 liveins: $sgpr0_sgpr1 715 ; CHECK-LABEL: name: load_constant_v3i32_align16 716 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 717 ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<4 x s32>) = G_LOAD [[COPY]](p4) :: (invariant load 16, addrspace 4) 718 ; CHECK: [[EXTRACT:%[0-9]+]]:sgpr(<3 x s32>) = G_EXTRACT [[LOAD]](<4 x s32>), 0 719 ; CHECK: S_ENDPGM 0, implicit [[EXTRACT]](<3 x s32>) 720 %0:_(p4) = COPY $sgpr0_sgpr1 721 %1:_(<3 x s32>) = G_LOAD %0 :: (invariant load 12, addrspace 4, align 16) 722 S_ENDPGM 0, implicit %1 723... 724 725--- 726name: load_constant_v6i16_align4 727legalized: true 728 729body: | 730 bb.0: 731 liveins: $sgpr0_sgpr1 732 ; CHECK-LABEL: name: load_constant_v6i16_align4 733 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 734 ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<4 x s16>) = G_LOAD [[COPY]](p4) :: (invariant load 8, align 4, addrspace 4) 735 ; CHECK: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 8 736 ; CHECK: [[PTR_ADD:%[0-9]+]]:sgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64) 737 ; CHECK: [[LOAD1:%[0-9]+]]:sgpr(<2 x s16>) = G_LOAD [[PTR_ADD]](p4) :: (invariant load 4 + 8, addrspace 4) 738 ; CHECK: [[DEF:%[0-9]+]]:sgpr(<6 x s16>) = G_IMPLICIT_DEF 739 ; CHECK: [[INSERT:%[0-9]+]]:sgpr(<6 x s16>) = G_INSERT [[DEF]], [[LOAD]](<4 x s16>), 0 740 ; CHECK: [[INSERT1:%[0-9]+]]:sgpr(<6 x s16>) = G_INSERT [[INSERT]], [[LOAD1]](<2 x s16>), 64 741 ; CHECK: S_ENDPGM 0, implicit [[INSERT1]](<6 x s16>) 742 %0:_(p4) = COPY $sgpr0_sgpr1 743 %1:_(<6 x s16>) = G_LOAD %0 :: (invariant load 12, addrspace 4, align 4) 744 S_ENDPGM 0, implicit %1 745... 746 747--- 748name: load_constant_v6i16_align8 749legalized: true 750 751body: | 752 bb.0: 753 liveins: $sgpr0_sgpr1 754 ; CHECK-LABEL: name: load_constant_v6i16_align8 755 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 756 ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<4 x s16>) = G_LOAD [[COPY]](p4) :: (invariant load 8, addrspace 4) 757 ; CHECK: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 8 758 ; CHECK: [[PTR_ADD:%[0-9]+]]:sgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64) 759 ; CHECK: [[LOAD1:%[0-9]+]]:sgpr(<2 x s16>) = G_LOAD [[PTR_ADD]](p4) :: (invariant load 4 + 8, align 8, addrspace 4) 760 ; CHECK: [[DEF:%[0-9]+]]:sgpr(<6 x s16>) = G_IMPLICIT_DEF 761 ; CHECK: [[INSERT:%[0-9]+]]:sgpr(<6 x s16>) = G_INSERT [[DEF]], [[LOAD]](<4 x s16>), 0 762 ; CHECK: [[INSERT1:%[0-9]+]]:sgpr(<6 x s16>) = G_INSERT [[INSERT]], [[LOAD1]](<2 x s16>), 64 763 ; CHECK: S_ENDPGM 0, implicit [[INSERT1]](<6 x s16>) 764 %0:_(p4) = COPY $sgpr0_sgpr1 765 %1:_(<6 x s16>) = G_LOAD %0 :: (invariant load 12, addrspace 4, align 8) 766 S_ENDPGM 0, implicit %1 767... 768 769--- 770name: load_constant_v6i16_align16 771legalized: true 772 773body: | 774 bb.0: 775 liveins: $sgpr0_sgpr1 776 ; CHECK-LABEL: name: load_constant_v6i16_align16 777 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 778 ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<8 x s16>) = G_LOAD [[COPY]](p4) :: (invariant load 16, addrspace 4) 779 ; CHECK: [[EXTRACT:%[0-9]+]]:sgpr(<6 x s16>) = G_EXTRACT [[LOAD]](<8 x s16>), 0 780 ; CHECK: S_ENDPGM 0, implicit [[EXTRACT]](<6 x s16>) 781 %0:_(p4) = COPY $sgpr0_sgpr1 782 %1:_(<6 x s16>) = G_LOAD %0 :: (invariant load 12, addrspace 4, align 16) 783 S_ENDPGM 0, implicit %1 784... 785 786--- 787name: load_constant_i96_align4 788legalized: true 789 790body: | 791 bb.0: 792 liveins: $sgpr0_sgpr1 793 ; CHECK-LABEL: name: load_constant_i96_align4 794 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 795 ; CHECK: [[LOAD:%[0-9]+]]:sgpr(s64) = G_LOAD [[COPY]](p4) :: (invariant load 8, align 4, addrspace 4) 796 ; CHECK: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 8 797 ; CHECK: [[PTR_ADD:%[0-9]+]]:sgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64) 798 ; CHECK: [[LOAD1:%[0-9]+]]:sgpr(s32) = G_LOAD [[PTR_ADD]](p4) :: (invariant load 4 + 8, addrspace 4) 799 ; CHECK: [[DEF:%[0-9]+]]:sgpr(s96) = G_IMPLICIT_DEF 800 ; CHECK: [[INSERT:%[0-9]+]]:sgpr(s96) = G_INSERT [[DEF]], [[LOAD]](s64), 0 801 ; CHECK: [[INSERT1:%[0-9]+]]:sgpr(s96) = G_INSERT [[INSERT]], [[LOAD1]](s32), 64 802 ; CHECK: S_ENDPGM 0, implicit [[INSERT1]](s96) 803 %0:_(p4) = COPY $sgpr0_sgpr1 804 %1:_(s96) = G_LOAD %0 :: (invariant load 12, addrspace 4, align 4) 805 S_ENDPGM 0, implicit %1 806... 807 808--- 809name: load_constant_i96_align8 810legalized: true 811 812body: | 813 bb.0: 814 liveins: $sgpr0_sgpr1 815 ; CHECK-LABEL: name: load_constant_i96_align8 816 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 817 ; CHECK: [[LOAD:%[0-9]+]]:sgpr(s64) = G_LOAD [[COPY]](p4) :: (invariant load 8, addrspace 4) 818 ; CHECK: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 8 819 ; CHECK: [[PTR_ADD:%[0-9]+]]:sgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64) 820 ; CHECK: [[LOAD1:%[0-9]+]]:sgpr(s32) = G_LOAD [[PTR_ADD]](p4) :: (invariant load 4 + 8, align 8, addrspace 4) 821 ; CHECK: [[DEF:%[0-9]+]]:sgpr(s96) = G_IMPLICIT_DEF 822 ; CHECK: [[INSERT:%[0-9]+]]:sgpr(s96) = G_INSERT [[DEF]], [[LOAD]](s64), 0 823 ; CHECK: [[INSERT1:%[0-9]+]]:sgpr(s96) = G_INSERT [[INSERT]], [[LOAD1]](s32), 64 824 ; CHECK: S_ENDPGM 0, implicit [[INSERT1]](s96) 825 %0:_(p4) = COPY $sgpr0_sgpr1 826 %1:_(s96) = G_LOAD %0 :: (invariant load 12, addrspace 4, align 8) 827 S_ENDPGM 0, implicit %1 828... 829 830--- 831name: load_constant_i96_align16 832legalized: true 833 834body: | 835 bb.0: 836 liveins: $sgpr0_sgpr1 837 ; CHECK-LABEL: name: load_constant_i96_align16 838 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 839 ; CHECK: [[LOAD:%[0-9]+]]:sgpr(s128) = G_LOAD [[COPY]](p4) :: (invariant load 16, addrspace 4) 840 ; CHECK: [[EXTRACT:%[0-9]+]]:sgpr(s96) = G_EXTRACT [[LOAD]](s128), 0 841 ; CHECK: S_ENDPGM 0, implicit [[EXTRACT]](s96) 842 %0:_(p4) = COPY $sgpr0_sgpr1 843 %1:_(s96) = G_LOAD %0 :: (invariant load 12, addrspace 4, align 16) 844 S_ENDPGM 0, implicit %1 845... 846