1; RUN: llc < %s | FileCheck %s
2
3; Test that basic 64-bit integer comparison operations assemble as expected.
4
5target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64"
6target triple = "lanai"
7
8; CHECK-LABEL: eq_i64:
9; CHECK: xor
10; CHECK: xor
11; CHECK: or.f
12; CHECK-NEXT: seq
13define i32 @eq_i64(i64 inreg %x, i64 inreg %y) {
14  %a = icmp eq i64 %x, %y
15  %b = zext i1 %a to i32
16  ret i32 %b
17}
18
19; CHECK-LABEL: ne_i64:
20; CHECK: xor
21; CHECK: xor
22; CHECK: or.f
23; CHECK-NEXT: sne
24define i32 @ne_i64(i64 inreg %x, i64 inreg %y) {
25  %a = icmp ne i64 %x, %y
26  %b = zext i1 %a to i32
27  ret i32 %b
28}
29
30; CHECK-LABEL: slt_i64:
31; CHECK: sub.f %r6, %r18, %r0
32; CHECK-NEXT: slt %r3
33; CHECK-NEXT: sub.f %r7, %r19, %r0
34; CHECK-NEXT: sult %r9
35; CHECK-NEXT: sub.f %r6, %r18, %r0
36; CHECK-NEXT: sel.eq %r9, %r3, %rv
37define i32 @slt_i64(i64 inreg %x, i64 inreg %y) {
38  %a = icmp slt i64 %x, %y
39  %b = zext i1 %a to i32
40  ret i32 %b
41}
42
43; CHECK-LABEL: sle_i64:
44; CHECK: sub.f %r6, %r18, %r0
45; CHECK-NEXT: sle %r3
46; CHECK-NEXT: sub.f %r7, %r19, %r0
47; CHECK-NEXT: sule %r9
48; CHECK-NEXT: sub.f %r6, %r18, %r0
49; CHECK-NEXT: sel.eq %r9, %r3, %rv
50define i32 @sle_i64(i64 inreg %x, i64 inreg %y) {
51  %a = icmp sle i64 %x, %y
52  %b = zext i1 %a to i32
53  ret i32 %b
54}
55
56; CHECK-LABEL: ult_i64:
57; CHECK: sub.f %r6, %r18, %r0
58; CHECK-NEXT: sult %r3
59; CHECK-NEXT: sub.f %r7, %r19, %r0
60; CHECK-NEXT: sult %r9
61; CHECK-NEXT: sub.f %r6, %r18, %r0
62; CHECK-NEXT: sel.eq %r9, %r3, %rv
63define i32 @ult_i64(i64 inreg %x, i64 inreg %y) {
64  %a = icmp ult i64 %x, %y
65  %b = zext i1 %a to i32
66  ret i32 %b
67}
68
69; CHECK-LABEL: ule_i64:
70; CHECK: sub.f %r6, %r18, %r0
71; CHECK-NEXT: sule %r3
72; CHECK-NEXT: sub.f %r7, %r19, %r0
73; CHECK-NEXT: sule %r9
74; CHECK-NEXT: sub.f %r6, %r18, %r0
75; CHECK-NEXT: sel.eq %r9, %r3, %rv
76define i32 @ule_i64(i64 inreg %x, i64 inreg %y) {
77  %a = icmp ule i64 %x, %y
78  %b = zext i1 %a to i32
79  ret i32 %b
80}
81
82; CHECK-LABEL: sgt_i64:
83; CHECK: sub.f %r6, %r18, %r0
84; CHECK-NEXT: sgt %r3
85; CHECK-NEXT: sub.f %r7, %r19, %r0
86; CHECK-NEXT: sugt %r9
87; CHECK-NEXT: sub.f %r6, %r18, %r0
88; CHECK-NEXT: sel.eq %r9, %r3, %rv
89define i32 @sgt_i64(i64 inreg %x, i64 inreg %y) {
90  %a = icmp sgt i64 %x, %y
91  %b = zext i1 %a to i32
92  ret i32 %b
93}
94
95; CHECK-LABEL: sge_i64:
96; CHECK: sub.f %r6, %r18, %r0
97; CHECK-NEXT: sge %r3
98; CHECK-NEXT: sub.f %r7, %r19, %r0
99; CHECK-NEXT: suge %r9
100; CHECK-NEXT: sub.f %r6, %r18, %r0
101; CHECK-NEXT: sel.eq %r9, %r3, %rv
102define i32 @sge_i64(i64 inreg %x, i64 inreg %y) {
103  %a = icmp sge i64 %x, %y
104  %b = zext i1 %a to i32
105  ret i32 %b
106}
107
108; CHECK-LABEL: ugt_i64:
109; CHECK: sub.f %r6, %r18, %r0
110; CHECK-NEXT: sugt %r3
111; CHECK-NEXT: sub.f %r7, %r19, %r0
112; CHECK-NEXT: sugt %r9
113; CHECK-NEXT: sub.f %r6, %r18, %r0
114; CHECK-NEXT: sel.eq %r9, %r3, %rv
115define i32 @ugt_i64(i64 inreg %x, i64 inreg %y) {
116  %a = icmp ugt i64 %x, %y
117  %b = zext i1 %a to i32
118  ret i32 %b
119}
120
121; CHECK-LABEL: uge_i64:
122; CHECK: sub.f %r6, %r18, %r0
123; CHECK-NEXT: suge %r3
124; CHECK-NEXT: sub.f %r7, %r19, %r0
125; CHECK-NEXT: suge %r9
126; CHECK-NEXT: sub.f %r6, %r18, %r0
127; CHECK-NEXT: sel.eq %r9, %r3, %rv
128define i32 @uge_i64(i64 inreg %x, i64 inreg %y) {
129  %a = icmp uge i64 %x, %y
130  %b = zext i1 %a to i32
131  ret i32 %b
132}
133