1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 -relocation-model=pic | FileCheck %s \
3; RUN:    -check-prefix=MIPS2
4; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 -relocation-model=pic | FileCheck %s \
5; RUN:    -check-prefix=MIPS32
6; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \
7; RUN:    -check-prefix=MIPS32R2
8; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \
9; RUN:    -check-prefix=MIPS32R2
10; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \
11; RUN:    -check-prefix=MIPS32R2
12; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \
13; RUN:    -check-prefix=MIPS32R6
14; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 -relocation-model=pic | FileCheck %s \
15; RUN:    -check-prefix=MIPS3
16; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 -relocation-model=pic | FileCheck %s \
17; RUN:    -check-prefix=MIPS4
18; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 -relocation-model=pic | FileCheck %s \
19; RUN:    -check-prefix=MIPS64
20; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \
21; RUN:    -check-prefix=MIPS64R2
22; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \
23; RUN:    -check-prefix=MIPS64R2
24; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \
25; RUN:    -check-prefix=MIPS64R2
26; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \
27; RUN:    -check-prefix=MIPS64R6
28; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \
29; RUN:    -check-prefix=MMR3
30; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
31; RUN:    -check-prefix=MMR6
32
33define signext i1 @lshr_i1(i1 signext %a, i1 signext %b) {
34; MIPS2-LABEL: lshr_i1:
35; MIPS2:       # %bb.0: # %entry
36; MIPS2-NEXT:    jr $ra
37; MIPS2-NEXT:    move $2, $4
38;
39; MIPS32-LABEL: lshr_i1:
40; MIPS32:       # %bb.0: # %entry
41; MIPS32-NEXT:    jr $ra
42; MIPS32-NEXT:    move $2, $4
43;
44; MIPS32R2-LABEL: lshr_i1:
45; MIPS32R2:       # %bb.0: # %entry
46; MIPS32R2-NEXT:    jr $ra
47; MIPS32R2-NEXT:    move $2, $4
48;
49; MIPS32R6-LABEL: lshr_i1:
50; MIPS32R6:       # %bb.0: # %entry
51; MIPS32R6-NEXT:    jr $ra
52; MIPS32R6-NEXT:    move $2, $4
53;
54; MIPS3-LABEL: lshr_i1:
55; MIPS3:       # %bb.0: # %entry
56; MIPS3-NEXT:    jr $ra
57; MIPS3-NEXT:    move $2, $4
58;
59; MIPS4-LABEL: lshr_i1:
60; MIPS4:       # %bb.0: # %entry
61; MIPS4-NEXT:    jr $ra
62; MIPS4-NEXT:    move $2, $4
63;
64; MIPS64-LABEL: lshr_i1:
65; MIPS64:       # %bb.0: # %entry
66; MIPS64-NEXT:    jr $ra
67; MIPS64-NEXT:    move $2, $4
68;
69; MIPS64R2-LABEL: lshr_i1:
70; MIPS64R2:       # %bb.0: # %entry
71; MIPS64R2-NEXT:    jr $ra
72; MIPS64R2-NEXT:    move $2, $4
73;
74; MIPS64R6-LABEL: lshr_i1:
75; MIPS64R6:       # %bb.0: # %entry
76; MIPS64R6-NEXT:    jr $ra
77; MIPS64R6-NEXT:    move $2, $4
78;
79; MMR3-LABEL: lshr_i1:
80; MMR3:       # %bb.0: # %entry
81; MMR3-NEXT:    move $2, $4
82; MMR3-NEXT:    jrc $ra
83;
84; MMR6-LABEL: lshr_i1:
85; MMR6:       # %bb.0: # %entry
86; MMR6-NEXT:    move $2, $4
87; MMR6-NEXT:    jrc $ra
88entry:
89
90  %r = lshr i1 %a, %b
91  ret i1 %r
92}
93
94define zeroext i8 @lshr_i8(i8 zeroext %a, i8 zeroext %b) {
95; MIPS2-LABEL: lshr_i8:
96; MIPS2:       # %bb.0: # %entry
97; MIPS2-NEXT:    jr $ra
98; MIPS2-NEXT:    srlv $2, $4, $5
99;
100; MIPS32-LABEL: lshr_i8:
101; MIPS32:       # %bb.0: # %entry
102; MIPS32-NEXT:    jr $ra
103; MIPS32-NEXT:    srlv $2, $4, $5
104;
105; MIPS32R2-LABEL: lshr_i8:
106; MIPS32R2:       # %bb.0: # %entry
107; MIPS32R2-NEXT:    jr $ra
108; MIPS32R2-NEXT:    srlv $2, $4, $5
109;
110; MIPS32R6-LABEL: lshr_i8:
111; MIPS32R6:       # %bb.0: # %entry
112; MIPS32R6-NEXT:    jr $ra
113; MIPS32R6-NEXT:    srlv $2, $4, $5
114;
115; MIPS3-LABEL: lshr_i8:
116; MIPS3:       # %bb.0: # %entry
117; MIPS3-NEXT:    jr $ra
118; MIPS3-NEXT:    srlv $2, $4, $5
119;
120; MIPS4-LABEL: lshr_i8:
121; MIPS4:       # %bb.0: # %entry
122; MIPS4-NEXT:    jr $ra
123; MIPS4-NEXT:    srlv $2, $4, $5
124;
125; MIPS64-LABEL: lshr_i8:
126; MIPS64:       # %bb.0: # %entry
127; MIPS64-NEXT:    jr $ra
128; MIPS64-NEXT:    srlv $2, $4, $5
129;
130; MIPS64R2-LABEL: lshr_i8:
131; MIPS64R2:       # %bb.0: # %entry
132; MIPS64R2-NEXT:    jr $ra
133; MIPS64R2-NEXT:    srlv $2, $4, $5
134;
135; MIPS64R6-LABEL: lshr_i8:
136; MIPS64R6:       # %bb.0: # %entry
137; MIPS64R6-NEXT:    jr $ra
138; MIPS64R6-NEXT:    srlv $2, $4, $5
139;
140; MMR3-LABEL: lshr_i8:
141; MMR3:       # %bb.0: # %entry
142; MMR3-NEXT:    jr $ra
143; MMR3-NEXT:    srlv $2, $4, $5
144;
145; MMR6-LABEL: lshr_i8:
146; MMR6:       # %bb.0: # %entry
147; MMR6-NEXT:    srlv $2, $4, $5
148; MMR6-NEXT:    jrc $ra
149entry:
150
151  %r = lshr i8 %a, %b
152  ret i8 %r
153}
154
155define zeroext i16 @lshr_i16(i16 zeroext %a, i16 zeroext %b) {
156; MIPS2-LABEL: lshr_i16:
157; MIPS2:       # %bb.0: # %entry
158; MIPS2-NEXT:    jr $ra
159; MIPS2-NEXT:    srlv $2, $4, $5
160;
161; MIPS32-LABEL: lshr_i16:
162; MIPS32:       # %bb.0: # %entry
163; MIPS32-NEXT:    jr $ra
164; MIPS32-NEXT:    srlv $2, $4, $5
165;
166; MIPS32R2-LABEL: lshr_i16:
167; MIPS32R2:       # %bb.0: # %entry
168; MIPS32R2-NEXT:    jr $ra
169; MIPS32R2-NEXT:    srlv $2, $4, $5
170;
171; MIPS32R6-LABEL: lshr_i16:
172; MIPS32R6:       # %bb.0: # %entry
173; MIPS32R6-NEXT:    jr $ra
174; MIPS32R6-NEXT:    srlv $2, $4, $5
175;
176; MIPS3-LABEL: lshr_i16:
177; MIPS3:       # %bb.0: # %entry
178; MIPS3-NEXT:    jr $ra
179; MIPS3-NEXT:    srlv $2, $4, $5
180;
181; MIPS4-LABEL: lshr_i16:
182; MIPS4:       # %bb.0: # %entry
183; MIPS4-NEXT:    jr $ra
184; MIPS4-NEXT:    srlv $2, $4, $5
185;
186; MIPS64-LABEL: lshr_i16:
187; MIPS64:       # %bb.0: # %entry
188; MIPS64-NEXT:    jr $ra
189; MIPS64-NEXT:    srlv $2, $4, $5
190;
191; MIPS64R2-LABEL: lshr_i16:
192; MIPS64R2:       # %bb.0: # %entry
193; MIPS64R2-NEXT:    jr $ra
194; MIPS64R2-NEXT:    srlv $2, $4, $5
195;
196; MIPS64R6-LABEL: lshr_i16:
197; MIPS64R6:       # %bb.0: # %entry
198; MIPS64R6-NEXT:    jr $ra
199; MIPS64R6-NEXT:    srlv $2, $4, $5
200;
201; MMR3-LABEL: lshr_i16:
202; MMR3:       # %bb.0: # %entry
203; MMR3-NEXT:    jr $ra
204; MMR3-NEXT:    srlv $2, $4, $5
205;
206; MMR6-LABEL: lshr_i16:
207; MMR6:       # %bb.0: # %entry
208; MMR6-NEXT:    srlv $2, $4, $5
209; MMR6-NEXT:    jrc $ra
210entry:
211
212  %r = lshr i16 %a, %b
213  ret i16 %r
214}
215
216define signext i32 @lshr_i32(i32 signext %a, i32 signext %b) {
217; MIPS2-LABEL: lshr_i32:
218; MIPS2:       # %bb.0: # %entry
219; MIPS2-NEXT:    jr $ra
220; MIPS2-NEXT:    srlv $2, $4, $5
221;
222; MIPS32-LABEL: lshr_i32:
223; MIPS32:       # %bb.0: # %entry
224; MIPS32-NEXT:    jr $ra
225; MIPS32-NEXT:    srlv $2, $4, $5
226;
227; MIPS32R2-LABEL: lshr_i32:
228; MIPS32R2:       # %bb.0: # %entry
229; MIPS32R2-NEXT:    jr $ra
230; MIPS32R2-NEXT:    srlv $2, $4, $5
231;
232; MIPS32R6-LABEL: lshr_i32:
233; MIPS32R6:       # %bb.0: # %entry
234; MIPS32R6-NEXT:    jr $ra
235; MIPS32R6-NEXT:    srlv $2, $4, $5
236;
237; MIPS3-LABEL: lshr_i32:
238; MIPS3:       # %bb.0: # %entry
239; MIPS3-NEXT:    jr $ra
240; MIPS3-NEXT:    srlv $2, $4, $5
241;
242; MIPS4-LABEL: lshr_i32:
243; MIPS4:       # %bb.0: # %entry
244; MIPS4-NEXT:    jr $ra
245; MIPS4-NEXT:    srlv $2, $4, $5
246;
247; MIPS64-LABEL: lshr_i32:
248; MIPS64:       # %bb.0: # %entry
249; MIPS64-NEXT:    jr $ra
250; MIPS64-NEXT:    srlv $2, $4, $5
251;
252; MIPS64R2-LABEL: lshr_i32:
253; MIPS64R2:       # %bb.0: # %entry
254; MIPS64R2-NEXT:    jr $ra
255; MIPS64R2-NEXT:    srlv $2, $4, $5
256;
257; MIPS64R6-LABEL: lshr_i32:
258; MIPS64R6:       # %bb.0: # %entry
259; MIPS64R6-NEXT:    jr $ra
260; MIPS64R6-NEXT:    srlv $2, $4, $5
261;
262; MMR3-LABEL: lshr_i32:
263; MMR3:       # %bb.0: # %entry
264; MMR3-NEXT:    jr $ra
265; MMR3-NEXT:    srlv $2, $4, $5
266;
267; MMR6-LABEL: lshr_i32:
268; MMR6:       # %bb.0: # %entry
269; MMR6-NEXT:    srlv $2, $4, $5
270; MMR6-NEXT:    jrc $ra
271entry:
272
273  %r = lshr i32 %a, %b
274  ret i32 %r
275}
276
277define signext i64 @lshr_i64(i64 signext %a, i64 signext %b) {
278; MIPS2-LABEL: lshr_i64:
279; MIPS2:       # %bb.0: # %entry
280; MIPS2-NEXT:    srlv $6, $4, $7
281; MIPS2-NEXT:    andi $1, $7, 32
282; MIPS2-NEXT:    bnez $1, $BB4_2
283; MIPS2-NEXT:    addiu $2, $zero, 0
284; MIPS2-NEXT:  # %bb.1: # %entry
285; MIPS2-NEXT:    srlv $1, $5, $7
286; MIPS2-NEXT:    not $2, $7
287; MIPS2-NEXT:    sll $3, $4, 1
288; MIPS2-NEXT:    sllv $2, $3, $2
289; MIPS2-NEXT:    or $3, $2, $1
290; MIPS2-NEXT:    jr $ra
291; MIPS2-NEXT:    move $2, $6
292; MIPS2-NEXT:  $BB4_2:
293; MIPS2-NEXT:    jr $ra
294; MIPS2-NEXT:    move $3, $6
295;
296; MIPS32-LABEL: lshr_i64:
297; MIPS32:       # %bb.0: # %entry
298; MIPS32-NEXT:    srlv $1, $5, $7
299; MIPS32-NEXT:    not $2, $7
300; MIPS32-NEXT:    sll $3, $4, 1
301; MIPS32-NEXT:    sllv $2, $3, $2
302; MIPS32-NEXT:    or $3, $2, $1
303; MIPS32-NEXT:    srlv $2, $4, $7
304; MIPS32-NEXT:    andi $1, $7, 32
305; MIPS32-NEXT:    movn $3, $2, $1
306; MIPS32-NEXT:    jr $ra
307; MIPS32-NEXT:    movn $2, $zero, $1
308;
309; MIPS32R2-LABEL: lshr_i64:
310; MIPS32R2:       # %bb.0: # %entry
311; MIPS32R2-NEXT:    srlv $1, $5, $7
312; MIPS32R2-NEXT:    not $2, $7
313; MIPS32R2-NEXT:    sll $3, $4, 1
314; MIPS32R2-NEXT:    sllv $2, $3, $2
315; MIPS32R2-NEXT:    or $3, $2, $1
316; MIPS32R2-NEXT:    srlv $2, $4, $7
317; MIPS32R2-NEXT:    andi $1, $7, 32
318; MIPS32R2-NEXT:    movn $3, $2, $1
319; MIPS32R2-NEXT:    jr $ra
320; MIPS32R2-NEXT:    movn $2, $zero, $1
321;
322; MIPS32R6-LABEL: lshr_i64:
323; MIPS32R6:       # %bb.0: # %entry
324; MIPS32R6-NEXT:    srlv $1, $5, $7
325; MIPS32R6-NEXT:    not $2, $7
326; MIPS32R6-NEXT:    sll $3, $4, 1
327; MIPS32R6-NEXT:    sllv $2, $3, $2
328; MIPS32R6-NEXT:    or $1, $2, $1
329; MIPS32R6-NEXT:    andi $2, $7, 32
330; MIPS32R6-NEXT:    seleqz $1, $1, $2
331; MIPS32R6-NEXT:    srlv $4, $4, $7
332; MIPS32R6-NEXT:    selnez $3, $4, $2
333; MIPS32R6-NEXT:    or $3, $3, $1
334; MIPS32R6-NEXT:    jr $ra
335; MIPS32R6-NEXT:    seleqz $2, $4, $2
336;
337; MIPS3-LABEL: lshr_i64:
338; MIPS3:       # %bb.0: # %entry
339; MIPS3-NEXT:    jr $ra
340; MIPS3-NEXT:    dsrlv $2, $4, $5
341;
342; MIPS4-LABEL: lshr_i64:
343; MIPS4:       # %bb.0: # %entry
344; MIPS4-NEXT:    jr $ra
345; MIPS4-NEXT:    dsrlv $2, $4, $5
346;
347; MIPS64-LABEL: lshr_i64:
348; MIPS64:       # %bb.0: # %entry
349; MIPS64-NEXT:    jr $ra
350; MIPS64-NEXT:    dsrlv $2, $4, $5
351;
352; MIPS64R2-LABEL: lshr_i64:
353; MIPS64R2:       # %bb.0: # %entry
354; MIPS64R2-NEXT:    jr $ra
355; MIPS64R2-NEXT:    dsrlv $2, $4, $5
356;
357; MIPS64R6-LABEL: lshr_i64:
358; MIPS64R6:       # %bb.0: # %entry
359; MIPS64R6-NEXT:    jr $ra
360; MIPS64R6-NEXT:    dsrlv $2, $4, $5
361;
362; MMR3-LABEL: lshr_i64:
363; MMR3:       # %bb.0: # %entry
364; MMR3-NEXT:    srlv $2, $5, $7
365; MMR3-NEXT:    not16 $3, $7
366; MMR3-NEXT:    sll16 $5, $4, 1
367; MMR3-NEXT:    sllv $3, $5, $3
368; MMR3-NEXT:    or16 $3, $2
369; MMR3-NEXT:    srlv $2, $4, $7
370; MMR3-NEXT:    andi16 $4, $7, 32
371; MMR3-NEXT:    movn $3, $2, $4
372; MMR3-NEXT:    li16 $5, 0
373; MMR3-NEXT:    jr $ra
374; MMR3-NEXT:    movn $2, $5, $4
375;
376; MMR6-LABEL: lshr_i64:
377; MMR6:       # %bb.0: # %entry
378; MMR6-NEXT:    srlv $1, $5, $7
379; MMR6-NEXT:    not16 $2, $7
380; MMR6-NEXT:    sll16 $3, $4, 1
381; MMR6-NEXT:    sllv $2, $3, $2
382; MMR6-NEXT:    or $1, $2, $1
383; MMR6-NEXT:    andi16 $2, $7, 32
384; MMR6-NEXT:    seleqz $1, $1, $2
385; MMR6-NEXT:    srlv $4, $4, $7
386; MMR6-NEXT:    selnez $3, $4, $2
387; MMR6-NEXT:    or $3, $3, $1
388; MMR6-NEXT:    seleqz $2, $4, $2
389; MMR6-NEXT:    jrc $ra
390entry:
391
392  %r = lshr i64 %a, %b
393  ret i64 %r
394}
395
396define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
397; MIPS2-LABEL: lshr_i128:
398; MIPS2:       # %bb.0: # %entry
399; MIPS2-NEXT:    lw $2, 28($sp)
400; MIPS2-NEXT:    addiu $1, $zero, 64
401; MIPS2-NEXT:    subu $12, $1, $2
402; MIPS2-NEXT:    sllv $10, $5, $12
403; MIPS2-NEXT:    andi $15, $12, 32
404; MIPS2-NEXT:    andi $8, $2, 32
405; MIPS2-NEXT:    addiu $3, $zero, 0
406; MIPS2-NEXT:    bnez $15, $BB5_2
407; MIPS2-NEXT:    addiu $13, $zero, 0
408; MIPS2-NEXT:  # %bb.1: # %entry
409; MIPS2-NEXT:    move $13, $10
410; MIPS2-NEXT:  $BB5_2: # %entry
411; MIPS2-NEXT:    not $9, $2
412; MIPS2-NEXT:    bnez $8, $BB5_5
413; MIPS2-NEXT:    srlv $24, $6, $2
414; MIPS2-NEXT:  # %bb.3: # %entry
415; MIPS2-NEXT:    sll $1, $6, 1
416; MIPS2-NEXT:    srlv $11, $7, $2
417; MIPS2-NEXT:    sllv $1, $1, $9
418; MIPS2-NEXT:    or $14, $1, $11
419; MIPS2-NEXT:    bnez $15, $BB5_7
420; MIPS2-NEXT:    move $11, $24
421; MIPS2-NEXT:  # %bb.4: # %entry
422; MIPS2-NEXT:    b $BB5_6
423; MIPS2-NEXT:    nop
424; MIPS2-NEXT:  $BB5_5:
425; MIPS2-NEXT:    addiu $11, $zero, 0
426; MIPS2-NEXT:    bnez $15, $BB5_7
427; MIPS2-NEXT:    move $14, $24
428; MIPS2-NEXT:  $BB5_6: # %entry
429; MIPS2-NEXT:    sllv $1, $4, $12
430; MIPS2-NEXT:    not $10, $12
431; MIPS2-NEXT:    srl $12, $5, 1
432; MIPS2-NEXT:    srlv $10, $12, $10
433; MIPS2-NEXT:    or $10, $1, $10
434; MIPS2-NEXT:  $BB5_7: # %entry
435; MIPS2-NEXT:    addiu $15, $2, -64
436; MIPS2-NEXT:    sll $12, $4, 1
437; MIPS2-NEXT:    andi $1, $15, 32
438; MIPS2-NEXT:    bnez $1, $BB5_10
439; MIPS2-NEXT:    srlv $25, $4, $15
440; MIPS2-NEXT:  # %bb.8: # %entry
441; MIPS2-NEXT:    srlv $1, $5, $15
442; MIPS2-NEXT:    not $15, $15
443; MIPS2-NEXT:    sllv $15, $12, $15
444; MIPS2-NEXT:    or $24, $15, $1
445; MIPS2-NEXT:    move $15, $25
446; MIPS2-NEXT:    sltiu $25, $2, 64
447; MIPS2-NEXT:    beqz $25, $BB5_12
448; MIPS2-NEXT:    nop
449; MIPS2-NEXT:  # %bb.9: # %entry
450; MIPS2-NEXT:    b $BB5_11
451; MIPS2-NEXT:    nop
452; MIPS2-NEXT:  $BB5_10:
453; MIPS2-NEXT:    move $24, $25
454; MIPS2-NEXT:    sltiu $25, $2, 64
455; MIPS2-NEXT:    beqz $25, $BB5_12
456; MIPS2-NEXT:    addiu $15, $zero, 0
457; MIPS2-NEXT:  $BB5_11:
458; MIPS2-NEXT:    or $24, $14, $13
459; MIPS2-NEXT:  $BB5_12: # %entry
460; MIPS2-NEXT:    sltiu $13, $2, 1
461; MIPS2-NEXT:    beqz $13, $BB5_19
462; MIPS2-NEXT:    nop
463; MIPS2-NEXT:  # %bb.13: # %entry
464; MIPS2-NEXT:    bnez $25, $BB5_20
465; MIPS2-NEXT:    nop
466; MIPS2-NEXT:  $BB5_14: # %entry
467; MIPS2-NEXT:    bnez $13, $BB5_16
468; MIPS2-NEXT:    addiu $10, $zero, 63
469; MIPS2-NEXT:  $BB5_15: # %entry
470; MIPS2-NEXT:    move $6, $15
471; MIPS2-NEXT:  $BB5_16: # %entry
472; MIPS2-NEXT:    sltu $10, $10, $2
473; MIPS2-NEXT:    bnez $8, $BB5_22
474; MIPS2-NEXT:    srlv $11, $4, $2
475; MIPS2-NEXT:  # %bb.17: # %entry
476; MIPS2-NEXT:    srlv $1, $5, $2
477; MIPS2-NEXT:    sllv $2, $12, $9
478; MIPS2-NEXT:    or $4, $2, $1
479; MIPS2-NEXT:    move $5, $11
480; MIPS2-NEXT:    bnez $10, $BB5_24
481; MIPS2-NEXT:    addiu $2, $zero, 0
482; MIPS2-NEXT:  # %bb.18: # %entry
483; MIPS2-NEXT:    b $BB5_23
484; MIPS2-NEXT:    nop
485; MIPS2-NEXT:  $BB5_19: # %entry
486; MIPS2-NEXT:    beqz $25, $BB5_14
487; MIPS2-NEXT:    move $7, $24
488; MIPS2-NEXT:  $BB5_20:
489; MIPS2-NEXT:    or $15, $11, $10
490; MIPS2-NEXT:    bnez $13, $BB5_16
491; MIPS2-NEXT:    addiu $10, $zero, 63
492; MIPS2-NEXT:  # %bb.21:
493; MIPS2-NEXT:    b $BB5_15
494; MIPS2-NEXT:    nop
495; MIPS2-NEXT:  $BB5_22:
496; MIPS2-NEXT:    addiu $5, $zero, 0
497; MIPS2-NEXT:    move $4, $11
498; MIPS2-NEXT:    bnez $10, $BB5_24
499; MIPS2-NEXT:    addiu $2, $zero, 0
500; MIPS2-NEXT:  $BB5_23: # %entry
501; MIPS2-NEXT:    move $2, $5
502; MIPS2-NEXT:  $BB5_24: # %entry
503; MIPS2-NEXT:    bnez $10, $BB5_26
504; MIPS2-NEXT:    nop
505; MIPS2-NEXT:  # %bb.25: # %entry
506; MIPS2-NEXT:    move $3, $4
507; MIPS2-NEXT:  $BB5_26: # %entry
508; MIPS2-NEXT:    move $4, $6
509; MIPS2-NEXT:    jr $ra
510; MIPS2-NEXT:    move $5, $7
511;
512; MIPS32-LABEL: lshr_i128:
513; MIPS32:       # %bb.0: # %entry
514; MIPS32-NEXT:    lw $9, 28($sp)
515; MIPS32-NEXT:    addiu $1, $zero, 64
516; MIPS32-NEXT:    subu $2, $1, $9
517; MIPS32-NEXT:    sllv $10, $5, $2
518; MIPS32-NEXT:    andi $11, $2, 32
519; MIPS32-NEXT:    move $1, $10
520; MIPS32-NEXT:    movn $1, $zero, $11
521; MIPS32-NEXT:    srlv $3, $7, $9
522; MIPS32-NEXT:    not $12, $9
523; MIPS32-NEXT:    sll $8, $6, 1
524; MIPS32-NEXT:    sllv $8, $8, $12
525; MIPS32-NEXT:    or $3, $8, $3
526; MIPS32-NEXT:    srlv $13, $6, $9
527; MIPS32-NEXT:    andi $14, $9, 32
528; MIPS32-NEXT:    movn $3, $13, $14
529; MIPS32-NEXT:    addiu $15, $9, -64
530; MIPS32-NEXT:    or $3, $3, $1
531; MIPS32-NEXT:    srlv $1, $5, $15
532; MIPS32-NEXT:    sll $24, $4, 1
533; MIPS32-NEXT:    not $8, $15
534; MIPS32-NEXT:    sllv $8, $24, $8
535; MIPS32-NEXT:    or $1, $8, $1
536; MIPS32-NEXT:    srlv $8, $4, $15
537; MIPS32-NEXT:    andi $15, $15, 32
538; MIPS32-NEXT:    movn $1, $8, $15
539; MIPS32-NEXT:    sltiu $25, $9, 64
540; MIPS32-NEXT:    movn $1, $3, $25
541; MIPS32-NEXT:    sllv $3, $4, $2
542; MIPS32-NEXT:    not $2, $2
543; MIPS32-NEXT:    srl $gp, $5, 1
544; MIPS32-NEXT:    srlv $2, $gp, $2
545; MIPS32-NEXT:    or $gp, $3, $2
546; MIPS32-NEXT:    srlv $2, $5, $9
547; MIPS32-NEXT:    sllv $3, $24, $12
548; MIPS32-NEXT:    or $3, $3, $2
549; MIPS32-NEXT:    srlv $2, $4, $9
550; MIPS32-NEXT:    movn $3, $2, $14
551; MIPS32-NEXT:    movz $1, $7, $9
552; MIPS32-NEXT:    movz $3, $zero, $25
553; MIPS32-NEXT:    movn $gp, $10, $11
554; MIPS32-NEXT:    movn $13, $zero, $14
555; MIPS32-NEXT:    or $4, $13, $gp
556; MIPS32-NEXT:    movn $8, $zero, $15
557; MIPS32-NEXT:    movn $8, $4, $25
558; MIPS32-NEXT:    movz $8, $6, $9
559; MIPS32-NEXT:    movn $2, $zero, $14
560; MIPS32-NEXT:    movz $2, $zero, $25
561; MIPS32-NEXT:    move $4, $8
562; MIPS32-NEXT:    jr $ra
563; MIPS32-NEXT:    move $5, $1
564;
565; MIPS32R2-LABEL: lshr_i128:
566; MIPS32R2:       # %bb.0: # %entry
567; MIPS32R2-NEXT:    lw $9, 28($sp)
568; MIPS32R2-NEXT:    addiu $1, $zero, 64
569; MIPS32R2-NEXT:    subu $2, $1, $9
570; MIPS32R2-NEXT:    sllv $10, $5, $2
571; MIPS32R2-NEXT:    andi $11, $2, 32
572; MIPS32R2-NEXT:    move $1, $10
573; MIPS32R2-NEXT:    movn $1, $zero, $11
574; MIPS32R2-NEXT:    srlv $3, $7, $9
575; MIPS32R2-NEXT:    not $12, $9
576; MIPS32R2-NEXT:    sll $8, $6, 1
577; MIPS32R2-NEXT:    sllv $8, $8, $12
578; MIPS32R2-NEXT:    or $3, $8, $3
579; MIPS32R2-NEXT:    srlv $13, $6, $9
580; MIPS32R2-NEXT:    andi $14, $9, 32
581; MIPS32R2-NEXT:    movn $3, $13, $14
582; MIPS32R2-NEXT:    addiu $15, $9, -64
583; MIPS32R2-NEXT:    or $3, $3, $1
584; MIPS32R2-NEXT:    srlv $1, $5, $15
585; MIPS32R2-NEXT:    sll $24, $4, 1
586; MIPS32R2-NEXT:    not $8, $15
587; MIPS32R2-NEXT:    sllv $8, $24, $8
588; MIPS32R2-NEXT:    or $1, $8, $1
589; MIPS32R2-NEXT:    srlv $8, $4, $15
590; MIPS32R2-NEXT:    andi $15, $15, 32
591; MIPS32R2-NEXT:    movn $1, $8, $15
592; MIPS32R2-NEXT:    sltiu $25, $9, 64
593; MIPS32R2-NEXT:    movn $1, $3, $25
594; MIPS32R2-NEXT:    sllv $3, $4, $2
595; MIPS32R2-NEXT:    not $2, $2
596; MIPS32R2-NEXT:    srl $gp, $5, 1
597; MIPS32R2-NEXT:    srlv $2, $gp, $2
598; MIPS32R2-NEXT:    or $gp, $3, $2
599; MIPS32R2-NEXT:    srlv $2, $5, $9
600; MIPS32R2-NEXT:    sllv $3, $24, $12
601; MIPS32R2-NEXT:    or $3, $3, $2
602; MIPS32R2-NEXT:    srlv $2, $4, $9
603; MIPS32R2-NEXT:    movn $3, $2, $14
604; MIPS32R2-NEXT:    movz $1, $7, $9
605; MIPS32R2-NEXT:    movz $3, $zero, $25
606; MIPS32R2-NEXT:    movn $gp, $10, $11
607; MIPS32R2-NEXT:    movn $13, $zero, $14
608; MIPS32R2-NEXT:    or $4, $13, $gp
609; MIPS32R2-NEXT:    movn $8, $zero, $15
610; MIPS32R2-NEXT:    movn $8, $4, $25
611; MIPS32R2-NEXT:    movz $8, $6, $9
612; MIPS32R2-NEXT:    movn $2, $zero, $14
613; MIPS32R2-NEXT:    movz $2, $zero, $25
614; MIPS32R2-NEXT:    move $4, $8
615; MIPS32R2-NEXT:    jr $ra
616; MIPS32R2-NEXT:    move $5, $1
617;
618; MIPS32R6-LABEL: lshr_i128:
619; MIPS32R6:       # %bb.0: # %entry
620; MIPS32R6-NEXT:    addiu $sp, $sp, -8
621; MIPS32R6-NEXT:    .cfi_def_cfa_offset 8
622; MIPS32R6-NEXT:    sw $16, 4($sp) # 4-byte Folded Spill
623; MIPS32R6-NEXT:    .cfi_offset 16, -4
624; MIPS32R6-NEXT:    lw $1, 36($sp)
625; MIPS32R6-NEXT:    srlv $2, $7, $1
626; MIPS32R6-NEXT:    not $3, $1
627; MIPS32R6-NEXT:    sll $8, $6, 1
628; MIPS32R6-NEXT:    sllv $8, $8, $3
629; MIPS32R6-NEXT:    or $2, $8, $2
630; MIPS32R6-NEXT:    addiu $8, $1, -64
631; MIPS32R6-NEXT:    srlv $9, $5, $8
632; MIPS32R6-NEXT:    sll $10, $4, 1
633; MIPS32R6-NEXT:    not $11, $8
634; MIPS32R6-NEXT:    sllv $11, $10, $11
635; MIPS32R6-NEXT:    andi $12, $1, 32
636; MIPS32R6-NEXT:    seleqz $2, $2, $12
637; MIPS32R6-NEXT:    or $9, $11, $9
638; MIPS32R6-NEXT:    srlv $11, $6, $1
639; MIPS32R6-NEXT:    selnez $13, $11, $12
640; MIPS32R6-NEXT:    addiu $14, $zero, 64
641; MIPS32R6-NEXT:    subu $14, $14, $1
642; MIPS32R6-NEXT:    sllv $15, $5, $14
643; MIPS32R6-NEXT:    andi $24, $14, 32
644; MIPS32R6-NEXT:    andi $25, $8, 32
645; MIPS32R6-NEXT:    seleqz $9, $9, $25
646; MIPS32R6-NEXT:    seleqz $gp, $15, $24
647; MIPS32R6-NEXT:    or $2, $13, $2
648; MIPS32R6-NEXT:    selnez $13, $15, $24
649; MIPS32R6-NEXT:    sllv $15, $4, $14
650; MIPS32R6-NEXT:    not $14, $14
651; MIPS32R6-NEXT:    srl $16, $5, 1
652; MIPS32R6-NEXT:    srlv $14, $16, $14
653; MIPS32R6-NEXT:    or $14, $15, $14
654; MIPS32R6-NEXT:    seleqz $14, $14, $24
655; MIPS32R6-NEXT:    srlv $8, $4, $8
656; MIPS32R6-NEXT:    or $13, $13, $14
657; MIPS32R6-NEXT:    or $2, $2, $gp
658; MIPS32R6-NEXT:    srlv $5, $5, $1
659; MIPS32R6-NEXT:    selnez $14, $8, $25
660; MIPS32R6-NEXT:    sltiu $15, $1, 64
661; MIPS32R6-NEXT:    selnez $2, $2, $15
662; MIPS32R6-NEXT:    or $9, $14, $9
663; MIPS32R6-NEXT:    sllv $3, $10, $3
664; MIPS32R6-NEXT:    seleqz $10, $11, $12
665; MIPS32R6-NEXT:    or $10, $10, $13
666; MIPS32R6-NEXT:    or $3, $3, $5
667; MIPS32R6-NEXT:    seleqz $5, $9, $15
668; MIPS32R6-NEXT:    seleqz $9, $zero, $15
669; MIPS32R6-NEXT:    srlv $4, $4, $1
670; MIPS32R6-NEXT:    seleqz $11, $4, $12
671; MIPS32R6-NEXT:    selnez $11, $11, $15
672; MIPS32R6-NEXT:    seleqz $7, $7, $1
673; MIPS32R6-NEXT:    or $2, $2, $5
674; MIPS32R6-NEXT:    selnez $2, $2, $1
675; MIPS32R6-NEXT:    or $5, $7, $2
676; MIPS32R6-NEXT:    or $2, $9, $11
677; MIPS32R6-NEXT:    seleqz $3, $3, $12
678; MIPS32R6-NEXT:    selnez $7, $4, $12
679; MIPS32R6-NEXT:    seleqz $4, $6, $1
680; MIPS32R6-NEXT:    selnez $6, $10, $15
681; MIPS32R6-NEXT:    seleqz $8, $8, $25
682; MIPS32R6-NEXT:    seleqz $8, $8, $15
683; MIPS32R6-NEXT:    or $6, $6, $8
684; MIPS32R6-NEXT:    selnez $1, $6, $1
685; MIPS32R6-NEXT:    or $4, $4, $1
686; MIPS32R6-NEXT:    or $1, $7, $3
687; MIPS32R6-NEXT:    selnez $1, $1, $15
688; MIPS32R6-NEXT:    or $3, $9, $1
689; MIPS32R6-NEXT:    lw $16, 4($sp) # 4-byte Folded Reload
690; MIPS32R6-NEXT:    jr $ra
691; MIPS32R6-NEXT:    addiu $sp, $sp, 8
692;
693; MIPS3-LABEL: lshr_i128:
694; MIPS3:       # %bb.0: # %entry
695; MIPS3-NEXT:    sll $3, $7, 0
696; MIPS3-NEXT:    dsrlv $6, $4, $7
697; MIPS3-NEXT:    andi $1, $3, 64
698; MIPS3-NEXT:    bnez $1, .LBB5_2
699; MIPS3-NEXT:    daddiu $2, $zero, 0
700; MIPS3-NEXT:  # %bb.1: # %entry
701; MIPS3-NEXT:    dsrlv $1, $5, $7
702; MIPS3-NEXT:    dsll $2, $4, 1
703; MIPS3-NEXT:    not $3, $3
704; MIPS3-NEXT:    dsllv $2, $2, $3
705; MIPS3-NEXT:    or $3, $2, $1
706; MIPS3-NEXT:    jr $ra
707; MIPS3-NEXT:    move $2, $6
708; MIPS3-NEXT:  .LBB5_2:
709; MIPS3-NEXT:    jr $ra
710; MIPS3-NEXT:    move $3, $6
711;
712; MIPS4-LABEL: lshr_i128:
713; MIPS4:       # %bb.0: # %entry
714; MIPS4-NEXT:    dsrlv $1, $5, $7
715; MIPS4-NEXT:    dsll $2, $4, 1
716; MIPS4-NEXT:    sll $5, $7, 0
717; MIPS4-NEXT:    not $3, $5
718; MIPS4-NEXT:    dsllv $2, $2, $3
719; MIPS4-NEXT:    or $3, $2, $1
720; MIPS4-NEXT:    dsrlv $2, $4, $7
721; MIPS4-NEXT:    andi $1, $5, 64
722; MIPS4-NEXT:    movn $3, $2, $1
723; MIPS4-NEXT:    jr $ra
724; MIPS4-NEXT:    movn $2, $zero, $1
725;
726; MIPS64-LABEL: lshr_i128:
727; MIPS64:       # %bb.0: # %entry
728; MIPS64-NEXT:    dsrlv $1, $5, $7
729; MIPS64-NEXT:    dsll $2, $4, 1
730; MIPS64-NEXT:    sll $5, $7, 0
731; MIPS64-NEXT:    not $3, $5
732; MIPS64-NEXT:    dsllv $2, $2, $3
733; MIPS64-NEXT:    or $3, $2, $1
734; MIPS64-NEXT:    dsrlv $2, $4, $7
735; MIPS64-NEXT:    andi $1, $5, 64
736; MIPS64-NEXT:    movn $3, $2, $1
737; MIPS64-NEXT:    jr $ra
738; MIPS64-NEXT:    movn $2, $zero, $1
739;
740; MIPS64R2-LABEL: lshr_i128:
741; MIPS64R2:       # %bb.0: # %entry
742; MIPS64R2-NEXT:    dsrlv $1, $5, $7
743; MIPS64R2-NEXT:    dsll $2, $4, 1
744; MIPS64R2-NEXT:    sll $5, $7, 0
745; MIPS64R2-NEXT:    not $3, $5
746; MIPS64R2-NEXT:    dsllv $2, $2, $3
747; MIPS64R2-NEXT:    or $3, $2, $1
748; MIPS64R2-NEXT:    dsrlv $2, $4, $7
749; MIPS64R2-NEXT:    andi $1, $5, 64
750; MIPS64R2-NEXT:    movn $3, $2, $1
751; MIPS64R2-NEXT:    jr $ra
752; MIPS64R2-NEXT:    movn $2, $zero, $1
753;
754; MIPS64R6-LABEL: lshr_i128:
755; MIPS64R6:       # %bb.0: # %entry
756; MIPS64R6-NEXT:    dsrlv $1, $5, $7
757; MIPS64R6-NEXT:    dsll $2, $4, 1
758; MIPS64R6-NEXT:    sll $3, $7, 0
759; MIPS64R6-NEXT:    not $5, $3
760; MIPS64R6-NEXT:    dsllv $2, $2, $5
761; MIPS64R6-NEXT:    or $1, $2, $1
762; MIPS64R6-NEXT:    andi $2, $3, 64
763; MIPS64R6-NEXT:    sll $2, $2, 0
764; MIPS64R6-NEXT:    seleqz $1, $1, $2
765; MIPS64R6-NEXT:    dsrlv $4, $4, $7
766; MIPS64R6-NEXT:    selnez $3, $4, $2
767; MIPS64R6-NEXT:    or $3, $3, $1
768; MIPS64R6-NEXT:    jr $ra
769; MIPS64R6-NEXT:    seleqz $2, $4, $2
770;
771; MMR3-LABEL: lshr_i128:
772; MMR3:       # %bb.0: # %entry
773; MMR3-NEXT:    addiusp -40
774; MMR3-NEXT:    .cfi_def_cfa_offset 40
775; MMR3-NEXT:    swp $16, 32($sp)
776; MMR3-NEXT:    .cfi_offset 17, -4
777; MMR3-NEXT:    .cfi_offset 16, -8
778; MMR3-NEXT:    move $8, $7
779; MMR3-NEXT:    sw $6, 24($sp) # 4-byte Folded Spill
780; MMR3-NEXT:    sw $4, 28($sp) # 4-byte Folded Spill
781; MMR3-NEXT:    lw $16, 68($sp)
782; MMR3-NEXT:    li16 $2, 64
783; MMR3-NEXT:    subu16 $7, $2, $16
784; MMR3-NEXT:    sllv $9, $5, $7
785; MMR3-NEXT:    move $17, $5
786; MMR3-NEXT:    sw $5, 0($sp) # 4-byte Folded Spill
787; MMR3-NEXT:    andi16 $3, $7, 32
788; MMR3-NEXT:    sw $3, 20($sp) # 4-byte Folded Spill
789; MMR3-NEXT:    li16 $2, 0
790; MMR3-NEXT:    move $4, $9
791; MMR3-NEXT:    movn $4, $2, $3
792; MMR3-NEXT:    srlv $5, $8, $16
793; MMR3-NEXT:    not16 $3, $16
794; MMR3-NEXT:    sw $3, 16($sp) # 4-byte Folded Spill
795; MMR3-NEXT:    sll16 $2, $6, 1
796; MMR3-NEXT:    sllv $2, $2, $3
797; MMR3-NEXT:    or16 $2, $5
798; MMR3-NEXT:    srlv $5, $6, $16
799; MMR3-NEXT:    sw $5, 4($sp) # 4-byte Folded Spill
800; MMR3-NEXT:    andi16 $3, $16, 32
801; MMR3-NEXT:    sw $3, 12($sp) # 4-byte Folded Spill
802; MMR3-NEXT:    movn $2, $5, $3
803; MMR3-NEXT:    addiu $3, $16, -64
804; MMR3-NEXT:    or16 $2, $4
805; MMR3-NEXT:    srlv $4, $17, $3
806; MMR3-NEXT:    sw $4, 8($sp) # 4-byte Folded Spill
807; MMR3-NEXT:    lw $4, 28($sp) # 4-byte Folded Reload
808; MMR3-NEXT:    sll16 $6, $4, 1
809; MMR3-NEXT:    not16 $5, $3
810; MMR3-NEXT:    sllv $5, $6, $5
811; MMR3-NEXT:    lw $17, 8($sp) # 4-byte Folded Reload
812; MMR3-NEXT:    or16 $5, $17
813; MMR3-NEXT:    srlv $1, $4, $3
814; MMR3-NEXT:    andi16 $3, $3, 32
815; MMR3-NEXT:    sw $3, 8($sp) # 4-byte Folded Spill
816; MMR3-NEXT:    movn $5, $1, $3
817; MMR3-NEXT:    sltiu $10, $16, 64
818; MMR3-NEXT:    movn $5, $2, $10
819; MMR3-NEXT:    sllv $2, $4, $7
820; MMR3-NEXT:    not16 $3, $7
821; MMR3-NEXT:    lw $7, 0($sp) # 4-byte Folded Reload
822; MMR3-NEXT:    srl16 $4, $7, 1
823; MMR3-NEXT:    srlv $4, $4, $3
824; MMR3-NEXT:    or16 $4, $2
825; MMR3-NEXT:    srlv $2, $7, $16
826; MMR3-NEXT:    lw $3, 16($sp) # 4-byte Folded Reload
827; MMR3-NEXT:    sllv $3, $6, $3
828; MMR3-NEXT:    or16 $3, $2
829; MMR3-NEXT:    lw $2, 28($sp) # 4-byte Folded Reload
830; MMR3-NEXT:    srlv $2, $2, $16
831; MMR3-NEXT:    lw $17, 12($sp) # 4-byte Folded Reload
832; MMR3-NEXT:    movn $3, $2, $17
833; MMR3-NEXT:    movz $5, $8, $16
834; MMR3-NEXT:    li16 $6, 0
835; MMR3-NEXT:    movz $3, $6, $10
836; MMR3-NEXT:    lw $7, 20($sp) # 4-byte Folded Reload
837; MMR3-NEXT:    movn $4, $9, $7
838; MMR3-NEXT:    lw $6, 4($sp) # 4-byte Folded Reload
839; MMR3-NEXT:    li16 $7, 0
840; MMR3-NEXT:    movn $6, $7, $17
841; MMR3-NEXT:    or16 $6, $4
842; MMR3-NEXT:    lw $4, 8($sp) # 4-byte Folded Reload
843; MMR3-NEXT:    movn $1, $7, $4
844; MMR3-NEXT:    li16 $7, 0
845; MMR3-NEXT:    movn $1, $6, $10
846; MMR3-NEXT:    lw $4, 24($sp) # 4-byte Folded Reload
847; MMR3-NEXT:    movz $1, $4, $16
848; MMR3-NEXT:    movn $2, $7, $17
849; MMR3-NEXT:    li16 $4, 0
850; MMR3-NEXT:    movz $2, $4, $10
851; MMR3-NEXT:    move $4, $1
852; MMR3-NEXT:    lwp $16, 32($sp)
853; MMR3-NEXT:    addiusp 40
854; MMR3-NEXT:    jrc $ra
855;
856; MMR6-LABEL: lshr_i128:
857; MMR6:       # %bb.0: # %entry
858; MMR6-NEXT:    addiu $sp, $sp, -32
859; MMR6-NEXT:    .cfi_def_cfa_offset 32
860; MMR6-NEXT:    sw $17, 28($sp) # 4-byte Folded Spill
861; MMR6-NEXT:    sw $16, 24($sp) # 4-byte Folded Spill
862; MMR6-NEXT:    .cfi_offset 17, -4
863; MMR6-NEXT:    .cfi_offset 16, -8
864; MMR6-NEXT:    move $1, $7
865; MMR6-NEXT:    move $7, $5
866; MMR6-NEXT:    lw $3, 60($sp)
867; MMR6-NEXT:    srlv $2, $1, $3
868; MMR6-NEXT:    not16 $5, $3
869; MMR6-NEXT:    sw $5, 12($sp) # 4-byte Folded Spill
870; MMR6-NEXT:    move $17, $6
871; MMR6-NEXT:    sw $6, 16($sp) # 4-byte Folded Spill
872; MMR6-NEXT:    sll16 $6, $6, 1
873; MMR6-NEXT:    sllv $6, $6, $5
874; MMR6-NEXT:    or $8, $6, $2
875; MMR6-NEXT:    addiu $5, $3, -64
876; MMR6-NEXT:    srlv $9, $7, $5
877; MMR6-NEXT:    move $6, $4
878; MMR6-NEXT:    sll16 $2, $4, 1
879; MMR6-NEXT:    sw $2, 8($sp) # 4-byte Folded Spill
880; MMR6-NEXT:    not16 $16, $5
881; MMR6-NEXT:    sllv $10, $2, $16
882; MMR6-NEXT:    andi16 $16, $3, 32
883; MMR6-NEXT:    seleqz $8, $8, $16
884; MMR6-NEXT:    or $9, $10, $9
885; MMR6-NEXT:    srlv $10, $17, $3
886; MMR6-NEXT:    selnez $11, $10, $16
887; MMR6-NEXT:    li16 $17, 64
888; MMR6-NEXT:    subu16 $2, $17, $3
889; MMR6-NEXT:    sllv $12, $7, $2
890; MMR6-NEXT:    move $17, $7
891; MMR6-NEXT:    andi16 $4, $2, 32
892; MMR6-NEXT:    andi16 $7, $5, 32
893; MMR6-NEXT:    sw $7, 20($sp) # 4-byte Folded Spill
894; MMR6-NEXT:    seleqz $9, $9, $7
895; MMR6-NEXT:    seleqz $13, $12, $4
896; MMR6-NEXT:    or $8, $11, $8
897; MMR6-NEXT:    selnez $11, $12, $4
898; MMR6-NEXT:    sllv $12, $6, $2
899; MMR6-NEXT:    move $7, $6
900; MMR6-NEXT:    sw $6, 4($sp) # 4-byte Folded Spill
901; MMR6-NEXT:    not16 $2, $2
902; MMR6-NEXT:    srl16 $6, $17, 1
903; MMR6-NEXT:    srlv $2, $6, $2
904; MMR6-NEXT:    or $2, $12, $2
905; MMR6-NEXT:    seleqz $2, $2, $4
906; MMR6-NEXT:    srlv $4, $7, $5
907; MMR6-NEXT:    or $11, $11, $2
908; MMR6-NEXT:    or $5, $8, $13
909; MMR6-NEXT:    srlv $6, $17, $3
910; MMR6-NEXT:    lw $2, 20($sp) # 4-byte Folded Reload
911; MMR6-NEXT:    selnez $7, $4, $2
912; MMR6-NEXT:    sltiu $8, $3, 64
913; MMR6-NEXT:    selnez $12, $5, $8
914; MMR6-NEXT:    or $7, $7, $9
915; MMR6-NEXT:    lw $5, 12($sp) # 4-byte Folded Reload
916; MMR6-NEXT:    lw $2, 8($sp) # 4-byte Folded Reload
917; MMR6-NEXT:    sllv $9, $2, $5
918; MMR6-NEXT:    seleqz $10, $10, $16
919; MMR6-NEXT:    li16 $5, 0
920; MMR6-NEXT:    or $10, $10, $11
921; MMR6-NEXT:    or $6, $9, $6
922; MMR6-NEXT:    seleqz $2, $7, $8
923; MMR6-NEXT:    seleqz $7, $5, $8
924; MMR6-NEXT:    lw $5, 4($sp) # 4-byte Folded Reload
925; MMR6-NEXT:    srlv $9, $5, $3
926; MMR6-NEXT:    seleqz $11, $9, $16
927; MMR6-NEXT:    selnez $11, $11, $8
928; MMR6-NEXT:    seleqz $1, $1, $3
929; MMR6-NEXT:    or $2, $12, $2
930; MMR6-NEXT:    selnez $2, $2, $3
931; MMR6-NEXT:    or $5, $1, $2
932; MMR6-NEXT:    or $2, $7, $11
933; MMR6-NEXT:    seleqz $1, $6, $16
934; MMR6-NEXT:    selnez $6, $9, $16
935; MMR6-NEXT:    lw $16, 16($sp) # 4-byte Folded Reload
936; MMR6-NEXT:    seleqz $9, $16, $3
937; MMR6-NEXT:    selnez $10, $10, $8
938; MMR6-NEXT:    lw $16, 20($sp) # 4-byte Folded Reload
939; MMR6-NEXT:    seleqz $4, $4, $16
940; MMR6-NEXT:    seleqz $4, $4, $8
941; MMR6-NEXT:    or $4, $10, $4
942; MMR6-NEXT:    selnez $3, $4, $3
943; MMR6-NEXT:    or $4, $9, $3
944; MMR6-NEXT:    or $1, $6, $1
945; MMR6-NEXT:    selnez $1, $1, $8
946; MMR6-NEXT:    or $3, $7, $1
947; MMR6-NEXT:    lw $16, 24($sp) # 4-byte Folded Reload
948; MMR6-NEXT:    lw $17, 28($sp) # 4-byte Folded Reload
949; MMR6-NEXT:    addiu $sp, $sp, 32
950; MMR6-NEXT:    jrc $ra
951entry:
952
953; o32 shouldn't use TImode helpers.
954; GP32-NOT:       lw        $25, %call16(__lshrti3)($gp)
955; MM-NOT:         lw        $25, %call16(__lshrti3)($2)
956
957  %r = lshr i128 %a, %b
958  ret i128 %r
959}
960