1from __future__ import print_function 2import lldb 3from lldbsuite.test.lldbtest import * 4from lldbsuite.test.decorators import * 5from gdbclientutils import * 6 7 8class TestGDBServerTargetXML(GDBRemoteTestBase): 9 10 @skipIfXmlSupportMissing 11 @skipIfRemote 12 @skipIfLLVMTargetMissing("X86") 13 def test_x86_64_regs(self): 14 """Test grabbing various x86_64 registers from gdbserver.""" 15 reg_data = [ 16 "0102030405060708", # rcx 17 "1112131415161718", # rdx 18 "2122232425262728", # rsi 19 "3132333435363738", # rdi 20 "4142434445464748", # rbp 21 "5152535455565758", # rsp 22 "6162636465666768", # r8 23 "7172737475767778", # r9 24 "8182838485868788", # rip 25 "91929394", # eflags 26 "0102030405060708090a", # st0 27 "1112131415161718191a", # st1 28 ] + 6 * [ 29 "2122232425262728292a" # st2..st7 30 ] + [ 31 "8182838485868788898a8b8c8d8e8f90", # xmm0 32 "9192939495969798999a9b9c9d9e9fa0", # xmm1 33 ] + 14 * [ 34 "a1a2a3a4a5a6a7a8a9aaabacadaeafb0", # xmm2..xmm15 35 ] + [ 36 "00000000", # mxcsr 37 ] + [ 38 "b1b2b3b4b5b6b7b8b9babbbcbdbebfc0", # ymm0h 39 "c1c2c3c4c5c6c7c8c9cacbcccdcecfd0", # ymm1h 40 ] + 14 * [ 41 "d1d2d3d4d5d6d7d8d9dadbdcdddedfe0", # ymm2h..ymm15h 42 ] 43 44 class MyResponder(MockGDBServerResponder): 45 def qXferRead(self, obj, annex, offset, length): 46 if annex == "target.xml": 47 return """<?xml version="1.0"?> 48 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 49 <target> 50 <architecture>i386:x86-64</architecture> 51 <osabi>GNU/Linux</osabi> 52 <feature name="org.gnu.gdb.i386.core"> 53 <reg name="rcx" bitsize="64" type="int64" regnum="2"/> 54 <reg name="rdx" bitsize="64" type="int64" regnum="3"/> 55 <reg name="rsi" bitsize="64" type="int64" regnum="4"/> 56 <reg name="rdi" bitsize="64" type="int64" regnum="5"/> 57 <reg name="rbp" bitsize="64" type="data_ptr" regnum="6"/> 58 <reg name="rsp" bitsize="64" type="data_ptr" regnum="7"/> 59 <reg name="r8" bitsize="64" type="int64" regnum="8"/> 60 <reg name="r9" bitsize="64" type="int64" regnum="9"/> 61 <reg name="rip" bitsize="64" type="code_ptr" regnum="16"/> 62 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="17"/> 63 <reg name="st0" bitsize="80" type="i387_ext" regnum="24"/> 64 <reg name="st1" bitsize="80" type="i387_ext" regnum="25"/> 65 <reg name="st2" bitsize="80" type="i387_ext" regnum="26"/> 66 <reg name="st3" bitsize="80" type="i387_ext" regnum="27"/> 67 <reg name="st4" bitsize="80" type="i387_ext" regnum="28"/> 68 <reg name="st5" bitsize="80" type="i387_ext" regnum="29"/> 69 <reg name="st6" bitsize="80" type="i387_ext" regnum="30"/> 70 <reg name="st7" bitsize="80" type="i387_ext" regnum="31"/> 71 </feature> 72 <feature name="org.gnu.gdb.i386.sse"> 73 <reg name="xmm0" bitsize="128" type="vec128" regnum="40"/> 74 <reg name="xmm1" bitsize="128" type="vec128" regnum="41"/> 75 <reg name="xmm2" bitsize="128" type="vec128" regnum="42"/> 76 <reg name="xmm3" bitsize="128" type="vec128" regnum="43"/> 77 <reg name="xmm4" bitsize="128" type="vec128" regnum="44"/> 78 <reg name="xmm5" bitsize="128" type="vec128" regnum="45"/> 79 <reg name="xmm6" bitsize="128" type="vec128" regnum="46"/> 80 <reg name="xmm7" bitsize="128" type="vec128" regnum="47"/> 81 <reg name="xmm8" bitsize="128" type="vec128" regnum="48"/> 82 <reg name="xmm9" bitsize="128" type="vec128" regnum="49"/> 83 <reg name="xmm10" bitsize="128" type="vec128" regnum="50"/> 84 <reg name="xmm11" bitsize="128" type="vec128" regnum="51"/> 85 <reg name="xmm12" bitsize="128" type="vec128" regnum="52"/> 86 <reg name="xmm13" bitsize="128" type="vec128" regnum="53"/> 87 <reg name="xmm14" bitsize="128" type="vec128" regnum="54"/> 88 <reg name="xmm15" bitsize="128" type="vec128" regnum="55"/> 89 <reg name="mxcsr" bitsize="32" type="i386_mxcsr" regnum="56" group="vector"/> 90 </feature> 91 <feature name="org.gnu.gdb.i386.avx"> 92 <reg name="ymm0h" bitsize="128" type="uint128" regnum="60"/> 93 <reg name="ymm1h" bitsize="128" type="uint128" regnum="61"/> 94 <reg name="ymm2h" bitsize="128" type="uint128" regnum="62"/> 95 <reg name="ymm3h" bitsize="128" type="uint128" regnum="63"/> 96 <reg name="ymm4h" bitsize="128" type="uint128" regnum="64"/> 97 <reg name="ymm5h" bitsize="128" type="uint128" regnum="65"/> 98 <reg name="ymm6h" bitsize="128" type="uint128" regnum="66"/> 99 <reg name="ymm7h" bitsize="128" type="uint128" regnum="67"/> 100 <reg name="ymm8h" bitsize="128" type="uint128" regnum="68"/> 101 <reg name="ymm9h" bitsize="128" type="uint128" regnum="69"/> 102 <reg name="ymm10h" bitsize="128" type="uint128" regnum="70"/> 103 <reg name="ymm11h" bitsize="128" type="uint128" regnum="71"/> 104 <reg name="ymm12h" bitsize="128" type="uint128" regnum="72"/> 105 <reg name="ymm13h" bitsize="128" type="uint128" regnum="73"/> 106 <reg name="ymm14h" bitsize="128" type="uint128" regnum="74"/> 107 <reg name="ymm15h" bitsize="128" type="uint128" regnum="75"/> 108 </feature> 109 </target>""", False 110 else: 111 return None, False 112 113 def readRegister(self, regnum): 114 return "" 115 116 def readRegisters(self): 117 return "".join(reg_data) 118 119 def writeRegisters(self, reg_hex): 120 return "OK" 121 122 def haltReason(self): 123 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 124 125 self.server.responder = MyResponder() 126 127 target = self.createTarget("basic_eh_frame.yaml") 128 process = self.connect(target) 129 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 130 [lldb.eStateStopped]) 131 132 # test generic aliases 133 self.match("register read arg4", 134 ["rcx = 0x0807060504030201"]) 135 self.match("register read arg3", 136 ["rdx = 0x1817161514131211"]) 137 self.match("register read arg2", 138 ["rsi = 0x2827262524232221"]) 139 self.match("register read arg1", 140 ["rdi = 0x3837363534333231"]) 141 self.match("register read fp", 142 ["rbp = 0x4847464544434241"]) 143 self.match("register read sp", 144 ["rsp = 0x5857565554535251"]) 145 self.match("register read arg5", 146 ["r8 = 0x6867666564636261"]) 147 self.match("register read arg6", 148 ["r9 = 0x7877767574737271"]) 149 self.match("register read pc", 150 ["rip = 0x8887868584838281"]) 151 self.match("register read flags", 152 ["eflags = 0x94939291"]) 153 154 # both stX and xmmX should be displayed as vectors 155 self.match("register read st0", 156 ["st0 = {0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a}"]) 157 self.match("register read st1", 158 ["st1 = {0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a}"]) 159 self.match("register read xmm0", 160 ["xmm0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 " 161 "0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 162 self.match("register read xmm1", 163 ["xmm1 = {0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 " 164 "0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0}"]) 165 166 @skipIfXmlSupportMissing 167 @skipIfRemote 168 @skipIfLLVMTargetMissing("X86") 169 def test_i386_regs(self): 170 """Test grabbing various i386 registers from gdbserver.""" 171 reg_data = [ 172 "01020304", # eax 173 "11121314", # ecx 174 "21222324", # edx 175 "31323334", # ebx 176 "41424344", # esp 177 "51525354", # ebp 178 "61626364", # esi 179 "71727374", # edi 180 "81828384", # eip 181 "91929394", # eflags 182 "0102030405060708090a", # st0 183 "1112131415161718191a", # st1 184 ] + 6 * [ 185 "2122232425262728292a" # st2..st7 186 ] + [ 187 "8182838485868788898a8b8c8d8e8f90", # xmm0 188 "9192939495969798999a9b9c9d9e9fa0", # xmm1 189 ] + 6 * [ 190 "a1a2a3a4a5a6a7a8a9aaabacadaeafb0", # xmm2..xmm7 191 ] + [ 192 "00000000", # mxcsr 193 ] + [ 194 "b1b2b3b4b5b6b7b8b9babbbcbdbebfc0", # ymm0h 195 "c1c2c3c4c5c6c7c8c9cacbcccdcecfd0", # ymm1h 196 ] + 6 * [ 197 "d1d2d3d4d5d6d7d8d9dadbdcdddedfe0", # ymm2h..ymm7h 198 ] 199 200 class MyResponder(MockGDBServerResponder): 201 def qXferRead(self, obj, annex, offset, length): 202 if annex == "target.xml": 203 return """<?xml version="1.0"?> 204 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 205 <target> 206 <architecture>i386</architecture> 207 <osabi>GNU/Linux</osabi> 208 <feature name="org.gnu.gdb.i386.core"> 209 <reg name="eax" bitsize="32" type="int32" regnum="0"/> 210 <reg name="ecx" bitsize="32" type="int32" regnum="1"/> 211 <reg name="edx" bitsize="32" type="int32" regnum="2"/> 212 <reg name="ebx" bitsize="32" type="int32" regnum="3"/> 213 <reg name="esp" bitsize="32" type="data_ptr" regnum="4"/> 214 <reg name="ebp" bitsize="32" type="data_ptr" regnum="5"/> 215 <reg name="esi" bitsize="32" type="int32" regnum="6"/> 216 <reg name="edi" bitsize="32" type="int32" regnum="7"/> 217 <reg name="eip" bitsize="32" type="code_ptr" regnum="8"/> 218 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="9"/> 219 <reg name="st0" bitsize="80" type="i387_ext" regnum="16"/> 220 <reg name="st1" bitsize="80" type="i387_ext" regnum="17"/> 221 <reg name="st2" bitsize="80" type="i387_ext" regnum="18"/> 222 <reg name="st3" bitsize="80" type="i387_ext" regnum="19"/> 223 <reg name="st4" bitsize="80" type="i387_ext" regnum="20"/> 224 <reg name="st5" bitsize="80" type="i387_ext" regnum="21"/> 225 <reg name="st6" bitsize="80" type="i387_ext" regnum="22"/> 226 <reg name="st7" bitsize="80" type="i387_ext" regnum="23"/> 227 </feature> 228 <feature name="org.gnu.gdb.i386.sse"> 229 <reg name="xmm0" bitsize="128" type="vec128" regnum="32"/> 230 <reg name="xmm1" bitsize="128" type="vec128" regnum="33"/> 231 <reg name="xmm2" bitsize="128" type="vec128" regnum="34"/> 232 <reg name="xmm3" bitsize="128" type="vec128" regnum="35"/> 233 <reg name="xmm4" bitsize="128" type="vec128" regnum="36"/> 234 <reg name="xmm5" bitsize="128" type="vec128" regnum="37"/> 235 <reg name="xmm6" bitsize="128" type="vec128" regnum="38"/> 236 <reg name="xmm7" bitsize="128" type="vec128" regnum="39"/> 237 <reg name="mxcsr" bitsize="32" type="i386_mxcsr" regnum="40" group="vector"/> 238 </feature> 239 <feature name="org.gnu.gdb.i386.avx"> 240 <reg name="ymm0h" bitsize="128" type="uint128" regnum="42"/> 241 <reg name="ymm1h" bitsize="128" type="uint128" regnum="43"/> 242 <reg name="ymm2h" bitsize="128" type="uint128" regnum="44"/> 243 <reg name="ymm3h" bitsize="128" type="uint128" regnum="45"/> 244 <reg name="ymm4h" bitsize="128" type="uint128" regnum="46"/> 245 <reg name="ymm5h" bitsize="128" type="uint128" regnum="47"/> 246 <reg name="ymm6h" bitsize="128" type="uint128" regnum="48"/> 247 <reg name="ymm7h" bitsize="128" type="uint128" regnum="49"/> 248 </feature> 249 </target>""", False 250 else: 251 return None, False 252 253 def readRegister(self, regnum): 254 return "" 255 256 def readRegisters(self): 257 return "".join(reg_data) 258 259 def writeRegisters(self, reg_hex): 260 return "OK" 261 262 def haltReason(self): 263 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 264 265 self.server.responder = MyResponder() 266 267 target = self.createTarget("basic_eh_frame-i386.yaml") 268 process = self.connect(target) 269 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 270 [lldb.eStateStopped]) 271 272 # test generic aliases 273 self.match("register read fp", 274 ["ebp = 0x54535251"]) 275 self.match("register read pc", 276 ["eip = 0x84838281"]) 277 self.match("register read flags", 278 ["eflags = 0x94939291"]) 279 280 # both stX and xmmX should be displayed as vectors 281 self.match("register read st0", 282 ["st0 = {0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a}"]) 283 self.match("register read st1", 284 ["st1 = {0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a}"]) 285 self.match("register read xmm0", 286 ["xmm0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 " 287 "0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 288 self.match("register read xmm1", 289 ["xmm1 = {0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 " 290 "0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0}"]) 291 292 @skipIfXmlSupportMissing 293 @skipIfRemote 294 @skipIfLLVMTargetMissing("AArch64") 295 def test_aarch64_regs(self): 296 """Test grabbing various aarch64 registers from gdbserver.""" 297 class MyResponder(MockGDBServerResponder): 298 reg_data = ( 299 "0102030405060708" # x0 300 "1112131415161718" # x1 301 ) + 27 * ( 302 "2122232425262728" # x2..x28 303 ) + ( 304 "3132333435363738" # x29 (fp) 305 "4142434445464748" # x30 (lr) 306 "5152535455565758" # x31 (sp) 307 "6162636465666768" # pc 308 "71727374" # cpsr 309 "8182838485868788898a8b8c8d8e8f90" # v0 310 "9192939495969798999a9b9c9d9e9fa0" # v1 311 ) + 30 * ( 312 "a1a2a3a4a5a6a7a8a9aaabacadaeafb0" # v2..v31 313 ) + ( 314 "00000000" # fpsr 315 "00000000" # fpcr 316 ) 317 318 def qXferRead(self, obj, annex, offset, length): 319 if annex == "target.xml": 320 return """<?xml version="1.0"?> 321 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 322 <target> 323 <architecture>aarch64</architecture> 324 <feature name="org.gnu.gdb.aarch64.core"> 325 <reg name="x0" bitsize="64" type="int" regnum="0"/> 326 <reg name="x1" bitsize="64" type="int" regnum="1"/> 327 <reg name="x2" bitsize="64" type="int" regnum="2"/> 328 <reg name="x3" bitsize="64" type="int" regnum="3"/> 329 <reg name="x4" bitsize="64" type="int" regnum="4"/> 330 <reg name="x5" bitsize="64" type="int" regnum="5"/> 331 <reg name="x6" bitsize="64" type="int" regnum="6"/> 332 <reg name="x7" bitsize="64" type="int" regnum="7"/> 333 <reg name="x8" bitsize="64" type="int" regnum="8"/> 334 <reg name="x9" bitsize="64" type="int" regnum="9"/> 335 <reg name="x10" bitsize="64" type="int" regnum="10"/> 336 <reg name="x11" bitsize="64" type="int" regnum="11"/> 337 <reg name="x12" bitsize="64" type="int" regnum="12"/> 338 <reg name="x13" bitsize="64" type="int" regnum="13"/> 339 <reg name="x14" bitsize="64" type="int" regnum="14"/> 340 <reg name="x15" bitsize="64" type="int" regnum="15"/> 341 <reg name="x16" bitsize="64" type="int" regnum="16"/> 342 <reg name="x17" bitsize="64" type="int" regnum="17"/> 343 <reg name="x18" bitsize="64" type="int" regnum="18"/> 344 <reg name="x19" bitsize="64" type="int" regnum="19"/> 345 <reg name="x20" bitsize="64" type="int" regnum="20"/> 346 <reg name="x21" bitsize="64" type="int" regnum="21"/> 347 <reg name="x22" bitsize="64" type="int" regnum="22"/> 348 <reg name="x23" bitsize="64" type="int" regnum="23"/> 349 <reg name="x24" bitsize="64" type="int" regnum="24"/> 350 <reg name="x25" bitsize="64" type="int" regnum="25"/> 351 <reg name="x26" bitsize="64" type="int" regnum="26"/> 352 <reg name="x27" bitsize="64" type="int" regnum="27"/> 353 <reg name="x28" bitsize="64" type="int" regnum="28"/> 354 <reg name="x29" bitsize="64" type="int" regnum="29"/> 355 <reg name="x30" bitsize="64" type="int" regnum="30"/> 356 <reg name="sp" bitsize="64" type="data_ptr" regnum="31"/> 357 <reg name="pc" bitsize="64" type="code_ptr" regnum="32"/> 358 <reg name="cpsr" bitsize="32" type="cpsr_flags" regnum="33"/> 359 </feature> 360 <feature name="org.gnu.gdb.aarch64.fpu"> 361 <reg name="v0" bitsize="128" type="aarch64v" regnum="34"/> 362 <reg name="v1" bitsize="128" type="aarch64v" regnum="35"/> 363 <reg name="v2" bitsize="128" type="aarch64v" regnum="36"/> 364 <reg name="v3" bitsize="128" type="aarch64v" regnum="37"/> 365 <reg name="v4" bitsize="128" type="aarch64v" regnum="38"/> 366 <reg name="v5" bitsize="128" type="aarch64v" regnum="39"/> 367 <reg name="v6" bitsize="128" type="aarch64v" regnum="40"/> 368 <reg name="v7" bitsize="128" type="aarch64v" regnum="41"/> 369 <reg name="v8" bitsize="128" type="aarch64v" regnum="42"/> 370 <reg name="v9" bitsize="128" type="aarch64v" regnum="43"/> 371 <reg name="v10" bitsize="128" type="aarch64v" regnum="44"/> 372 <reg name="v11" bitsize="128" type="aarch64v" regnum="45"/> 373 <reg name="v12" bitsize="128" type="aarch64v" regnum="46"/> 374 <reg name="v13" bitsize="128" type="aarch64v" regnum="47"/> 375 <reg name="v14" bitsize="128" type="aarch64v" regnum="48"/> 376 <reg name="v15" bitsize="128" type="aarch64v" regnum="49"/> 377 <reg name="v16" bitsize="128" type="aarch64v" regnum="50"/> 378 <reg name="v17" bitsize="128" type="aarch64v" regnum="51"/> 379 <reg name="v18" bitsize="128" type="aarch64v" regnum="52"/> 380 <reg name="v19" bitsize="128" type="aarch64v" regnum="53"/> 381 <reg name="v20" bitsize="128" type="aarch64v" regnum="54"/> 382 <reg name="v21" bitsize="128" type="aarch64v" regnum="55"/> 383 <reg name="v22" bitsize="128" type="aarch64v" regnum="56"/> 384 <reg name="v23" bitsize="128" type="aarch64v" regnum="57"/> 385 <reg name="v24" bitsize="128" type="aarch64v" regnum="58"/> 386 <reg name="v25" bitsize="128" type="aarch64v" regnum="59"/> 387 <reg name="v26" bitsize="128" type="aarch64v" regnum="60"/> 388 <reg name="v27" bitsize="128" type="aarch64v" regnum="61"/> 389 <reg name="v28" bitsize="128" type="aarch64v" regnum="62"/> 390 <reg name="v29" bitsize="128" type="aarch64v" regnum="63"/> 391 <reg name="v30" bitsize="128" type="aarch64v" regnum="64"/> 392 <reg name="v31" bitsize="128" type="aarch64v" regnum="65"/> 393 <reg name="fpsr" bitsize="32" type="int" regnum="66"/> 394 <reg name="fpcr" bitsize="32" type="int" regnum="67"/> 395 </feature> 396 </target>""", False 397 else: 398 return None, False 399 400 def readRegister(self, regnum): 401 return "" 402 403 def readRegisters(self): 404 return self.reg_data 405 406 def writeRegisters(self, reg_hex): 407 self.reg_data = reg_hex 408 return "OK" 409 410 def haltReason(self): 411 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 412 413 self.server.responder = MyResponder() 414 415 target = self.createTarget("basic_eh_frame-aarch64.yaml") 416 process = self.connect(target) 417 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 418 [lldb.eStateStopped]) 419 420 # test GPRs 421 self.match("register read x0", 422 ["x0 = 0x0807060504030201"]) 423 self.match("register read x1", 424 ["x1 = 0x1817161514131211"]) 425 self.match("register read x29", 426 ["x29 = 0x3837363534333231"]) 427 self.match("register read x30", 428 ["x30 = 0x4847464544434241"]) 429 self.match("register read x31", 430 ["sp = 0x5857565554535251"]) 431 self.match("register read sp", 432 ["sp = 0x5857565554535251"]) 433 self.match("register read pc", 434 ["pc = 0x6867666564636261"]) 435 self.match("register read cpsr", 436 ["cpsr = 0x74737271"]) 437 438 # test generic aliases 439 self.match("register read arg1", 440 ["x0 = 0x0807060504030201"]) 441 self.match("register read arg2", 442 ["x1 = 0x1817161514131211"]) 443 self.match("register read fp", 444 ["x29 = 0x3837363534333231"]) 445 self.match("register read lr", 446 ["x30 = 0x4847464544434241"]) 447 self.match("register read ra", 448 ["x30 = 0x4847464544434241"]) 449 self.match("register read flags", 450 ["cpsr = 0x74737271"]) 451 452 # test vector registers 453 self.match("register read v0", 454 ["v0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 455 self.match("register read v31", 456 ["v31 = {0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0}"]) 457 458 # test partial registers 459 self.match("register read w0", 460 ["w0 = 0x04030201"]) 461 self.runCmd("register write w0 0xfffefdfc") 462 self.match("register read x0", 463 ["x0 = 0x08070605fffefdfc"]) 464 465 self.match("register read w1", 466 ["w1 = 0x14131211"]) 467 self.runCmd("register write w1 0xefeeedec") 468 self.match("register read x1", 469 ["x1 = 0x18171615efeeedec"]) 470 471 self.match("register read w30", 472 ["w30 = 0x44434241"]) 473 self.runCmd("register write w30 0xdfdedddc") 474 self.match("register read x30", 475 ["x30 = 0x48474645dfdedddc"]) 476 477 self.match("register read w31", 478 ["w31 = 0x54535251"]) 479 self.runCmd("register write w31 0xcfcecdcc") 480 self.match("register read x31", 481 ["sp = 0x58575655cfcecdcc"]) 482 483 # test FPU registers (overlapping with vector registers) 484 self.runCmd("register write d0 16") 485 self.match("register read v0", 486 ["v0 = {0x00 0x00 0x00 0x00 0x00 0x00 0x30 0x40 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 487 self.runCmd("register write v31 '{0x00 0x00 0x00 0x00 0x00 0x00 0x50 0x40 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff}'") 488 self.match("register read d31", 489 ["d31 = 64"]) 490 491 self.runCmd("register write s0 32") 492 self.match("register read v0", 493 ["v0 = {0x00 0x00 0x00 0x42 0x00 0x00 0x30 0x40 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 494 self.runCmd("register write v31 '{0x00 0x00 0x00 0x43 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff}'") 495 self.match("register read s31", 496 ["s31 = 128"]) 497