1 //===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Methods common to all machine instructions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "llvm/CodeGen/MachineInstr.h"
14 #include "llvm/ADT/APFloat.h"
15 #include "llvm/ADT/ArrayRef.h"
16 #include "llvm/ADT/FoldingSet.h"
17 #include "llvm/ADT/Hashing.h"
18 #include "llvm/ADT/None.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallBitVector.h"
21 #include "llvm/ADT/SmallString.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/Analysis/AliasAnalysis.h"
24 #include "llvm/Analysis/Loads.h"
25 #include "llvm/Analysis/MemoryLocation.h"
26 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
27 #include "llvm/CodeGen/MachineBasicBlock.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineInstrBundle.h"
32 #include "llvm/CodeGen/MachineMemOperand.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineOperand.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/CodeGen/TargetInstrInfo.h"
39 #include "llvm/CodeGen/TargetRegisterInfo.h"
40 #include "llvm/CodeGen/TargetSubtargetInfo.h"
41 #include "llvm/Config/llvm-config.h"
42 #include "llvm/IR/Constants.h"
43 #include "llvm/IR/DebugInfoMetadata.h"
44 #include "llvm/IR/DebugLoc.h"
45 #include "llvm/IR/DerivedTypes.h"
46 #include "llvm/IR/Function.h"
47 #include "llvm/IR/InlineAsm.h"
48 #include "llvm/IR/InstrTypes.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Metadata.h"
52 #include "llvm/IR/Module.h"
53 #include "llvm/IR/ModuleSlotTracker.h"
54 #include "llvm/IR/Operator.h"
55 #include "llvm/IR/Type.h"
56 #include "llvm/IR/Value.h"
57 #include "llvm/MC/MCInstrDesc.h"
58 #include "llvm/MC/MCRegisterInfo.h"
59 #include "llvm/MC/MCSymbol.h"
60 #include "llvm/Support/Casting.h"
61 #include "llvm/Support/CommandLine.h"
62 #include "llvm/Support/Compiler.h"
63 #include "llvm/Support/Debug.h"
64 #include "llvm/Support/ErrorHandling.h"
65 #include "llvm/Support/FormattedStream.h"
66 #include "llvm/Support/LowLevelTypeImpl.h"
67 #include "llvm/Support/MathExtras.h"
68 #include "llvm/Support/raw_ostream.h"
69 #include "llvm/Target/TargetIntrinsicInfo.h"
70 #include "llvm/Target/TargetMachine.h"
71 #include <algorithm>
72 #include <cassert>
73 #include <cstddef>
74 #include <cstdint>
75 #include <cstring>
76 #include <iterator>
77 #include <utility>
78
79 using namespace llvm;
80
getMFIfAvailable(const MachineInstr & MI)81 static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) {
82 if (const MachineBasicBlock *MBB = MI.getParent())
83 if (const MachineFunction *MF = MBB->getParent())
84 return MF;
85 return nullptr;
86 }
87
88 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
89 // it.
tryToGetTargetInfo(const MachineInstr & MI,const TargetRegisterInfo * & TRI,const MachineRegisterInfo * & MRI,const TargetIntrinsicInfo * & IntrinsicInfo,const TargetInstrInfo * & TII)90 static void tryToGetTargetInfo(const MachineInstr &MI,
91 const TargetRegisterInfo *&TRI,
92 const MachineRegisterInfo *&MRI,
93 const TargetIntrinsicInfo *&IntrinsicInfo,
94 const TargetInstrInfo *&TII) {
95
96 if (const MachineFunction *MF = getMFIfAvailable(MI)) {
97 TRI = MF->getSubtarget().getRegisterInfo();
98 MRI = &MF->getRegInfo();
99 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
100 TII = MF->getSubtarget().getInstrInfo();
101 }
102 }
103
addImplicitDefUseOperands(MachineFunction & MF)104 void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
105 if (MCID->ImplicitDefs)
106 for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
107 ++ImpDefs)
108 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
109 if (MCID->ImplicitUses)
110 for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
111 ++ImpUses)
112 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
113 }
114
115 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
116 /// implicit operands. It reserves space for the number of operands specified by
117 /// the MCInstrDesc.
MachineInstr(MachineFunction & MF,const MCInstrDesc & tid,DebugLoc dl,bool NoImp)118 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
119 DebugLoc dl, bool NoImp)
120 : MCID(&tid), debugLoc(std::move(dl)), DebugInstrNum(0) {
121 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
122
123 // Reserve space for the expected number of operands.
124 if (unsigned NumOps = MCID->getNumOperands() +
125 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
126 CapOperands = OperandCapacity::get(NumOps);
127 Operands = MF.allocateOperandArray(CapOperands);
128 }
129
130 if (!NoImp)
131 addImplicitDefUseOperands(MF);
132 }
133
134 /// MachineInstr ctor - Copies MachineInstr arg exactly.
135 /// Does not copy the number from debug instruction numbering, to preserve
136 /// uniqueness.
MachineInstr(MachineFunction & MF,const MachineInstr & MI)137 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
138 : MCID(&MI.getDesc()), Info(MI.Info), debugLoc(MI.getDebugLoc()),
139 DebugInstrNum(0) {
140 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
141
142 CapOperands = OperandCapacity::get(MI.getNumOperands());
143 Operands = MF.allocateOperandArray(CapOperands);
144
145 // Copy operands.
146 for (const MachineOperand &MO : MI.operands())
147 addOperand(MF, MO);
148
149 // Copy all the sensible flags.
150 setFlags(MI.Flags);
151 }
152
moveBefore(MachineInstr * MovePos)153 void MachineInstr::moveBefore(MachineInstr *MovePos) {
154 MovePos->getParent()->splice(MovePos, getParent(), getIterator());
155 }
156
157 /// getRegInfo - If this instruction is embedded into a MachineFunction,
158 /// return the MachineRegisterInfo object for the current function, otherwise
159 /// return null.
getRegInfo()160 MachineRegisterInfo *MachineInstr::getRegInfo() {
161 if (MachineBasicBlock *MBB = getParent())
162 return &MBB->getParent()->getRegInfo();
163 return nullptr;
164 }
165
166 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
167 /// this instruction from their respective use lists. This requires that the
168 /// operands already be on their use lists.
RemoveRegOperandsFromUseLists(MachineRegisterInfo & MRI)169 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
170 for (MachineOperand &MO : operands())
171 if (MO.isReg())
172 MRI.removeRegOperandFromUseList(&MO);
173 }
174
175 /// AddRegOperandsToUseLists - Add all of the register operands in
176 /// this instruction from their respective use lists. This requires that the
177 /// operands not be on their use lists yet.
AddRegOperandsToUseLists(MachineRegisterInfo & MRI)178 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
179 for (MachineOperand &MO : operands())
180 if (MO.isReg())
181 MRI.addRegOperandToUseList(&MO);
182 }
183
addOperand(const MachineOperand & Op)184 void MachineInstr::addOperand(const MachineOperand &Op) {
185 MachineBasicBlock *MBB = getParent();
186 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
187 MachineFunction *MF = MBB->getParent();
188 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
189 addOperand(*MF, Op);
190 }
191
192 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
193 /// ranges. If MRI is non-null also update use-def chains.
moveOperands(MachineOperand * Dst,MachineOperand * Src,unsigned NumOps,MachineRegisterInfo * MRI)194 static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
195 unsigned NumOps, MachineRegisterInfo *MRI) {
196 if (MRI)
197 return MRI->moveOperands(Dst, Src, NumOps);
198 // MachineOperand is a trivially copyable type so we can just use memmove.
199 assert(Dst && Src && "Unknown operands");
200 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
201 }
202
203 /// addOperand - Add the specified operand to the instruction. If it is an
204 /// implicit operand, it is added to the end of the operand list. If it is
205 /// an explicit operand it is added at the end of the explicit operand list
206 /// (before the first implicit operand).
addOperand(MachineFunction & MF,const MachineOperand & Op)207 void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
208 assert(MCID && "Cannot add operands before providing an instr descriptor");
209
210 // Check if we're adding one of our existing operands.
211 if (&Op >= Operands && &Op < Operands + NumOperands) {
212 // This is unusual: MI->addOperand(MI->getOperand(i)).
213 // If adding Op requires reallocating or moving existing operands around,
214 // the Op reference could go stale. Support it by copying Op.
215 MachineOperand CopyOp(Op);
216 return addOperand(MF, CopyOp);
217 }
218
219 // Find the insert location for the new operand. Implicit registers go at
220 // the end, everything else goes before the implicit regs.
221 //
222 // FIXME: Allow mixed explicit and implicit operands on inline asm.
223 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
224 // implicit-defs, but they must not be moved around. See the FIXME in
225 // InstrEmitter.cpp.
226 unsigned OpNo = getNumOperands();
227 bool isImpReg = Op.isReg() && Op.isImplicit();
228 if (!isImpReg && !isInlineAsm()) {
229 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
230 --OpNo;
231 assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
232 }
233 }
234
235 #ifndef NDEBUG
236 bool isDebugOp = Op.getType() == MachineOperand::MO_Metadata ||
237 Op.getType() == MachineOperand::MO_MCSymbol;
238 // OpNo now points as the desired insertion point. Unless this is a variadic
239 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
240 // RegMask operands go between the explicit and implicit operands.
241 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
242 OpNo < MCID->getNumOperands() || isDebugOp) &&
243 "Trying to add an operand to a machine instr that is already done!");
244 #endif
245
246 MachineRegisterInfo *MRI = getRegInfo();
247
248 // Determine if the Operands array needs to be reallocated.
249 // Save the old capacity and operand array.
250 OperandCapacity OldCap = CapOperands;
251 MachineOperand *OldOperands = Operands;
252 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
253 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
254 Operands = MF.allocateOperandArray(CapOperands);
255 // Move the operands before the insertion point.
256 if (OpNo)
257 moveOperands(Operands, OldOperands, OpNo, MRI);
258 }
259
260 // Move the operands following the insertion point.
261 if (OpNo != NumOperands)
262 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
263 MRI);
264 ++NumOperands;
265
266 // Deallocate the old operand array.
267 if (OldOperands != Operands && OldOperands)
268 MF.deallocateOperandArray(OldCap, OldOperands);
269
270 // Copy Op into place. It still needs to be inserted into the MRI use lists.
271 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
272 NewMO->ParentMI = this;
273
274 // When adding a register operand, tell MRI about it.
275 if (NewMO->isReg()) {
276 // Ensure isOnRegUseList() returns false, regardless of Op's status.
277 NewMO->Contents.Reg.Prev = nullptr;
278 // Ignore existing ties. This is not a property that can be copied.
279 NewMO->TiedTo = 0;
280 // Add the new operand to MRI, but only for instructions in an MBB.
281 if (MRI)
282 MRI->addRegOperandToUseList(NewMO);
283 // The MCID operand information isn't accurate until we start adding
284 // explicit operands. The implicit operands are added first, then the
285 // explicits are inserted before them.
286 if (!isImpReg) {
287 // Tie uses to defs as indicated in MCInstrDesc.
288 if (NewMO->isUse()) {
289 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
290 if (DefIdx != -1)
291 tieOperands(DefIdx, OpNo);
292 }
293 // If the register operand is flagged as early, mark the operand as such.
294 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
295 NewMO->setIsEarlyClobber(true);
296 }
297 // Ensure debug instructions set debug flag on register uses.
298 if (NewMO->isUse() && isDebugInstr())
299 NewMO->setIsDebug();
300 }
301 }
302
303 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
304 /// fewer operand than it started with.
305 ///
RemoveOperand(unsigned OpNo)306 void MachineInstr::RemoveOperand(unsigned OpNo) {
307 assert(OpNo < getNumOperands() && "Invalid operand number");
308 untieRegOperand(OpNo);
309
310 #ifndef NDEBUG
311 // Moving tied operands would break the ties.
312 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
313 if (Operands[i].isReg())
314 assert(!Operands[i].isTied() && "Cannot move tied operands");
315 #endif
316
317 MachineRegisterInfo *MRI = getRegInfo();
318 if (MRI && Operands[OpNo].isReg())
319 MRI->removeRegOperandFromUseList(Operands + OpNo);
320
321 // Don't call the MachineOperand destructor. A lot of this code depends on
322 // MachineOperand having a trivial destructor anyway, and adding a call here
323 // wouldn't make it 'destructor-correct'.
324
325 if (unsigned N = NumOperands - 1 - OpNo)
326 moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
327 --NumOperands;
328 }
329
setExtraInfo(MachineFunction & MF,ArrayRef<MachineMemOperand * > MMOs,MCSymbol * PreInstrSymbol,MCSymbol * PostInstrSymbol,MDNode * HeapAllocMarker)330 void MachineInstr::setExtraInfo(MachineFunction &MF,
331 ArrayRef<MachineMemOperand *> MMOs,
332 MCSymbol *PreInstrSymbol,
333 MCSymbol *PostInstrSymbol,
334 MDNode *HeapAllocMarker) {
335 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
336 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
337 bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
338 int NumPointers =
339 MMOs.size() + HasPreInstrSymbol + HasPostInstrSymbol + HasHeapAllocMarker;
340
341 // Drop all extra info if there is none.
342 if (NumPointers <= 0) {
343 Info.clear();
344 return;
345 }
346
347 // If more than one pointer, then store out of line. Store heap alloc markers
348 // out of line because PointerSumType cannot hold more than 4 tag types with
349 // 32-bit pointers.
350 // FIXME: Maybe we should make the symbols in the extra info mutable?
351 else if (NumPointers > 1 || HasHeapAllocMarker) {
352 Info.set<EIIK_OutOfLine>(MF.createMIExtraInfo(
353 MMOs, PreInstrSymbol, PostInstrSymbol, HeapAllocMarker));
354 return;
355 }
356
357 // Otherwise store the single pointer inline.
358 if (HasPreInstrSymbol)
359 Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol);
360 else if (HasPostInstrSymbol)
361 Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol);
362 else
363 Info.set<EIIK_MMO>(MMOs[0]);
364 }
365
dropMemRefs(MachineFunction & MF)366 void MachineInstr::dropMemRefs(MachineFunction &MF) {
367 if (memoperands_empty())
368 return;
369
370 setExtraInfo(MF, {}, getPreInstrSymbol(), getPostInstrSymbol(),
371 getHeapAllocMarker());
372 }
373
setMemRefs(MachineFunction & MF,ArrayRef<MachineMemOperand * > MMOs)374 void MachineInstr::setMemRefs(MachineFunction &MF,
375 ArrayRef<MachineMemOperand *> MMOs) {
376 if (MMOs.empty()) {
377 dropMemRefs(MF);
378 return;
379 }
380
381 setExtraInfo(MF, MMOs, getPreInstrSymbol(), getPostInstrSymbol(),
382 getHeapAllocMarker());
383 }
384
addMemOperand(MachineFunction & MF,MachineMemOperand * MO)385 void MachineInstr::addMemOperand(MachineFunction &MF,
386 MachineMemOperand *MO) {
387 SmallVector<MachineMemOperand *, 2> MMOs;
388 MMOs.append(memoperands_begin(), memoperands_end());
389 MMOs.push_back(MO);
390 setMemRefs(MF, MMOs);
391 }
392
cloneMemRefs(MachineFunction & MF,const MachineInstr & MI)393 void MachineInstr::cloneMemRefs(MachineFunction &MF, const MachineInstr &MI) {
394 if (this == &MI)
395 // Nothing to do for a self-clone!
396 return;
397
398 assert(&MF == MI.getMF() &&
399 "Invalid machine functions when cloning memory refrences!");
400 // See if we can just steal the extra info already allocated for the
401 // instruction. We can do this whenever the pre- and post-instruction symbols
402 // are the same (including null).
403 if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&
404 getPostInstrSymbol() == MI.getPostInstrSymbol() &&
405 getHeapAllocMarker() == MI.getHeapAllocMarker()) {
406 Info = MI.Info;
407 return;
408 }
409
410 // Otherwise, fall back on a copy-based clone.
411 setMemRefs(MF, MI.memoperands());
412 }
413
414 /// Check to see if the MMOs pointed to by the two MemRefs arrays are
415 /// identical.
hasIdenticalMMOs(ArrayRef<MachineMemOperand * > LHS,ArrayRef<MachineMemOperand * > RHS)416 static bool hasIdenticalMMOs(ArrayRef<MachineMemOperand *> LHS,
417 ArrayRef<MachineMemOperand *> RHS) {
418 if (LHS.size() != RHS.size())
419 return false;
420
421 auto LHSPointees = make_pointee_range(LHS);
422 auto RHSPointees = make_pointee_range(RHS);
423 return std::equal(LHSPointees.begin(), LHSPointees.end(),
424 RHSPointees.begin());
425 }
426
cloneMergedMemRefs(MachineFunction & MF,ArrayRef<const MachineInstr * > MIs)427 void MachineInstr::cloneMergedMemRefs(MachineFunction &MF,
428 ArrayRef<const MachineInstr *> MIs) {
429 // Try handling easy numbers of MIs with simpler mechanisms.
430 if (MIs.empty()) {
431 dropMemRefs(MF);
432 return;
433 }
434 if (MIs.size() == 1) {
435 cloneMemRefs(MF, *MIs[0]);
436 return;
437 }
438 // Because an empty memoperands list provides *no* information and must be
439 // handled conservatively (assuming the instruction can do anything), the only
440 // way to merge with it is to drop all other memoperands.
441 if (MIs[0]->memoperands_empty()) {
442 dropMemRefs(MF);
443 return;
444 }
445
446 // Handle the general case.
447 SmallVector<MachineMemOperand *, 2> MergedMMOs;
448 // Start with the first instruction.
449 assert(&MF == MIs[0]->getMF() &&
450 "Invalid machine functions when cloning memory references!");
451 MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end());
452 // Now walk all the other instructions and accumulate any different MMOs.
453 for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) {
454 assert(&MF == MI.getMF() &&
455 "Invalid machine functions when cloning memory references!");
456
457 // Skip MIs with identical operands to the first. This is a somewhat
458 // arbitrary hack but will catch common cases without being quadratic.
459 // TODO: We could fully implement merge semantics here if needed.
460 if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands()))
461 continue;
462
463 // Because an empty memoperands list provides *no* information and must be
464 // handled conservatively (assuming the instruction can do anything), the
465 // only way to merge with it is to drop all other memoperands.
466 if (MI.memoperands_empty()) {
467 dropMemRefs(MF);
468 return;
469 }
470
471 // Otherwise accumulate these into our temporary buffer of the merged state.
472 MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end());
473 }
474
475 setMemRefs(MF, MergedMMOs);
476 }
477
setPreInstrSymbol(MachineFunction & MF,MCSymbol * Symbol)478 void MachineInstr::setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
479 // Do nothing if old and new symbols are the same.
480 if (Symbol == getPreInstrSymbol())
481 return;
482
483 // If there was only one symbol and we're removing it, just clear info.
484 if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) {
485 Info.clear();
486 return;
487 }
488
489 setExtraInfo(MF, memoperands(), Symbol, getPostInstrSymbol(),
490 getHeapAllocMarker());
491 }
492
setPostInstrSymbol(MachineFunction & MF,MCSymbol * Symbol)493 void MachineInstr::setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
494 // Do nothing if old and new symbols are the same.
495 if (Symbol == getPostInstrSymbol())
496 return;
497
498 // If there was only one symbol and we're removing it, just clear info.
499 if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) {
500 Info.clear();
501 return;
502 }
503
504 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), Symbol,
505 getHeapAllocMarker());
506 }
507
setHeapAllocMarker(MachineFunction & MF,MDNode * Marker)508 void MachineInstr::setHeapAllocMarker(MachineFunction &MF, MDNode *Marker) {
509 // Do nothing if old and new symbols are the same.
510 if (Marker == getHeapAllocMarker())
511 return;
512
513 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),
514 Marker);
515 }
516
cloneInstrSymbols(MachineFunction & MF,const MachineInstr & MI)517 void MachineInstr::cloneInstrSymbols(MachineFunction &MF,
518 const MachineInstr &MI) {
519 if (this == &MI)
520 // Nothing to do for a self-clone!
521 return;
522
523 assert(&MF == MI.getMF() &&
524 "Invalid machine functions when cloning instruction symbols!");
525
526 setPreInstrSymbol(MF, MI.getPreInstrSymbol());
527 setPostInstrSymbol(MF, MI.getPostInstrSymbol());
528 setHeapAllocMarker(MF, MI.getHeapAllocMarker());
529 }
530
mergeFlagsWith(const MachineInstr & Other) const531 uint16_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const {
532 // For now, the just return the union of the flags. If the flags get more
533 // complicated over time, we might need more logic here.
534 return getFlags() | Other.getFlags();
535 }
536
copyFlagsFromInstruction(const Instruction & I)537 uint16_t MachineInstr::copyFlagsFromInstruction(const Instruction &I) {
538 uint16_t MIFlags = 0;
539 // Copy the wrapping flags.
540 if (const OverflowingBinaryOperator *OB =
541 dyn_cast<OverflowingBinaryOperator>(&I)) {
542 if (OB->hasNoSignedWrap())
543 MIFlags |= MachineInstr::MIFlag::NoSWrap;
544 if (OB->hasNoUnsignedWrap())
545 MIFlags |= MachineInstr::MIFlag::NoUWrap;
546 }
547
548 // Copy the exact flag.
549 if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I))
550 if (PE->isExact())
551 MIFlags |= MachineInstr::MIFlag::IsExact;
552
553 // Copy the fast-math flags.
554 if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) {
555 const FastMathFlags Flags = FP->getFastMathFlags();
556 if (Flags.noNaNs())
557 MIFlags |= MachineInstr::MIFlag::FmNoNans;
558 if (Flags.noInfs())
559 MIFlags |= MachineInstr::MIFlag::FmNoInfs;
560 if (Flags.noSignedZeros())
561 MIFlags |= MachineInstr::MIFlag::FmNsz;
562 if (Flags.allowReciprocal())
563 MIFlags |= MachineInstr::MIFlag::FmArcp;
564 if (Flags.allowContract())
565 MIFlags |= MachineInstr::MIFlag::FmContract;
566 if (Flags.approxFunc())
567 MIFlags |= MachineInstr::MIFlag::FmAfn;
568 if (Flags.allowReassoc())
569 MIFlags |= MachineInstr::MIFlag::FmReassoc;
570 }
571
572 return MIFlags;
573 }
574
copyIRFlags(const Instruction & I)575 void MachineInstr::copyIRFlags(const Instruction &I) {
576 Flags = copyFlagsFromInstruction(I);
577 }
578
hasPropertyInBundle(uint64_t Mask,QueryType Type) const579 bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {
580 assert(!isBundledWithPred() && "Must be called on bundle header");
581 for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) {
582 if (MII->getDesc().getFlags() & Mask) {
583 if (Type == AnyInBundle)
584 return true;
585 } else {
586 if (Type == AllInBundle && !MII->isBundle())
587 return false;
588 }
589 // This was the last instruction in the bundle.
590 if (!MII->isBundledWithSucc())
591 return Type == AllInBundle;
592 }
593 }
594
isIdenticalTo(const MachineInstr & Other,MICheckType Check) const595 bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
596 MICheckType Check) const {
597 // If opcodes or number of operands are not the same then the two
598 // instructions are obviously not identical.
599 if (Other.getOpcode() != getOpcode() ||
600 Other.getNumOperands() != getNumOperands())
601 return false;
602
603 if (isBundle()) {
604 // We have passed the test above that both instructions have the same
605 // opcode, so we know that both instructions are bundles here. Let's compare
606 // MIs inside the bundle.
607 assert(Other.isBundle() && "Expected that both instructions are bundles.");
608 MachineBasicBlock::const_instr_iterator I1 = getIterator();
609 MachineBasicBlock::const_instr_iterator I2 = Other.getIterator();
610 // Loop until we analysed the last intruction inside at least one of the
611 // bundles.
612 while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
613 ++I1;
614 ++I2;
615 if (!I1->isIdenticalTo(*I2, Check))
616 return false;
617 }
618 // If we've reached the end of just one of the two bundles, but not both,
619 // the instructions are not identical.
620 if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
621 return false;
622 }
623
624 // Check operands to make sure they match.
625 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
626 const MachineOperand &MO = getOperand(i);
627 const MachineOperand &OMO = Other.getOperand(i);
628 if (!MO.isReg()) {
629 if (!MO.isIdenticalTo(OMO))
630 return false;
631 continue;
632 }
633
634 // Clients may or may not want to ignore defs when testing for equality.
635 // For example, machine CSE pass only cares about finding common
636 // subexpressions, so it's safe to ignore virtual register defs.
637 if (MO.isDef()) {
638 if (Check == IgnoreDefs)
639 continue;
640 else if (Check == IgnoreVRegDefs) {
641 if (!Register::isVirtualRegister(MO.getReg()) ||
642 !Register::isVirtualRegister(OMO.getReg()))
643 if (!MO.isIdenticalTo(OMO))
644 return false;
645 } else {
646 if (!MO.isIdenticalTo(OMO))
647 return false;
648 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
649 return false;
650 }
651 } else {
652 if (!MO.isIdenticalTo(OMO))
653 return false;
654 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
655 return false;
656 }
657 }
658 // If DebugLoc does not match then two debug instructions are not identical.
659 if (isDebugInstr())
660 if (getDebugLoc() && Other.getDebugLoc() &&
661 getDebugLoc() != Other.getDebugLoc())
662 return false;
663 return true;
664 }
665
getMF() const666 const MachineFunction *MachineInstr::getMF() const {
667 return getParent()->getParent();
668 }
669
removeFromParent()670 MachineInstr *MachineInstr::removeFromParent() {
671 assert(getParent() && "Not embedded in a basic block!");
672 return getParent()->remove(this);
673 }
674
removeFromBundle()675 MachineInstr *MachineInstr::removeFromBundle() {
676 assert(getParent() && "Not embedded in a basic block!");
677 return getParent()->remove_instr(this);
678 }
679
eraseFromParent()680 void MachineInstr::eraseFromParent() {
681 assert(getParent() && "Not embedded in a basic block!");
682 getParent()->erase(this);
683 }
684
eraseFromParentAndMarkDBGValuesForRemoval()685 void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() {
686 assert(getParent() && "Not embedded in a basic block!");
687 MachineBasicBlock *MBB = getParent();
688 MachineFunction *MF = MBB->getParent();
689 assert(MF && "Not embedded in a function!");
690
691 MachineInstr *MI = (MachineInstr *)this;
692 MachineRegisterInfo &MRI = MF->getRegInfo();
693
694 for (const MachineOperand &MO : MI->operands()) {
695 if (!MO.isReg() || !MO.isDef())
696 continue;
697 Register Reg = MO.getReg();
698 if (!Reg.isVirtual())
699 continue;
700 MRI.markUsesInDebugValueAsUndef(Reg);
701 }
702 MI->eraseFromParent();
703 }
704
eraseFromBundle()705 void MachineInstr::eraseFromBundle() {
706 assert(getParent() && "Not embedded in a basic block!");
707 getParent()->erase_instr(this);
708 }
709
isCandidateForCallSiteEntry(QueryType Type) const710 bool MachineInstr::isCandidateForCallSiteEntry(QueryType Type) const {
711 if (!isCall(Type))
712 return false;
713 switch (getOpcode()) {
714 case TargetOpcode::PATCHPOINT:
715 case TargetOpcode::STACKMAP:
716 case TargetOpcode::STATEPOINT:
717 case TargetOpcode::FENTRY_CALL:
718 return false;
719 }
720 return true;
721 }
722
shouldUpdateCallSiteInfo() const723 bool MachineInstr::shouldUpdateCallSiteInfo() const {
724 if (isBundle())
725 return isCandidateForCallSiteEntry(MachineInstr::AnyInBundle);
726 return isCandidateForCallSiteEntry();
727 }
728
getNumExplicitOperands() const729 unsigned MachineInstr::getNumExplicitOperands() const {
730 unsigned NumOperands = MCID->getNumOperands();
731 if (!MCID->isVariadic())
732 return NumOperands;
733
734 for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {
735 const MachineOperand &MO = getOperand(I);
736 // The operands must always be in the following order:
737 // - explicit reg defs,
738 // - other explicit operands (reg uses, immediates, etc.),
739 // - implicit reg defs
740 // - implicit reg uses
741 if (MO.isReg() && MO.isImplicit())
742 break;
743 ++NumOperands;
744 }
745 return NumOperands;
746 }
747
getNumExplicitDefs() const748 unsigned MachineInstr::getNumExplicitDefs() const {
749 unsigned NumDefs = MCID->getNumDefs();
750 if (!MCID->isVariadic())
751 return NumDefs;
752
753 for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
754 const MachineOperand &MO = getOperand(I);
755 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
756 break;
757 ++NumDefs;
758 }
759 return NumDefs;
760 }
761
bundleWithPred()762 void MachineInstr::bundleWithPred() {
763 assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
764 setFlag(BundledPred);
765 MachineBasicBlock::instr_iterator Pred = getIterator();
766 --Pred;
767 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
768 Pred->setFlag(BundledSucc);
769 }
770
bundleWithSucc()771 void MachineInstr::bundleWithSucc() {
772 assert(!isBundledWithSucc() && "MI is already bundled with its successor");
773 setFlag(BundledSucc);
774 MachineBasicBlock::instr_iterator Succ = getIterator();
775 ++Succ;
776 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
777 Succ->setFlag(BundledPred);
778 }
779
unbundleFromPred()780 void MachineInstr::unbundleFromPred() {
781 assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
782 clearFlag(BundledPred);
783 MachineBasicBlock::instr_iterator Pred = getIterator();
784 --Pred;
785 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
786 Pred->clearFlag(BundledSucc);
787 }
788
unbundleFromSucc()789 void MachineInstr::unbundleFromSucc() {
790 assert(isBundledWithSucc() && "MI isn't bundled with its successor");
791 clearFlag(BundledSucc);
792 MachineBasicBlock::instr_iterator Succ = getIterator();
793 ++Succ;
794 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
795 Succ->clearFlag(BundledPred);
796 }
797
isStackAligningInlineAsm() const798 bool MachineInstr::isStackAligningInlineAsm() const {
799 if (isInlineAsm()) {
800 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
801 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
802 return true;
803 }
804 return false;
805 }
806
getInlineAsmDialect() const807 InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
808 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
809 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
810 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
811 }
812
findInlineAsmFlagIdx(unsigned OpIdx,unsigned * GroupNo) const813 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
814 unsigned *GroupNo) const {
815 assert(isInlineAsm() && "Expected an inline asm instruction");
816 assert(OpIdx < getNumOperands() && "OpIdx out of range");
817
818 // Ignore queries about the initial operands.
819 if (OpIdx < InlineAsm::MIOp_FirstOperand)
820 return -1;
821
822 unsigned Group = 0;
823 unsigned NumOps;
824 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
825 i += NumOps) {
826 const MachineOperand &FlagMO = getOperand(i);
827 // If we reach the implicit register operands, stop looking.
828 if (!FlagMO.isImm())
829 return -1;
830 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
831 if (i + NumOps > OpIdx) {
832 if (GroupNo)
833 *GroupNo = Group;
834 return i;
835 }
836 ++Group;
837 }
838 return -1;
839 }
840
getDebugLabel() const841 const DILabel *MachineInstr::getDebugLabel() const {
842 assert(isDebugLabel() && "not a DBG_LABEL");
843 return cast<DILabel>(getOperand(0).getMetadata());
844 }
845
getDebugVariableOp() const846 const MachineOperand &MachineInstr::getDebugVariableOp() const {
847 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
848 unsigned VariableOp = isDebugValueList() ? 0 : 2;
849 return getOperand(VariableOp);
850 }
851
getDebugVariableOp()852 MachineOperand &MachineInstr::getDebugVariableOp() {
853 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
854 unsigned VariableOp = isDebugValueList() ? 0 : 2;
855 return getOperand(VariableOp);
856 }
857
getDebugVariable() const858 const DILocalVariable *MachineInstr::getDebugVariable() const {
859 return cast<DILocalVariable>(getDebugVariableOp().getMetadata());
860 }
861
getDebugExpressionOp() const862 const MachineOperand &MachineInstr::getDebugExpressionOp() const {
863 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
864 unsigned ExpressionOp = isDebugValueList() ? 1 : 3;
865 return getOperand(ExpressionOp);
866 }
867
getDebugExpressionOp()868 MachineOperand &MachineInstr::getDebugExpressionOp() {
869 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
870 unsigned ExpressionOp = isDebugValueList() ? 1 : 3;
871 return getOperand(ExpressionOp);
872 }
873
getDebugExpression() const874 const DIExpression *MachineInstr::getDebugExpression() const {
875 return cast<DIExpression>(getDebugExpressionOp().getMetadata());
876 }
877
isDebugEntryValue() const878 bool MachineInstr::isDebugEntryValue() const {
879 return isDebugValue() && getDebugExpression()->isEntryValue();
880 }
881
882 const TargetRegisterClass*
getRegClassConstraint(unsigned OpIdx,const TargetInstrInfo * TII,const TargetRegisterInfo * TRI) const883 MachineInstr::getRegClassConstraint(unsigned OpIdx,
884 const TargetInstrInfo *TII,
885 const TargetRegisterInfo *TRI) const {
886 assert(getParent() && "Can't have an MBB reference here!");
887 assert(getMF() && "Can't have an MF reference here!");
888 const MachineFunction &MF = *getMF();
889
890 // Most opcodes have fixed constraints in their MCInstrDesc.
891 if (!isInlineAsm())
892 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
893
894 if (!getOperand(OpIdx).isReg())
895 return nullptr;
896
897 // For tied uses on inline asm, get the constraint from the def.
898 unsigned DefIdx;
899 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
900 OpIdx = DefIdx;
901
902 // Inline asm stores register class constraints in the flag word.
903 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
904 if (FlagIdx < 0)
905 return nullptr;
906
907 unsigned Flag = getOperand(FlagIdx).getImm();
908 unsigned RCID;
909 if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse ||
910 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef ||
911 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) &&
912 InlineAsm::hasRegClassConstraint(Flag, RCID))
913 return TRI->getRegClass(RCID);
914
915 // Assume that all registers in a memory operand are pointers.
916 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
917 return TRI->getPointerRegClass(MF);
918
919 return nullptr;
920 }
921
getRegClassConstraintEffectForVReg(Register Reg,const TargetRegisterClass * CurRC,const TargetInstrInfo * TII,const TargetRegisterInfo * TRI,bool ExploreBundle) const922 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
923 Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
924 const TargetRegisterInfo *TRI, bool ExploreBundle) const {
925 // Check every operands inside the bundle if we have
926 // been asked to.
927 if (ExploreBundle)
928 for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
929 ++OpndIt)
930 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
931 OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
932 else
933 // Otherwise, just check the current operands.
934 for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
935 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
936 return CurRC;
937 }
938
getRegClassConstraintEffectForVRegImpl(unsigned OpIdx,Register Reg,const TargetRegisterClass * CurRC,const TargetInstrInfo * TII,const TargetRegisterInfo * TRI) const939 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
940 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
941 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
942 assert(CurRC && "Invalid initial register class");
943 // Check if Reg is constrained by some of its use/def from MI.
944 const MachineOperand &MO = getOperand(OpIdx);
945 if (!MO.isReg() || MO.getReg() != Reg)
946 return CurRC;
947 // If yes, accumulate the constraints through the operand.
948 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
949 }
950
getRegClassConstraintEffect(unsigned OpIdx,const TargetRegisterClass * CurRC,const TargetInstrInfo * TII,const TargetRegisterInfo * TRI) const951 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
952 unsigned OpIdx, const TargetRegisterClass *CurRC,
953 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
954 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
955 const MachineOperand &MO = getOperand(OpIdx);
956 assert(MO.isReg() &&
957 "Cannot get register constraints for non-register operand");
958 assert(CurRC && "Invalid initial register class");
959 if (unsigned SubIdx = MO.getSubReg()) {
960 if (OpRC)
961 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
962 else
963 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
964 } else if (OpRC)
965 CurRC = TRI->getCommonSubClass(CurRC, OpRC);
966 return CurRC;
967 }
968
969 /// Return the number of instructions inside the MI bundle, not counting the
970 /// header instruction.
getBundleSize() const971 unsigned MachineInstr::getBundleSize() const {
972 MachineBasicBlock::const_instr_iterator I = getIterator();
973 unsigned Size = 0;
974 while (I->isBundledWithSucc()) {
975 ++Size;
976 ++I;
977 }
978 return Size;
979 }
980
981 /// Returns true if the MachineInstr has an implicit-use operand of exactly
982 /// the given register (not considering sub/super-registers).
hasRegisterImplicitUseOperand(Register Reg) const983 bool MachineInstr::hasRegisterImplicitUseOperand(Register Reg) const {
984 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
985 const MachineOperand &MO = getOperand(i);
986 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
987 return true;
988 }
989 return false;
990 }
991
992 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
993 /// the specific register or -1 if it is not found. It further tightens
994 /// the search criteria to a use that kills the register if isKill is true.
findRegisterUseOperandIdx(Register Reg,bool isKill,const TargetRegisterInfo * TRI) const995 int MachineInstr::findRegisterUseOperandIdx(
996 Register Reg, bool isKill, const TargetRegisterInfo *TRI) const {
997 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
998 const MachineOperand &MO = getOperand(i);
999 if (!MO.isReg() || !MO.isUse())
1000 continue;
1001 Register MOReg = MO.getReg();
1002 if (!MOReg)
1003 continue;
1004 if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))
1005 if (!isKill || MO.isKill())
1006 return i;
1007 }
1008 return -1;
1009 }
1010
1011 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1012 /// indicating if this instruction reads or writes Reg. This also considers
1013 /// partial defines.
1014 std::pair<bool,bool>
readsWritesVirtualRegister(Register Reg,SmallVectorImpl<unsigned> * Ops) const1015 MachineInstr::readsWritesVirtualRegister(Register Reg,
1016 SmallVectorImpl<unsigned> *Ops) const {
1017 bool PartDef = false; // Partial redefine.
1018 bool FullDef = false; // Full define.
1019 bool Use = false;
1020
1021 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1022 const MachineOperand &MO = getOperand(i);
1023 if (!MO.isReg() || MO.getReg() != Reg)
1024 continue;
1025 if (Ops)
1026 Ops->push_back(i);
1027 if (MO.isUse())
1028 Use |= !MO.isUndef();
1029 else if (MO.getSubReg() && !MO.isUndef())
1030 // A partial def undef doesn't count as reading the register.
1031 PartDef = true;
1032 else
1033 FullDef = true;
1034 }
1035 // A partial redefine uses Reg unless there is also a full define.
1036 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1037 }
1038
1039 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1040 /// the specified register or -1 if it is not found. If isDead is true, defs
1041 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1042 /// also checks if there is a def of a super-register.
1043 int
findRegisterDefOperandIdx(Register Reg,bool isDead,bool Overlap,const TargetRegisterInfo * TRI) const1044 MachineInstr::findRegisterDefOperandIdx(Register Reg, bool isDead, bool Overlap,
1045 const TargetRegisterInfo *TRI) const {
1046 bool isPhys = Register::isPhysicalRegister(Reg);
1047 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1048 const MachineOperand &MO = getOperand(i);
1049 // Accept regmask operands when Overlap is set.
1050 // Ignore them when looking for a specific def operand (Overlap == false).
1051 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1052 return i;
1053 if (!MO.isReg() || !MO.isDef())
1054 continue;
1055 Register MOReg = MO.getReg();
1056 bool Found = (MOReg == Reg);
1057 if (!Found && TRI && isPhys && Register::isPhysicalRegister(MOReg)) {
1058 if (Overlap)
1059 Found = TRI->regsOverlap(MOReg, Reg);
1060 else
1061 Found = TRI->isSubRegister(MOReg, Reg);
1062 }
1063 if (Found && (!isDead || MO.isDead()))
1064 return i;
1065 }
1066 return -1;
1067 }
1068
1069 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1070 /// operand list that is used to represent the predicate. It returns -1 if
1071 /// none is found.
findFirstPredOperandIdx() const1072 int MachineInstr::findFirstPredOperandIdx() const {
1073 // Don't call MCID.findFirstPredOperandIdx() because this variant
1074 // is sometimes called on an instruction that's not yet complete, and
1075 // so the number of operands is less than the MCID indicates. In
1076 // particular, the PTX target does this.
1077 const MCInstrDesc &MCID = getDesc();
1078 if (MCID.isPredicable()) {
1079 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1080 if (MCID.OpInfo[i].isPredicate())
1081 return i;
1082 }
1083
1084 return -1;
1085 }
1086
1087 // MachineOperand::TiedTo is 4 bits wide.
1088 const unsigned TiedMax = 15;
1089
1090 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1091 ///
1092 /// Use and def operands can be tied together, indicated by a non-zero TiedTo
1093 /// field. TiedTo can have these values:
1094 ///
1095 /// 0: Operand is not tied to anything.
1096 /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1097 /// TiedMax: Tied to an operand >= TiedMax-1.
1098 ///
1099 /// The tied def must be one of the first TiedMax operands on a normal
1100 /// instruction. INLINEASM instructions allow more tied defs.
1101 ///
tieOperands(unsigned DefIdx,unsigned UseIdx)1102 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1103 MachineOperand &DefMO = getOperand(DefIdx);
1104 MachineOperand &UseMO = getOperand(UseIdx);
1105 assert(DefMO.isDef() && "DefIdx must be a def operand");
1106 assert(UseMO.isUse() && "UseIdx must be a use operand");
1107 assert(!DefMO.isTied() && "Def is already tied to another use");
1108 assert(!UseMO.isTied() && "Use is already tied to another def");
1109
1110 if (DefIdx < TiedMax)
1111 UseMO.TiedTo = DefIdx + 1;
1112 else {
1113 // Inline asm can use the group descriptors to find tied operands,
1114 // statepoint tied operands are trivial to match (1-1 reg def with reg use),
1115 // but on normal instruction, the tied def must be within the first TiedMax
1116 // operands.
1117 assert((isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) &&
1118 "DefIdx out of range");
1119 UseMO.TiedTo = TiedMax;
1120 }
1121
1122 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1123 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1124 }
1125
1126 /// Given the index of a tied register operand, find the operand it is tied to.
1127 /// Defs are tied to uses and vice versa. Returns the index of the tied operand
1128 /// which must exist.
findTiedOperandIdx(unsigned OpIdx) const1129 unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1130 const MachineOperand &MO = getOperand(OpIdx);
1131 assert(MO.isTied() && "Operand isn't tied");
1132
1133 // Normally TiedTo is in range.
1134 if (MO.TiedTo < TiedMax)
1135 return MO.TiedTo - 1;
1136
1137 // Uses on normal instructions can be out of range.
1138 if (!isInlineAsm() && getOpcode() != TargetOpcode::STATEPOINT) {
1139 // Normal tied defs must be in the 0..TiedMax-1 range.
1140 if (MO.isUse())
1141 return TiedMax - 1;
1142 // MO is a def. Search for the tied use.
1143 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1144 const MachineOperand &UseMO = getOperand(i);
1145 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1146 return i;
1147 }
1148 llvm_unreachable("Can't find tied use");
1149 }
1150
1151 if (getOpcode() == TargetOpcode::STATEPOINT) {
1152 // In STATEPOINT defs correspond 1-1 to GC pointer operands passed
1153 // on registers.
1154 StatepointOpers SO(this);
1155 unsigned CurUseIdx = SO.getFirstGCPtrIdx();
1156 assert(CurUseIdx != -1U && "only gc pointer statepoint operands can be tied");
1157 unsigned NumDefs = getNumDefs();
1158 for (unsigned CurDefIdx = 0; CurDefIdx < NumDefs; ++CurDefIdx) {
1159 while (!getOperand(CurUseIdx).isReg())
1160 CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1161 if (OpIdx == CurDefIdx)
1162 return CurUseIdx;
1163 if (OpIdx == CurUseIdx)
1164 return CurDefIdx;
1165 CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1166 }
1167 llvm_unreachable("Can't find tied use");
1168 }
1169
1170 // Now deal with inline asm by parsing the operand group descriptor flags.
1171 // Find the beginning of each operand group.
1172 SmallVector<unsigned, 8> GroupIdx;
1173 unsigned OpIdxGroup = ~0u;
1174 unsigned NumOps;
1175 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1176 i += NumOps) {
1177 const MachineOperand &FlagMO = getOperand(i);
1178 assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1179 unsigned CurGroup = GroupIdx.size();
1180 GroupIdx.push_back(i);
1181 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1182 // OpIdx belongs to this operand group.
1183 if (OpIdx > i && OpIdx < i + NumOps)
1184 OpIdxGroup = CurGroup;
1185 unsigned TiedGroup;
1186 if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1187 continue;
1188 // Operands in this group are tied to operands in TiedGroup which must be
1189 // earlier. Find the number of operands between the two groups.
1190 unsigned Delta = i - GroupIdx[TiedGroup];
1191
1192 // OpIdx is a use tied to TiedGroup.
1193 if (OpIdxGroup == CurGroup)
1194 return OpIdx - Delta;
1195
1196 // OpIdx is a def tied to this use group.
1197 if (OpIdxGroup == TiedGroup)
1198 return OpIdx + Delta;
1199 }
1200 llvm_unreachable("Invalid tied operand on inline asm");
1201 }
1202
1203 /// clearKillInfo - Clears kill flags on all operands.
1204 ///
clearKillInfo()1205 void MachineInstr::clearKillInfo() {
1206 for (MachineOperand &MO : operands()) {
1207 if (MO.isReg() && MO.isUse())
1208 MO.setIsKill(false);
1209 }
1210 }
1211
substituteRegister(Register FromReg,Register ToReg,unsigned SubIdx,const TargetRegisterInfo & RegInfo)1212 void MachineInstr::substituteRegister(Register FromReg, Register ToReg,
1213 unsigned SubIdx,
1214 const TargetRegisterInfo &RegInfo) {
1215 if (Register::isPhysicalRegister(ToReg)) {
1216 if (SubIdx)
1217 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1218 for (MachineOperand &MO : operands()) {
1219 if (!MO.isReg() || MO.getReg() != FromReg)
1220 continue;
1221 MO.substPhysReg(ToReg, RegInfo);
1222 }
1223 } else {
1224 for (MachineOperand &MO : operands()) {
1225 if (!MO.isReg() || MO.getReg() != FromReg)
1226 continue;
1227 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1228 }
1229 }
1230 }
1231
1232 /// isSafeToMove - Return true if it is safe to move this instruction. If
1233 /// SawStore is set to true, it means that there is a store (or call) between
1234 /// the instruction's location and its intended destination.
isSafeToMove(AAResults * AA,bool & SawStore) const1235 bool MachineInstr::isSafeToMove(AAResults *AA, bool &SawStore) const {
1236 // Ignore stuff that we obviously can't move.
1237 //
1238 // Treat volatile loads as stores. This is not strictly necessary for
1239 // volatiles, but it is required for atomic loads. It is not allowed to move
1240 // a load across an atomic load with Ordering > Monotonic.
1241 if (mayStore() || isCall() || isPHI() ||
1242 (mayLoad() && hasOrderedMemoryRef())) {
1243 SawStore = true;
1244 return false;
1245 }
1246
1247 if (isPosition() || isDebugInstr() || isTerminator() ||
1248 mayRaiseFPException() || hasUnmodeledSideEffects())
1249 return false;
1250
1251 // See if this instruction does a load. If so, we have to guarantee that the
1252 // loaded value doesn't change between the load and the its intended
1253 // destination. The check for isInvariantLoad gives the target the chance to
1254 // classify the load as always returning a constant, e.g. a constant pool
1255 // load.
1256 if (mayLoad() && !isDereferenceableInvariantLoad(AA))
1257 // Otherwise, this is a real load. If there is a store between the load and
1258 // end of block, we can't move it.
1259 return !SawStore;
1260
1261 return true;
1262 }
1263
MemOperandsHaveAlias(const MachineFrameInfo & MFI,AAResults * AA,bool UseTBAA,const MachineMemOperand * MMOa,const MachineMemOperand * MMOb)1264 static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, AAResults *AA,
1265 bool UseTBAA, const MachineMemOperand *MMOa,
1266 const MachineMemOperand *MMOb) {
1267 // The following interface to AA is fashioned after DAGCombiner::isAlias and
1268 // operates with MachineMemOperand offset with some important assumptions:
1269 // - LLVM fundamentally assumes flat address spaces.
1270 // - MachineOperand offset can *only* result from legalization and cannot
1271 // affect queries other than the trivial case of overlap checking.
1272 // - These offsets never wrap and never step outside of allocated objects.
1273 // - There should never be any negative offsets here.
1274 //
1275 // FIXME: Modify API to hide this math from "user"
1276 // Even before we go to AA we can reason locally about some memory objects. It
1277 // can save compile time, and possibly catch some corner cases not currently
1278 // covered.
1279
1280 int64_t OffsetA = MMOa->getOffset();
1281 int64_t OffsetB = MMOb->getOffset();
1282 int64_t MinOffset = std::min(OffsetA, OffsetB);
1283
1284 uint64_t WidthA = MMOa->getSize();
1285 uint64_t WidthB = MMOb->getSize();
1286 bool KnownWidthA = WidthA != MemoryLocation::UnknownSize;
1287 bool KnownWidthB = WidthB != MemoryLocation::UnknownSize;
1288
1289 const Value *ValA = MMOa->getValue();
1290 const Value *ValB = MMOb->getValue();
1291 bool SameVal = (ValA && ValB && (ValA == ValB));
1292 if (!SameVal) {
1293 const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1294 const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1295 if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1296 return false;
1297 if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1298 return false;
1299 if (PSVa && PSVb && (PSVa == PSVb))
1300 SameVal = true;
1301 }
1302
1303 if (SameVal) {
1304 if (!KnownWidthA || !KnownWidthB)
1305 return true;
1306 int64_t MaxOffset = std::max(OffsetA, OffsetB);
1307 int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1308 return (MinOffset + LowWidth > MaxOffset);
1309 }
1310
1311 if (!AA)
1312 return true;
1313
1314 if (!ValA || !ValB)
1315 return true;
1316
1317 assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
1318 assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
1319
1320 int64_t OverlapA =
1321 KnownWidthA ? WidthA + OffsetA - MinOffset : MemoryLocation::UnknownSize;
1322 int64_t OverlapB =
1323 KnownWidthB ? WidthB + OffsetB - MinOffset : MemoryLocation::UnknownSize;
1324
1325 return !AA->isNoAlias(
1326 MemoryLocation(ValA, OverlapA, UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1327 MemoryLocation(ValB, OverlapB,
1328 UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1329 }
1330
mayAlias(AAResults * AA,const MachineInstr & Other,bool UseTBAA) const1331 bool MachineInstr::mayAlias(AAResults *AA, const MachineInstr &Other,
1332 bool UseTBAA) const {
1333 const MachineFunction *MF = getMF();
1334 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1335 const MachineFrameInfo &MFI = MF->getFrameInfo();
1336
1337 // Exclude call instruction which may alter the memory but can not be handled
1338 // by this function.
1339 if (isCall() || Other.isCall())
1340 return true;
1341
1342 // If neither instruction stores to memory, they can't alias in any
1343 // meaningful way, even if they read from the same address.
1344 if (!mayStore() && !Other.mayStore())
1345 return false;
1346
1347 // Both instructions must be memory operations to be able to alias.
1348 if (!mayLoadOrStore() || !Other.mayLoadOrStore())
1349 return false;
1350
1351 // Let the target decide if memory accesses cannot possibly overlap.
1352 if (TII->areMemAccessesTriviallyDisjoint(*this, Other))
1353 return false;
1354
1355 // Memory operations without memory operands may access anything. Be
1356 // conservative and assume `MayAlias`.
1357 if (memoperands_empty() || Other.memoperands_empty())
1358 return true;
1359
1360 // Skip if there are too many memory operands.
1361 auto NumChecks = getNumMemOperands() * Other.getNumMemOperands();
1362 if (NumChecks > TII->getMemOperandAACheckLimit())
1363 return true;
1364
1365 // Check each pair of memory operands from both instructions, which can't
1366 // alias only if all pairs won't alias.
1367 for (auto *MMOa : memoperands())
1368 for (auto *MMOb : Other.memoperands())
1369 if (MemOperandsHaveAlias(MFI, AA, UseTBAA, MMOa, MMOb))
1370 return true;
1371
1372 return false;
1373 }
1374
1375 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1376 /// or volatile memory reference, or if the information describing the memory
1377 /// reference is not available. Return false if it is known to have no ordered
1378 /// memory references.
hasOrderedMemoryRef() const1379 bool MachineInstr::hasOrderedMemoryRef() const {
1380 // An instruction known never to access memory won't have a volatile access.
1381 if (!mayStore() &&
1382 !mayLoad() &&
1383 !isCall() &&
1384 !hasUnmodeledSideEffects())
1385 return false;
1386
1387 // Otherwise, if the instruction has no memory reference information,
1388 // conservatively assume it wasn't preserved.
1389 if (memoperands_empty())
1390 return true;
1391
1392 // Check if any of our memory operands are ordered.
1393 return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
1394 return !MMO->isUnordered();
1395 });
1396 }
1397
1398 /// isDereferenceableInvariantLoad - Return true if this instruction will never
1399 /// trap and is loading from a location whose value is invariant across a run of
1400 /// this function.
isDereferenceableInvariantLoad(AAResults * AA) const1401 bool MachineInstr::isDereferenceableInvariantLoad(AAResults *AA) const {
1402 // If the instruction doesn't load at all, it isn't an invariant load.
1403 if (!mayLoad())
1404 return false;
1405
1406 // If the instruction has lost its memoperands, conservatively assume that
1407 // it may not be an invariant load.
1408 if (memoperands_empty())
1409 return false;
1410
1411 const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1412
1413 for (MachineMemOperand *MMO : memoperands()) {
1414 if (!MMO->isUnordered())
1415 // If the memory operand has ordering side effects, we can't move the
1416 // instruction. Such an instruction is technically an invariant load,
1417 // but the caller code would need updated to expect that.
1418 return false;
1419 if (MMO->isStore()) return false;
1420 if (MMO->isInvariant() && MMO->isDereferenceable())
1421 continue;
1422
1423 // A load from a constant PseudoSourceValue is invariant.
1424 if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
1425 if (PSV->isConstant(&MFI))
1426 continue;
1427
1428 if (const Value *V = MMO->getValue()) {
1429 // If we have an AliasAnalysis, ask it whether the memory is constant.
1430 if (AA &&
1431 AA->pointsToConstantMemory(
1432 MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
1433 continue;
1434 }
1435
1436 // Otherwise assume conservatively.
1437 return false;
1438 }
1439
1440 // Everything checks out.
1441 return true;
1442 }
1443
1444 /// isConstantValuePHI - If the specified instruction is a PHI that always
1445 /// merges together the same virtual register, return the register, otherwise
1446 /// return 0.
isConstantValuePHI() const1447 unsigned MachineInstr::isConstantValuePHI() const {
1448 if (!isPHI())
1449 return 0;
1450 assert(getNumOperands() >= 3 &&
1451 "It's illegal to have a PHI without source operands");
1452
1453 Register Reg = getOperand(1).getReg();
1454 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1455 if (getOperand(i).getReg() != Reg)
1456 return 0;
1457 return Reg;
1458 }
1459
hasUnmodeledSideEffects() const1460 bool MachineInstr::hasUnmodeledSideEffects() const {
1461 if (hasProperty(MCID::UnmodeledSideEffects))
1462 return true;
1463 if (isInlineAsm()) {
1464 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1465 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1466 return true;
1467 }
1468
1469 return false;
1470 }
1471
isLoadFoldBarrier() const1472 bool MachineInstr::isLoadFoldBarrier() const {
1473 return mayStore() || isCall() ||
1474 (hasUnmodeledSideEffects() && !isPseudoProbe());
1475 }
1476
1477 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1478 ///
allDefsAreDead() const1479 bool MachineInstr::allDefsAreDead() const {
1480 for (const MachineOperand &MO : operands()) {
1481 if (!MO.isReg() || MO.isUse())
1482 continue;
1483 if (!MO.isDead())
1484 return false;
1485 }
1486 return true;
1487 }
1488
1489 /// copyImplicitOps - Copy implicit register operands from specified
1490 /// instruction to this instruction.
copyImplicitOps(MachineFunction & MF,const MachineInstr & MI)1491 void MachineInstr::copyImplicitOps(MachineFunction &MF,
1492 const MachineInstr &MI) {
1493 for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
1494 i != e; ++i) {
1495 const MachineOperand &MO = MI.getOperand(i);
1496 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1497 addOperand(MF, MO);
1498 }
1499 }
1500
hasComplexRegisterTies() const1501 bool MachineInstr::hasComplexRegisterTies() const {
1502 const MCInstrDesc &MCID = getDesc();
1503 if (MCID.Opcode == TargetOpcode::STATEPOINT)
1504 return true;
1505 for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1506 const auto &Operand = getOperand(I);
1507 if (!Operand.isReg() || Operand.isDef())
1508 // Ignore the defined registers as MCID marks only the uses as tied.
1509 continue;
1510 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
1511 int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
1512 if (ExpectedTiedIdx != TiedIdx)
1513 return true;
1514 }
1515 return false;
1516 }
1517
getTypeToPrint(unsigned OpIdx,SmallBitVector & PrintedTypes,const MachineRegisterInfo & MRI) const1518 LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1519 const MachineRegisterInfo &MRI) const {
1520 const MachineOperand &Op = getOperand(OpIdx);
1521 if (!Op.isReg())
1522 return LLT{};
1523
1524 if (isVariadic() || OpIdx >= getNumExplicitOperands())
1525 return MRI.getType(Op.getReg());
1526
1527 auto &OpInfo = getDesc().OpInfo[OpIdx];
1528 if (!OpInfo.isGenericType())
1529 return MRI.getType(Op.getReg());
1530
1531 if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1532 return LLT{};
1533
1534 LLT TypeToPrint = MRI.getType(Op.getReg());
1535 // Don't mark the type index printed if it wasn't actually printed: maybe
1536 // another operand with the same type index has an actual type attached:
1537 if (TypeToPrint.isValid())
1538 PrintedTypes.set(OpInfo.getGenericTypeIndex());
1539 return TypeToPrint;
1540 }
1541
1542 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
dump() const1543 LLVM_DUMP_METHOD void MachineInstr::dump() const {
1544 dbgs() << " ";
1545 print(dbgs());
1546 }
1547
dumprImpl(const MachineRegisterInfo & MRI,unsigned Depth,unsigned MaxDepth,SmallPtrSetImpl<const MachineInstr * > & AlreadySeenInstrs) const1548 LLVM_DUMP_METHOD void MachineInstr::dumprImpl(
1549 const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
1550 SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const {
1551 if (Depth >= MaxDepth)
1552 return;
1553 if (!AlreadySeenInstrs.insert(this).second)
1554 return;
1555 // PadToColumn always inserts at least one space.
1556 // Don't mess up the alignment if we don't want any space.
1557 if (Depth)
1558 fdbgs().PadToColumn(Depth * 2);
1559 print(fdbgs());
1560 for (const MachineOperand &MO : operands()) {
1561 if (!MO.isReg() || MO.isDef())
1562 continue;
1563 Register Reg = MO.getReg();
1564 if (Reg.isPhysical())
1565 continue;
1566 const MachineInstr *NewMI = MRI.getUniqueVRegDef(Reg);
1567 if (NewMI == nullptr)
1568 continue;
1569 NewMI->dumprImpl(MRI, Depth + 1, MaxDepth, AlreadySeenInstrs);
1570 }
1571 }
1572
dumpr(const MachineRegisterInfo & MRI,unsigned MaxDepth) const1573 LLVM_DUMP_METHOD void MachineInstr::dumpr(const MachineRegisterInfo &MRI,
1574 unsigned MaxDepth) const {
1575 SmallPtrSet<const MachineInstr *, 16> AlreadySeenInstrs;
1576 dumprImpl(MRI, 0, MaxDepth, AlreadySeenInstrs);
1577 }
1578 #endif
1579
print(raw_ostream & OS,bool IsStandalone,bool SkipOpers,bool SkipDebugLoc,bool AddNewLine,const TargetInstrInfo * TII) const1580 void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1581 bool SkipDebugLoc, bool AddNewLine,
1582 const TargetInstrInfo *TII) const {
1583 const Module *M = nullptr;
1584 const Function *F = nullptr;
1585 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1586 F = &MF->getFunction();
1587 M = F->getParent();
1588 if (!TII)
1589 TII = MF->getSubtarget().getInstrInfo();
1590 }
1591
1592 ModuleSlotTracker MST(M);
1593 if (F)
1594 MST.incorporateFunction(*F);
1595 print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII);
1596 }
1597
print(raw_ostream & OS,ModuleSlotTracker & MST,bool IsStandalone,bool SkipOpers,bool SkipDebugLoc,bool AddNewLine,const TargetInstrInfo * TII) const1598 void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
1599 bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1600 bool AddNewLine, const TargetInstrInfo *TII) const {
1601 // We can be a bit tidier if we know the MachineFunction.
1602 const TargetRegisterInfo *TRI = nullptr;
1603 const MachineRegisterInfo *MRI = nullptr;
1604 const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1605 tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
1606
1607 if (isCFIInstruction())
1608 assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
1609
1610 SmallBitVector PrintedTypes(8);
1611 bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
1612 auto getTiedOperandIdx = [&](unsigned OpIdx) {
1613 if (!ShouldPrintRegisterTies)
1614 return 0U;
1615 const MachineOperand &MO = getOperand(OpIdx);
1616 if (MO.isReg() && MO.isTied() && !MO.isDef())
1617 return findTiedOperandIdx(OpIdx);
1618 return 0U;
1619 };
1620 unsigned StartOp = 0;
1621 unsigned e = getNumOperands();
1622
1623 // Print explicitly defined operands on the left of an assignment syntax.
1624 while (StartOp < e) {
1625 const MachineOperand &MO = getOperand(StartOp);
1626 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1627 break;
1628
1629 if (StartOp != 0)
1630 OS << ", ";
1631
1632 LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
1633 unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1634 MO.print(OS, MST, TypeToPrint, StartOp, /*PrintDef=*/false, IsStandalone,
1635 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1636 ++StartOp;
1637 }
1638
1639 if (StartOp != 0)
1640 OS << " = ";
1641
1642 if (getFlag(MachineInstr::FrameSetup))
1643 OS << "frame-setup ";
1644 if (getFlag(MachineInstr::FrameDestroy))
1645 OS << "frame-destroy ";
1646 if (getFlag(MachineInstr::FmNoNans))
1647 OS << "nnan ";
1648 if (getFlag(MachineInstr::FmNoInfs))
1649 OS << "ninf ";
1650 if (getFlag(MachineInstr::FmNsz))
1651 OS << "nsz ";
1652 if (getFlag(MachineInstr::FmArcp))
1653 OS << "arcp ";
1654 if (getFlag(MachineInstr::FmContract))
1655 OS << "contract ";
1656 if (getFlag(MachineInstr::FmAfn))
1657 OS << "afn ";
1658 if (getFlag(MachineInstr::FmReassoc))
1659 OS << "reassoc ";
1660 if (getFlag(MachineInstr::NoUWrap))
1661 OS << "nuw ";
1662 if (getFlag(MachineInstr::NoSWrap))
1663 OS << "nsw ";
1664 if (getFlag(MachineInstr::IsExact))
1665 OS << "exact ";
1666 if (getFlag(MachineInstr::NoFPExcept))
1667 OS << "nofpexcept ";
1668 if (getFlag(MachineInstr::NoMerge))
1669 OS << "nomerge ";
1670
1671 // Print the opcode name.
1672 if (TII)
1673 OS << TII->getName(getOpcode());
1674 else
1675 OS << "UNKNOWN";
1676
1677 if (SkipOpers)
1678 return;
1679
1680 // Print the rest of the operands.
1681 bool FirstOp = true;
1682 unsigned AsmDescOp = ~0u;
1683 unsigned AsmOpCount = 0;
1684
1685 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1686 // Print asm string.
1687 OS << " ";
1688 const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1689 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
1690 unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1691 getOperand(OpIdx).print(OS, MST, TypeToPrint, OpIdx, /*PrintDef=*/true, IsStandalone,
1692 ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1693 IntrinsicInfo);
1694
1695 // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1696 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1697 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1698 OS << " [sideeffect]";
1699 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1700 OS << " [mayload]";
1701 if (ExtraInfo & InlineAsm::Extra_MayStore)
1702 OS << " [maystore]";
1703 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1704 OS << " [isconvergent]";
1705 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1706 OS << " [alignstack]";
1707 if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1708 OS << " [attdialect]";
1709 if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1710 OS << " [inteldialect]";
1711
1712 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1713 FirstOp = false;
1714 }
1715
1716 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1717 const MachineOperand &MO = getOperand(i);
1718
1719 if (FirstOp) FirstOp = false; else OS << ",";
1720 OS << " ";
1721
1722 if (isDebugValue() && MO.isMetadata()) {
1723 // Pretty print DBG_VALUE* instructions.
1724 auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1725 if (DIV && !DIV->getName().empty())
1726 OS << "!\"" << DIV->getName() << '\"';
1727 else {
1728 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1729 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1730 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1731 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1732 }
1733 } else if (isDebugLabel() && MO.isMetadata()) {
1734 // Pretty print DBG_LABEL instructions.
1735 auto *DIL = dyn_cast<DILabel>(MO.getMetadata());
1736 if (DIL && !DIL->getName().empty())
1737 OS << "\"" << DIL->getName() << '\"';
1738 else {
1739 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1740 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1741 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1742 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1743 }
1744 } else if (i == AsmDescOp && MO.isImm()) {
1745 // Pretty print the inline asm operand descriptor.
1746 OS << '$' << AsmOpCount++;
1747 unsigned Flag = MO.getImm();
1748 OS << ":[";
1749 OS << InlineAsm::getKindName(InlineAsm::getKind(Flag));
1750
1751 unsigned RCID = 0;
1752 if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
1753 InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1754 if (TRI) {
1755 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1756 } else
1757 OS << ":RC" << RCID;
1758 }
1759
1760 if (InlineAsm::isMemKind(Flag)) {
1761 unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1762 OS << ":" << InlineAsm::getMemConstraintName(MCID);
1763 }
1764
1765 unsigned TiedTo = 0;
1766 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1767 OS << " tiedto:$" << TiedTo;
1768
1769 OS << ']';
1770
1771 // Compute the index of the next operand descriptor.
1772 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1773 } else {
1774 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1775 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1776 if (MO.isImm() && isOperandSubregIdx(i))
1777 MachineOperand::printSubRegIdx(OS, MO.getImm(), TRI);
1778 else
1779 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1780 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1781 }
1782 }
1783
1784 // Print any optional symbols attached to this instruction as-if they were
1785 // operands.
1786 if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
1787 if (!FirstOp) {
1788 FirstOp = false;
1789 OS << ',';
1790 }
1791 OS << " pre-instr-symbol ";
1792 MachineOperand::printSymbol(OS, *PreInstrSymbol);
1793 }
1794 if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
1795 if (!FirstOp) {
1796 FirstOp = false;
1797 OS << ',';
1798 }
1799 OS << " post-instr-symbol ";
1800 MachineOperand::printSymbol(OS, *PostInstrSymbol);
1801 }
1802 if (MDNode *HeapAllocMarker = getHeapAllocMarker()) {
1803 if (!FirstOp) {
1804 FirstOp = false;
1805 OS << ',';
1806 }
1807 OS << " heap-alloc-marker ";
1808 HeapAllocMarker->printAsOperand(OS, MST);
1809 }
1810
1811 if (DebugInstrNum) {
1812 if (!FirstOp)
1813 OS << ",";
1814 OS << " debug-instr-number " << DebugInstrNum;
1815 }
1816
1817 if (!SkipDebugLoc) {
1818 if (const DebugLoc &DL = getDebugLoc()) {
1819 if (!FirstOp)
1820 OS << ',';
1821 OS << " debug-location ";
1822 DL->printAsOperand(OS, MST);
1823 }
1824 }
1825
1826 if (!memoperands_empty()) {
1827 SmallVector<StringRef, 0> SSNs;
1828 const LLVMContext *Context = nullptr;
1829 std::unique_ptr<LLVMContext> CtxPtr;
1830 const MachineFrameInfo *MFI = nullptr;
1831 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1832 MFI = &MF->getFrameInfo();
1833 Context = &MF->getFunction().getContext();
1834 } else {
1835 CtxPtr = std::make_unique<LLVMContext>();
1836 Context = CtxPtr.get();
1837 }
1838
1839 OS << " :: ";
1840 bool NeedComma = false;
1841 for (const MachineMemOperand *Op : memoperands()) {
1842 if (NeedComma)
1843 OS << ", ";
1844 Op->print(OS, MST, SSNs, *Context, MFI, TII);
1845 NeedComma = true;
1846 }
1847 }
1848
1849 if (SkipDebugLoc)
1850 return;
1851
1852 bool HaveSemi = false;
1853
1854 // Print debug location information.
1855 if (const DebugLoc &DL = getDebugLoc()) {
1856 if (!HaveSemi) {
1857 OS << ';';
1858 HaveSemi = true;
1859 }
1860 OS << ' ';
1861 DL.print(OS);
1862 }
1863
1864 // Print extra comments for DEBUG_VALUE.
1865 if (isDebugValue() && getDebugVariableOp().isMetadata()) {
1866 if (!HaveSemi) {
1867 OS << ";";
1868 HaveSemi = true;
1869 }
1870 auto *DV = getDebugVariable();
1871 OS << " line no:" << DV->getLine();
1872 if (isIndirectDebugValue())
1873 OS << " indirect";
1874 }
1875 // TODO: DBG_LABEL
1876
1877 if (AddNewLine)
1878 OS << '\n';
1879 }
1880
addRegisterKilled(Register IncomingReg,const TargetRegisterInfo * RegInfo,bool AddIfNotFound)1881 bool MachineInstr::addRegisterKilled(Register IncomingReg,
1882 const TargetRegisterInfo *RegInfo,
1883 bool AddIfNotFound) {
1884 bool isPhysReg = Register::isPhysicalRegister(IncomingReg);
1885 bool hasAliases = isPhysReg &&
1886 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1887 bool Found = false;
1888 SmallVector<unsigned,4> DeadOps;
1889 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1890 MachineOperand &MO = getOperand(i);
1891 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1892 continue;
1893
1894 // DEBUG_VALUE nodes do not contribute to code generation and should
1895 // always be ignored. Failure to do so may result in trying to modify
1896 // KILL flags on DEBUG_VALUE nodes.
1897 if (MO.isDebug())
1898 continue;
1899
1900 Register Reg = MO.getReg();
1901 if (!Reg)
1902 continue;
1903
1904 if (Reg == IncomingReg) {
1905 if (!Found) {
1906 if (MO.isKill())
1907 // The register is already marked kill.
1908 return true;
1909 if (isPhysReg && isRegTiedToDefOperand(i))
1910 // Two-address uses of physregs must not be marked kill.
1911 return true;
1912 MO.setIsKill();
1913 Found = true;
1914 }
1915 } else if (hasAliases && MO.isKill() && Register::isPhysicalRegister(Reg)) {
1916 // A super-register kill already exists.
1917 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1918 return true;
1919 if (RegInfo->isSubRegister(IncomingReg, Reg))
1920 DeadOps.push_back(i);
1921 }
1922 }
1923
1924 // Trim unneeded kill operands.
1925 while (!DeadOps.empty()) {
1926 unsigned OpIdx = DeadOps.back();
1927 if (getOperand(OpIdx).isImplicit() &&
1928 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1929 RemoveOperand(OpIdx);
1930 else
1931 getOperand(OpIdx).setIsKill(false);
1932 DeadOps.pop_back();
1933 }
1934
1935 // If not found, this means an alias of one of the operands is killed. Add a
1936 // new implicit operand if required.
1937 if (!Found && AddIfNotFound) {
1938 addOperand(MachineOperand::CreateReg(IncomingReg,
1939 false /*IsDef*/,
1940 true /*IsImp*/,
1941 true /*IsKill*/));
1942 return true;
1943 }
1944 return Found;
1945 }
1946
clearRegisterKills(Register Reg,const TargetRegisterInfo * RegInfo)1947 void MachineInstr::clearRegisterKills(Register Reg,
1948 const TargetRegisterInfo *RegInfo) {
1949 if (!Register::isPhysicalRegister(Reg))
1950 RegInfo = nullptr;
1951 for (MachineOperand &MO : operands()) {
1952 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1953 continue;
1954 Register OpReg = MO.getReg();
1955 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
1956 MO.setIsKill(false);
1957 }
1958 }
1959
addRegisterDead(Register Reg,const TargetRegisterInfo * RegInfo,bool AddIfNotFound)1960 bool MachineInstr::addRegisterDead(Register Reg,
1961 const TargetRegisterInfo *RegInfo,
1962 bool AddIfNotFound) {
1963 bool isPhysReg = Register::isPhysicalRegister(Reg);
1964 bool hasAliases = isPhysReg &&
1965 MCRegAliasIterator(Reg, RegInfo, false).isValid();
1966 bool Found = false;
1967 SmallVector<unsigned,4> DeadOps;
1968 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1969 MachineOperand &MO = getOperand(i);
1970 if (!MO.isReg() || !MO.isDef())
1971 continue;
1972 Register MOReg = MO.getReg();
1973 if (!MOReg)
1974 continue;
1975
1976 if (MOReg == Reg) {
1977 MO.setIsDead();
1978 Found = true;
1979 } else if (hasAliases && MO.isDead() &&
1980 Register::isPhysicalRegister(MOReg)) {
1981 // There exists a super-register that's marked dead.
1982 if (RegInfo->isSuperRegister(Reg, MOReg))
1983 return true;
1984 if (RegInfo->isSubRegister(Reg, MOReg))
1985 DeadOps.push_back(i);
1986 }
1987 }
1988
1989 // Trim unneeded dead operands.
1990 while (!DeadOps.empty()) {
1991 unsigned OpIdx = DeadOps.back();
1992 if (getOperand(OpIdx).isImplicit() &&
1993 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1994 RemoveOperand(OpIdx);
1995 else
1996 getOperand(OpIdx).setIsDead(false);
1997 DeadOps.pop_back();
1998 }
1999
2000 // If not found, this means an alias of one of the operands is dead. Add a
2001 // new implicit operand if required.
2002 if (Found || !AddIfNotFound)
2003 return Found;
2004
2005 addOperand(MachineOperand::CreateReg(Reg,
2006 true /*IsDef*/,
2007 true /*IsImp*/,
2008 false /*IsKill*/,
2009 true /*IsDead*/));
2010 return true;
2011 }
2012
clearRegisterDeads(Register Reg)2013 void MachineInstr::clearRegisterDeads(Register Reg) {
2014 for (MachineOperand &MO : operands()) {
2015 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
2016 continue;
2017 MO.setIsDead(false);
2018 }
2019 }
2020
setRegisterDefReadUndef(Register Reg,bool IsUndef)2021 void MachineInstr::setRegisterDefReadUndef(Register Reg, bool IsUndef) {
2022 for (MachineOperand &MO : operands()) {
2023 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
2024 continue;
2025 MO.setIsUndef(IsUndef);
2026 }
2027 }
2028
addRegisterDefined(Register Reg,const TargetRegisterInfo * RegInfo)2029 void MachineInstr::addRegisterDefined(Register Reg,
2030 const TargetRegisterInfo *RegInfo) {
2031 if (Register::isPhysicalRegister(Reg)) {
2032 MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo);
2033 if (MO)
2034 return;
2035 } else {
2036 for (const MachineOperand &MO : operands()) {
2037 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
2038 MO.getSubReg() == 0)
2039 return;
2040 }
2041 }
2042 addOperand(MachineOperand::CreateReg(Reg,
2043 true /*IsDef*/,
2044 true /*IsImp*/));
2045 }
2046
setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,const TargetRegisterInfo & TRI)2047 void MachineInstr::setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
2048 const TargetRegisterInfo &TRI) {
2049 bool HasRegMask = false;
2050 for (MachineOperand &MO : operands()) {
2051 if (MO.isRegMask()) {
2052 HasRegMask = true;
2053 continue;
2054 }
2055 if (!MO.isReg() || !MO.isDef()) continue;
2056 Register Reg = MO.getReg();
2057 if (!Reg.isPhysical())
2058 continue;
2059 // If there are no uses, including partial uses, the def is dead.
2060 if (llvm::none_of(UsedRegs,
2061 [&](MCRegister Use) { return TRI.regsOverlap(Use, Reg); }))
2062 MO.setIsDead();
2063 }
2064
2065 // This is a call with a register mask operand.
2066 // Mask clobbers are always dead, so add defs for the non-dead defines.
2067 if (HasRegMask)
2068 for (const Register &UsedReg : UsedRegs)
2069 addRegisterDefined(UsedReg, &TRI);
2070 }
2071
2072 unsigned
getHashValue(const MachineInstr * const & MI)2073 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
2074 // Build up a buffer of hash code components.
2075 SmallVector<size_t, 16> HashComponents;
2076 HashComponents.reserve(MI->getNumOperands() + 1);
2077 HashComponents.push_back(MI->getOpcode());
2078 for (const MachineOperand &MO : MI->operands()) {
2079 if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg()))
2080 continue; // Skip virtual register defs.
2081
2082 HashComponents.push_back(hash_value(MO));
2083 }
2084 return hash_combine_range(HashComponents.begin(), HashComponents.end());
2085 }
2086
emitError(StringRef Msg) const2087 void MachineInstr::emitError(StringRef Msg) const {
2088 // Find the source location cookie.
2089 uint64_t LocCookie = 0;
2090 const MDNode *LocMD = nullptr;
2091 for (unsigned i = getNumOperands(); i != 0; --i) {
2092 if (getOperand(i-1).isMetadata() &&
2093 (LocMD = getOperand(i-1).getMetadata()) &&
2094 LocMD->getNumOperands() != 0) {
2095 if (const ConstantInt *CI =
2096 mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
2097 LocCookie = CI->getZExtValue();
2098 break;
2099 }
2100 }
2101 }
2102
2103 if (const MachineBasicBlock *MBB = getParent())
2104 if (const MachineFunction *MF = MBB->getParent())
2105 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
2106 report_fatal_error(Msg);
2107 }
2108
BuildMI(MachineFunction & MF,const DebugLoc & DL,const MCInstrDesc & MCID,bool IsIndirect,Register Reg,const MDNode * Variable,const MDNode * Expr)2109 MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2110 const MCInstrDesc &MCID, bool IsIndirect,
2111 Register Reg, const MDNode *Variable,
2112 const MDNode *Expr) {
2113 assert(isa<DILocalVariable>(Variable) && "not a variable");
2114 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2115 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2116 "Expected inlined-at fields to agree");
2117 auto MIB = BuildMI(MF, DL, MCID).addReg(Reg);
2118 if (IsIndirect)
2119 MIB.addImm(0U);
2120 else
2121 MIB.addReg(0U);
2122 return MIB.addMetadata(Variable).addMetadata(Expr);
2123 }
2124
BuildMI(MachineFunction & MF,const DebugLoc & DL,const MCInstrDesc & MCID,bool IsIndirect,const MachineOperand & MO,const MDNode * Variable,const MDNode * Expr)2125 MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2126 const MCInstrDesc &MCID, bool IsIndirect,
2127 const MachineOperand &MO,
2128 const MDNode *Variable, const MDNode *Expr) {
2129 assert(isa<DILocalVariable>(Variable) && "not a variable");
2130 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2131 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2132 "Expected inlined-at fields to agree");
2133 if (MO.isReg())
2134 return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr);
2135
2136 auto MIB = BuildMI(MF, DL, MCID).add(MO);
2137 if (IsIndirect)
2138 MIB.addImm(0U);
2139 else
2140 MIB.addReg(0U);
2141 return MIB.addMetadata(Variable).addMetadata(Expr);
2142 }
2143
BuildMI(MachineFunction & MF,const DebugLoc & DL,const MCInstrDesc & MCID,bool IsIndirect,ArrayRef<MachineOperand> MOs,const MDNode * Variable,const MDNode * Expr)2144 MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2145 const MCInstrDesc &MCID, bool IsIndirect,
2146 ArrayRef<MachineOperand> MOs,
2147 const MDNode *Variable, const MDNode *Expr) {
2148 assert(isa<DILocalVariable>(Variable) && "not a variable");
2149 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2150 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2151 "Expected inlined-at fields to agree");
2152 if (MCID.Opcode == TargetOpcode::DBG_VALUE)
2153 return BuildMI(MF, DL, MCID, IsIndirect, MOs[0], Variable, Expr);
2154
2155 auto MIB = BuildMI(MF, DL, MCID);
2156 MIB.addMetadata(Variable).addMetadata(Expr);
2157 for (const MachineOperand &MO : MOs)
2158 if (MO.isReg())
2159 MIB.addReg(MO.getReg());
2160 else
2161 MIB.add(MO);
2162 return MIB;
2163 }
2164
BuildMI(MachineBasicBlock & BB,MachineBasicBlock::iterator I,const DebugLoc & DL,const MCInstrDesc & MCID,bool IsIndirect,Register Reg,const MDNode * Variable,const MDNode * Expr)2165 MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2166 MachineBasicBlock::iterator I,
2167 const DebugLoc &DL, const MCInstrDesc &MCID,
2168 bool IsIndirect, Register Reg,
2169 const MDNode *Variable, const MDNode *Expr) {
2170 MachineFunction &MF = *BB.getParent();
2171 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
2172 BB.insert(I, MI);
2173 return MachineInstrBuilder(MF, MI);
2174 }
2175
BuildMI(MachineBasicBlock & BB,MachineBasicBlock::iterator I,const DebugLoc & DL,const MCInstrDesc & MCID,bool IsIndirect,MachineOperand & MO,const MDNode * Variable,const MDNode * Expr)2176 MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2177 MachineBasicBlock::iterator I,
2178 const DebugLoc &DL, const MCInstrDesc &MCID,
2179 bool IsIndirect, MachineOperand &MO,
2180 const MDNode *Variable, const MDNode *Expr) {
2181 MachineFunction &MF = *BB.getParent();
2182 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr);
2183 BB.insert(I, MI);
2184 return MachineInstrBuilder(MF, *MI);
2185 }
2186
BuildMI(MachineBasicBlock & BB,MachineBasicBlock::iterator I,const DebugLoc & DL,const MCInstrDesc & MCID,bool IsIndirect,ArrayRef<MachineOperand> MOs,const MDNode * Variable,const MDNode * Expr)2187 MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2188 MachineBasicBlock::iterator I,
2189 const DebugLoc &DL, const MCInstrDesc &MCID,
2190 bool IsIndirect, ArrayRef<MachineOperand> MOs,
2191 const MDNode *Variable, const MDNode *Expr) {
2192 MachineFunction &MF = *BB.getParent();
2193 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MOs, Variable, Expr);
2194 BB.insert(I, MI);
2195 return MachineInstrBuilder(MF, *MI);
2196 }
2197
2198 /// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
2199 /// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
2200 static const DIExpression *
computeExprForSpill(const MachineInstr & MI,SmallVectorImpl<const MachineOperand * > & SpilledOperands)2201 computeExprForSpill(const MachineInstr &MI,
2202 SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2203 assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&
2204 "Expected inlined-at fields to agree");
2205
2206 const DIExpression *Expr = MI.getDebugExpression();
2207 if (MI.isIndirectDebugValue()) {
2208 assert(MI.getDebugOffset().getImm() == 0 &&
2209 "DBG_VALUE with nonzero offset");
2210 Expr = DIExpression::prepend(Expr, DIExpression::DerefBefore);
2211 } else if (MI.isDebugValueList()) {
2212 // We will replace the spilled register with a frame index, so
2213 // immediately deref all references to the spilled register.
2214 std::array<uint64_t, 1> Ops{{dwarf::DW_OP_deref}};
2215 for (const MachineOperand *Op : SpilledOperands) {
2216 unsigned OpIdx = MI.getDebugOperandIndex(Op);
2217 Expr = DIExpression::appendOpsToArg(Expr, Ops, OpIdx);
2218 }
2219 }
2220 return Expr;
2221 }
computeExprForSpill(const MachineInstr & MI,Register SpillReg)2222 static const DIExpression *computeExprForSpill(const MachineInstr &MI,
2223 Register SpillReg) {
2224 assert(MI.hasDebugOperandForReg(SpillReg) && "Spill Reg is not used in MI.");
2225 SmallVector<const MachineOperand *> SpillOperands;
2226 for (const MachineOperand &Op : MI.getDebugOperandsForReg(SpillReg))
2227 SpillOperands.push_back(&Op);
2228 return computeExprForSpill(MI, SpillOperands);
2229 }
2230
buildDbgValueForSpill(MachineBasicBlock & BB,MachineBasicBlock::iterator I,const MachineInstr & Orig,int FrameIndex,Register SpillReg)2231 MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB,
2232 MachineBasicBlock::iterator I,
2233 const MachineInstr &Orig,
2234 int FrameIndex, Register SpillReg) {
2235 const DIExpression *Expr = computeExprForSpill(Orig, SpillReg);
2236 MachineInstrBuilder NewMI =
2237 BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());
2238 // Non-Variadic Operands: Location, Offset, Variable, Expression
2239 // Variadic Operands: Variable, Expression, Locations...
2240 if (Orig.isNonListDebugValue())
2241 NewMI.addFrameIndex(FrameIndex).addImm(0U);
2242 NewMI.addMetadata(Orig.getDebugVariable()).addMetadata(Expr);
2243 if (Orig.isDebugValueList()) {
2244 for (const MachineOperand &Op : Orig.debug_operands())
2245 if (Op.isReg() && Op.getReg() == SpillReg)
2246 NewMI.addFrameIndex(FrameIndex);
2247 else
2248 NewMI.add(MachineOperand(Op));
2249 }
2250 return NewMI;
2251 }
buildDbgValueForSpill(MachineBasicBlock & BB,MachineBasicBlock::iterator I,const MachineInstr & Orig,int FrameIndex,SmallVectorImpl<const MachineOperand * > & SpilledOperands)2252 MachineInstr *llvm::buildDbgValueForSpill(
2253 MachineBasicBlock &BB, MachineBasicBlock::iterator I,
2254 const MachineInstr &Orig, int FrameIndex,
2255 SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2256 const DIExpression *Expr = computeExprForSpill(Orig, SpilledOperands);
2257 MachineInstrBuilder NewMI =
2258 BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());
2259 // Non-Variadic Operands: Location, Offset, Variable, Expression
2260 // Variadic Operands: Variable, Expression, Locations...
2261 if (Orig.isNonListDebugValue())
2262 NewMI.addFrameIndex(FrameIndex).addImm(0U);
2263 NewMI.addMetadata(Orig.getDebugVariable()).addMetadata(Expr);
2264 if (Orig.isDebugValueList()) {
2265 for (const MachineOperand &Op : Orig.debug_operands())
2266 if (is_contained(SpilledOperands, &Op))
2267 NewMI.addFrameIndex(FrameIndex);
2268 else
2269 NewMI.add(MachineOperand(Op));
2270 }
2271 return NewMI;
2272 }
2273
updateDbgValueForSpill(MachineInstr & Orig,int FrameIndex,Register Reg)2274 void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex,
2275 Register Reg) {
2276 const DIExpression *Expr = computeExprForSpill(Orig, Reg);
2277 if (Orig.isNonListDebugValue())
2278 Orig.getDebugOffset().ChangeToImmediate(0U);
2279 for (MachineOperand &Op : Orig.getDebugOperandsForReg(Reg))
2280 Op.ChangeToFrameIndex(FrameIndex);
2281 Orig.getDebugExpressionOp().setMetadata(Expr);
2282 }
2283
collectDebugValues(SmallVectorImpl<MachineInstr * > & DbgValues)2284 void MachineInstr::collectDebugValues(
2285 SmallVectorImpl<MachineInstr *> &DbgValues) {
2286 MachineInstr &MI = *this;
2287 if (!MI.getOperand(0).isReg())
2288 return;
2289
2290 MachineBasicBlock::iterator DI = MI; ++DI;
2291 for (MachineBasicBlock::iterator DE = MI.getParent()->end();
2292 DI != DE; ++DI) {
2293 if (!DI->isDebugValue())
2294 return;
2295 if (DI->hasDebugOperandForReg(MI.getOperand(0).getReg()))
2296 DbgValues.push_back(&*DI);
2297 }
2298 }
2299
changeDebugValuesDefReg(Register Reg)2300 void MachineInstr::changeDebugValuesDefReg(Register Reg) {
2301 // Collect matching debug values.
2302 SmallVector<MachineInstr *, 2> DbgValues;
2303
2304 if (!getOperand(0).isReg())
2305 return;
2306
2307 Register DefReg = getOperand(0).getReg();
2308 auto *MRI = getRegInfo();
2309 for (auto &MO : MRI->use_operands(DefReg)) {
2310 auto *DI = MO.getParent();
2311 if (!DI->isDebugValue())
2312 continue;
2313 if (DI->hasDebugOperandForReg(DefReg)) {
2314 DbgValues.push_back(DI);
2315 }
2316 }
2317
2318 // Propagate Reg to debug value instructions.
2319 for (auto *DBI : DbgValues)
2320 for (MachineOperand &Op : DBI->getDebugOperandsForReg(DefReg))
2321 Op.setReg(Reg);
2322 }
2323
2324 using MMOList = SmallVector<const MachineMemOperand *, 2>;
2325
getSpillSlotSize(const MMOList & Accesses,const MachineFrameInfo & MFI)2326 static unsigned getSpillSlotSize(const MMOList &Accesses,
2327 const MachineFrameInfo &MFI) {
2328 unsigned Size = 0;
2329 for (auto A : Accesses)
2330 if (MFI.isSpillSlotObjectIndex(
2331 cast<FixedStackPseudoSourceValue>(A->getPseudoValue())
2332 ->getFrameIndex()))
2333 Size += A->getSize();
2334 return Size;
2335 }
2336
2337 Optional<unsigned>
getSpillSize(const TargetInstrInfo * TII) const2338 MachineInstr::getSpillSize(const TargetInstrInfo *TII) const {
2339 int FI;
2340 if (TII->isStoreToStackSlotPostFE(*this, FI)) {
2341 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2342 if (MFI.isSpillSlotObjectIndex(FI))
2343 return (*memoperands_begin())->getSize();
2344 }
2345 return None;
2346 }
2347
2348 Optional<unsigned>
getFoldedSpillSize(const TargetInstrInfo * TII) const2349 MachineInstr::getFoldedSpillSize(const TargetInstrInfo *TII) const {
2350 MMOList Accesses;
2351 if (TII->hasStoreToStackSlot(*this, Accesses))
2352 return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2353 return None;
2354 }
2355
2356 Optional<unsigned>
getRestoreSize(const TargetInstrInfo * TII) const2357 MachineInstr::getRestoreSize(const TargetInstrInfo *TII) const {
2358 int FI;
2359 if (TII->isLoadFromStackSlotPostFE(*this, FI)) {
2360 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2361 if (MFI.isSpillSlotObjectIndex(FI))
2362 return (*memoperands_begin())->getSize();
2363 }
2364 return None;
2365 }
2366
2367 Optional<unsigned>
getFoldedRestoreSize(const TargetInstrInfo * TII) const2368 MachineInstr::getFoldedRestoreSize(const TargetInstrInfo *TII) const {
2369 MMOList Accesses;
2370 if (TII->hasLoadFromStackSlot(*this, Accesses))
2371 return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2372 return None;
2373 }
2374
getDebugInstrNum()2375 unsigned MachineInstr::getDebugInstrNum() {
2376 if (DebugInstrNum == 0)
2377 DebugInstrNum = getParent()->getParent()->getNewDebugInstrNum();
2378 return DebugInstrNum;
2379 }
2380
getDebugInstrNum(MachineFunction & MF)2381 unsigned MachineInstr::getDebugInstrNum(MachineFunction &MF) {
2382 if (DebugInstrNum == 0)
2383 DebugInstrNum = MF.getNewDebugInstrNum();
2384 return DebugInstrNum;
2385 }
2386