1//=- AArch64SchedA57.td - ARM Cortex-A57 Scheduling Defs -----*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for ARM Cortex-A57 to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// The Cortex-A57 is a traditional superscalar microprocessor with a 16// conservative 3-wide in-order stage for decode and dispatch. Combined with the 17// much wider out-of-order issue stage, this produced a need to carefully 18// schedule micro-ops so that all three decoded each cycle are successfully 19// issued as the reservation station(s) simply don't stay occupied for long. 20// Therefore, IssueWidth is set to the narrower of the two at three, while still 21// modeling the machine as out-of-order. 22 23def CortexA57Model : SchedMachineModel { 24 let IssueWidth = 3; // 3-way decode and dispatch 25 let MicroOpBufferSize = 128; // 128 micro-op re-order buffer 26 let LoadLatency = 4; // Optimistic load latency 27 let MispredictPenalty = 14; // Fetch + Decode/Rename/Dispatch + Branch 28 29 // Enable partial & runtime unrolling. The magic number is chosen based on 30 // experiments and benchmarking data. 31 let LoopMicroOpBufferSize = 16; 32 let CompleteModel = 1; 33 34 list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F, 35 PAUnsupported.F, 36 SMEUnsupported.F); 37} 38 39//===----------------------------------------------------------------------===// 40// Define each kind of processor resource and number available on Cortex-A57. 41// Cortex A-57 has 8 pipelines that each has its own 8-entry queue where 42// micro-ops wait for their operands and then issue out-of-order. 43 44def A57UnitB : ProcResource<1>; // Type B micro-ops 45def A57UnitI : ProcResource<2>; // Type I micro-ops 46def A57UnitM : ProcResource<1>; // Type M micro-ops 47def A57UnitL : ProcResource<1>; // Type L micro-ops 48def A57UnitS : ProcResource<1>; // Type S micro-ops 49def A57UnitX : ProcResource<1>; // Type X micro-ops 50def A57UnitW : ProcResource<1>; // Type W micro-ops 51let SchedModel = CortexA57Model in { 52 def A57UnitV : ProcResGroup<[A57UnitX, A57UnitW]>; // Type V micro-ops 53} 54 55let SchedModel = CortexA57Model in { 56 57//===----------------------------------------------------------------------===// 58// Define customized scheduler read/write types specific to the Cortex-A57. 59 60include "AArch64SchedA57WriteRes.td" 61 62//===----------------------------------------------------------------------===// 63// Map the target-defined scheduler read/write resources and latency for 64// Cortex-A57. The Cortex-A57 types are directly associated with resources, so 65// defining the aliases precludes the need for mapping them using WriteRes. The 66// aliases are sufficient for creating a coarse, working model. As the model 67// evolves, InstRWs will be used to override some of these SchedAliases. 68// 69// WARNING: Using SchedAliases is convenient and works well for latency and 70// resource lookup for instructions. However, this creates an entry in 71// AArch64WriteLatencyTable with a WriteResourceID of 0, breaking 72// any SchedReadAdvance since the lookup will fail. 73 74def : SchedAlias<WriteImm, A57Write_1cyc_1I>; 75def : SchedAlias<WriteI, A57Write_1cyc_1I>; 76def : SchedAlias<WriteISReg, A57Write_2cyc_1M>; 77def : SchedAlias<WriteIEReg, A57Write_2cyc_1M>; 78def : SchedAlias<WriteExtr, A57Write_1cyc_1I>; 79def : SchedAlias<WriteIS, A57Write_1cyc_1I>; 80def : SchedAlias<WriteID32, A57Write_19cyc_1M>; 81def : SchedAlias<WriteID64, A57Write_35cyc_1M>; 82def : WriteRes<WriteIM32, [A57UnitM]> { let Latency = 3; } 83def : WriteRes<WriteIM64, [A57UnitM]> { let Latency = 5; } 84def : SchedAlias<WriteBr, A57Write_1cyc_1B>; 85def : SchedAlias<WriteBrReg, A57Write_1cyc_1B>; 86def : SchedAlias<WriteLD, A57Write_4cyc_1L>; 87def : SchedAlias<WriteST, A57Write_1cyc_1S>; 88def : SchedAlias<WriteSTP, A57Write_1cyc_1S>; 89def : SchedAlias<WriteAdr, A57Write_1cyc_1I>; 90def : SchedAlias<WriteLDIdx, A57Write_4cyc_1I_1L>; 91def : SchedAlias<WriteSTIdx, A57Write_1cyc_1I_1S>; 92def : SchedAlias<WriteF, A57Write_3cyc_1V>; 93def : SchedAlias<WriteFCmp, A57Write_3cyc_1V>; 94def : SchedAlias<WriteFCvt, A57Write_5cyc_1V>; 95def : SchedAlias<WriteFCopy, A57Write_5cyc_1L>; 96def : SchedAlias<WriteFImm, A57Write_3cyc_1V>; 97def : WriteRes<WriteFMul, [A57UnitV]> { let Latency = 5;} 98def : SchedAlias<WriteFDiv, A57Write_17cyc_1W>; 99def : SchedAlias<WriteVd, A57Write_3cyc_1V>; 100def : SchedAlias<WriteVq, A57Write_3cyc_1V>; 101def : SchedAlias<WriteVLD, A57Write_5cyc_1L>; 102def : SchedAlias<WriteVST, A57Write_1cyc_1S>; 103 104def : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 105 106def : WriteRes<WriteSys, []> { let Latency = 1; } 107def : WriteRes<WriteBarrier, []> { let Latency = 1; } 108def : WriteRes<WriteHint, []> { let Latency = 1; } 109 110def : WriteRes<WriteLDHi, []> { let Latency = 4; } 111 112// Forwarding logic is only modeled for multiply and accumulate 113def : ReadAdvance<ReadI, 0>; 114def : ReadAdvance<ReadISReg, 0>; 115def : ReadAdvance<ReadIEReg, 0>; 116def : ReadAdvance<ReadIM, 0>; 117def : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>; 118def : ReadAdvance<ReadID, 0>; 119def : ReadAdvance<ReadExtrHi, 0>; 120def : ReadAdvance<ReadST, 0>; 121def : ReadAdvance<ReadAdrBase, 0>; 122def : ReadAdvance<ReadVLD, 0>; 123 124 125//===----------------------------------------------------------------------===// 126// Specialize the coarse model by associating instruction groups with the 127// subtarget-defined types. As the modeled is refined, this will override most 128// of the above ShchedAlias mappings. 129 130// Miscellaneous 131// ----------------------------------------------------------------------------- 132 133def : InstRW<[WriteI], (instrs COPY)>; 134 135 136// Branch Instructions 137// ----------------------------------------------------------------------------- 138 139def : InstRW<[A57Write_1cyc_1B_1I], (instrs BL)>; 140def : InstRW<[A57Write_2cyc_1B_1I], (instrs BLR)>; 141 142 143// Shifted Register with Shift == 0 144// ---------------------------------------------------------------------------- 145 146def A57WriteISReg : SchedWriteVariant<[ 147 SchedVar<RegShiftedPred, [WriteISReg]>, 148 SchedVar<NoSchedPred, [WriteI]>]>; 149def : InstRW<[A57WriteISReg], (instregex ".*rs$")>; 150 151 152// Divide and Multiply Instructions 153// ----------------------------------------------------------------------------- 154 155// Multiply high 156def : InstRW<[A57Write_6cyc_1M], (instrs SMULHrr, UMULHrr)>; 157 158 159// Miscellaneous Data-Processing Instructions 160// ----------------------------------------------------------------------------- 161 162def : InstRW<[A57Write_1cyc_1I], (instrs EXTRWrri)>; 163def : InstRW<[A57Write_3cyc_1I_1M], (instrs EXTRXrri)>; 164def : InstRW<[A57Write_2cyc_1M], (instregex "BFM")>; 165 166 167// Cryptography Extensions 168// ----------------------------------------------------------------------------- 169 170def A57ReadAES : SchedReadAdvance<3, [A57Write_3cyc_1W]>; 171def : InstRW<[A57Write_3cyc_1W], (instregex "^AES[DE]")>; 172def : InstRW<[A57Write_3cyc_1W, A57ReadAES], (instregex "^AESI?MC")>; 173def : InstRW<[A57Write_6cyc_2V], (instregex "^SHA1SU0")>; 174def : InstRW<[A57Write_3cyc_1W], (instregex "^SHA1(H|SU1)")>; 175def : InstRW<[A57Write_6cyc_2W], (instregex "^SHA1[CMP]")>; 176def : InstRW<[A57Write_3cyc_1W], (instregex "^SHA256SU0")>; 177def : InstRW<[A57Write_6cyc_2W], (instregex "^SHA256(H|H2|SU1)")>; 178def : InstRW<[A57Write_3cyc_1W], (instregex "^CRC32")>; 179 180 181// Vector Load 182// ----------------------------------------------------------------------------- 183 184def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1i(8|16|32)$")>; 185def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1i(8|16|32)_POST$")>; 186def : InstRW<[A57Write_5cyc_1L], (instregex "LD1i(64)$")>; 187def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1i(64)_POST$")>; 188 189def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1Rv(8b|4h|2s)$")>; 190def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(8b|4h|2s)_POST$")>; 191def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Rv(1d)$")>; 192def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Rv(1d)_POST$")>; 193def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)$")>; 194def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>; 195 196def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Onev(8b|4h|2s|1d)$")>; 197def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>; 198def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Onev(16b|8h|4s|2d)$")>; 199def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>; 200def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Twov(8b|4h|2s|1d)$")>; 201def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>; 202def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Twov(16b|8h|4s|2d)$")>; 203def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>; 204def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Threev(8b|4h|2s|1d)$")>; 205def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>; 206def : InstRW<[A57Write_7cyc_3L], (instregex "LD1Threev(16b|8h|4s|2d)$")>; 207def : InstRW<[A57Write_7cyc_3L, WriteAdr], (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>; 208def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Fourv(8b|4h|2s|1d)$")>; 209def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>; 210def : InstRW<[A57Write_8cyc_4L], (instregex "LD1Fourv(16b|8h|4s|2d)$")>; 211def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>; 212 213def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD2i(8|16)$")>; 214def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2i(8|16)_POST$")>; 215def : InstRW<[A57Write_6cyc_2L], (instregex "LD2i(32)$")>; 216def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD2i(32)_POST$")>; 217def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2i(64)$")>; 218def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2i(64)_POST$")>; 219 220def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2Rv(8b|4h|2s)$")>; 221def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2Rv(8b|4h|2s)_POST$")>; 222def : InstRW<[A57Write_5cyc_1L], (instregex "LD2Rv(1d)$")>; 223def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD2Rv(1d)_POST$")>; 224def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)$")>; 225def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>; 226 227def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2Twov(8b|4h|2s)$")>; 228def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2Twov(8b|4h|2s)_POST$")>; 229def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD2Twov(16b|8h|4s)$")>; 230def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD2Twov(16b|8h|4s)_POST$")>; 231def : InstRW<[A57Write_6cyc_2L], (instregex "LD2Twov(2d)$")>; 232def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD2Twov(2d)_POST$")>; 233 234def : InstRW<[A57Write_9cyc_1L_3V], (instregex "LD3i(8|16)$")>; 235def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr], (instregex "LD3i(8|16)_POST$")>; 236def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD3i(32)$")>; 237def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD3i(32)_POST$")>; 238def : InstRW<[A57Write_6cyc_2L], (instregex "LD3i(64)$")>; 239def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD3i(64)_POST$")>; 240 241def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD3Rv(8b|4h|2s)$")>; 242def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD3Rv(8b|4h|2s)_POST$")>; 243def : InstRW<[A57Write_6cyc_2L], (instregex "LD3Rv(1d)$")>; 244def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD3Rv(1d)_POST$")>; 245def : InstRW<[A57Write_9cyc_1L_3V], (instregex "LD3Rv(16b|8h|4s)$")>; 246def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr], (instregex "LD3Rv(16b|8h|4s)_POST$")>; 247def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD3Rv(2d)$")>; 248def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD3Rv(2d)_POST$")>; 249 250def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD3Threev(8b|4h|2s)$")>; 251def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD3Threev(8b|4h|2s)_POST$")>; 252def : InstRW<[A57Write_10cyc_3L_4V], (instregex "LD3Threev(16b|8h|4s)$")>; 253def : InstRW<[A57Write_10cyc_3L_4V, WriteAdr], (instregex "LD3Threev(16b|8h|4s)_POST$")>; 254def : InstRW<[A57Write_8cyc_4L], (instregex "LD3Threev(2d)$")>; 255def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD3Threev(2d)_POST$")>; 256 257def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4i(8|16)$")>; 258def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(8|16)_POST$")>; 259def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD4i(32)$")>; 260def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD4i(32)_POST$")>; 261def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4i(64)$")>; 262def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(64)_POST$")>; 263 264def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD4Rv(8b|4h|2s)$")>; 265def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD4Rv(8b|4h|2s)_POST$")>; 266def : InstRW<[A57Write_6cyc_2L], (instregex "LD4Rv(1d)$")>; 267def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD4Rv(1d)_POST$")>; 268def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4Rv(16b|8h|4s)$")>; 269def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4Rv(16b|8h|4s)_POST$")>; 270def : InstRW<[A57Write_9cyc_2L_4V], (instregex "LD4Rv(2d)$")>; 271def : InstRW<[A57Write_9cyc_2L_4V, WriteAdr], (instregex "LD4Rv(2d)_POST$")>; 272 273def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD4Fourv(8b|4h|2s)$")>; 274def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD4Fourv(8b|4h|2s)_POST$")>; 275def : InstRW<[A57Write_11cyc_4L_4V], (instregex "LD4Fourv(16b|8h|4s)$")>; 276def : InstRW<[A57Write_11cyc_4L_4V, WriteAdr], (instregex "LD4Fourv(16b|8h|4s)_POST$")>; 277def : InstRW<[A57Write_8cyc_4L], (instregex "LD4Fourv(2d)$")>; 278def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD4Fourv(2d)_POST$")>; 279 280// Vector Store 281// ----------------------------------------------------------------------------- 282 283def : InstRW<[A57Write_1cyc_1S], (instregex "ST1i(8|16|32)$")>; 284def : InstRW<[A57Write_1cyc_1S, WriteAdr], (instregex "ST1i(8|16|32)_POST$")>; 285def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST1i(64)$")>; 286def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST1i(64)_POST$")>; 287 288def : InstRW<[A57Write_1cyc_1S], (instregex "ST1Onev(8b|4h|2s|1d)$")>; 289def : InstRW<[A57Write_1cyc_1S, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>; 290def : InstRW<[A57Write_2cyc_2S], (instregex "ST1Onev(16b|8h|4s|2d)$")>; 291def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>; 292def : InstRW<[A57Write_2cyc_2S], (instregex "ST1Twov(8b|4h|2s|1d)$")>; 293def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>; 294def : InstRW<[A57Write_4cyc_4S], (instregex "ST1Twov(16b|8h|4s|2d)$")>; 295def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>; 296def : InstRW<[A57Write_3cyc_3S], (instregex "ST1Threev(8b|4h|2s|1d)$")>; 297def : InstRW<[A57Write_3cyc_3S, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>; 298def : InstRW<[A57Write_6cyc_6S], (instregex "ST1Threev(16b|8h|4s|2d)$")>; 299def : InstRW<[A57Write_6cyc_6S, WriteAdr], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>; 300def : InstRW<[A57Write_4cyc_4S], (instregex "ST1Fourv(8b|4h|2s|1d)$")>; 301def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>; 302def : InstRW<[A57Write_8cyc_8S], (instregex "ST1Fourv(16b|8h|4s|2d)$")>; 303def : InstRW<[A57Write_8cyc_8S, WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>; 304 305def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST2i(8|16|32)$")>; 306def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST2i(8|16|32)_POST$")>; 307def : InstRW<[A57Write_2cyc_2S], (instregex "ST2i(64)$")>; 308def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST2i(64)_POST$")>; 309 310def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST2Twov(8b|4h|2s)$")>; 311def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>; 312def : InstRW<[A57Write_4cyc_4S_2V], (instregex "ST2Twov(16b|8h|4s)$")>; 313def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr], (instregex "ST2Twov(16b|8h|4s)_POST$")>; 314def : InstRW<[A57Write_4cyc_4S], (instregex "ST2Twov(2d)$")>; 315def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST2Twov(2d)_POST$")>; 316 317def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST3i(8|16)$")>; 318def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST3i(8|16)_POST$")>; 319def : InstRW<[A57Write_3cyc_3S], (instregex "ST3i(32)$")>; 320def : InstRW<[A57Write_3cyc_3S, WriteAdr], (instregex "ST3i(32)_POST$")>; 321def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST3i(64)$")>; 322def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST3i(64)_POST$")>; 323 324def : InstRW<[A57Write_3cyc_3S_2V], (instregex "ST3Threev(8b|4h|2s)$")>; 325def : InstRW<[A57Write_3cyc_3S_2V, WriteAdr], (instregex "ST3Threev(8b|4h|2s)_POST$")>; 326def : InstRW<[A57Write_6cyc_6S_4V], (instregex "ST3Threev(16b|8h|4s)$")>; 327def : InstRW<[A57Write_6cyc_6S_4V, WriteAdr], (instregex "ST3Threev(16b|8h|4s)_POST$")>; 328def : InstRW<[A57Write_6cyc_6S], (instregex "ST3Threev(2d)$")>; 329def : InstRW<[A57Write_6cyc_6S, WriteAdr], (instregex "ST3Threev(2d)_POST$")>; 330 331def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST4i(8|16)$")>; 332def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST4i(8|16)_POST$")>; 333def : InstRW<[A57Write_4cyc_4S], (instregex "ST4i(32)$")>; 334def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST4i(32)_POST$")>; 335def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST4i(64)$")>; 336def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST4i(64)_POST$")>; 337 338def : InstRW<[A57Write_4cyc_4S_2V], (instregex "ST4Fourv(8b|4h|2s)$")>; 339def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr], (instregex "ST4Fourv(8b|4h|2s)_POST$")>; 340def : InstRW<[A57Write_8cyc_8S_4V], (instregex "ST4Fourv(16b|8h|4s)$")>; 341def : InstRW<[A57Write_8cyc_8S_4V, WriteAdr], (instregex "ST4Fourv(16b|8h|4s)_POST$")>; 342def : InstRW<[A57Write_8cyc_8S], (instregex "ST4Fourv(2d)$")>; 343def : InstRW<[A57Write_8cyc_8S, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>; 344 345// Vector - Integer 346// ----------------------------------------------------------------------------- 347 348// Reference for forms in this group 349// D form - v8i8, v4i16, v2i32 350// Q form - v16i8, v8i16, v4i32 351// D form - v1i8, v1i16, v1i32, v1i64 352// Q form - v16i8, v8i16, v4i32, v2i64 353// D form - v8i8_v8i16, v4i16_v4i32, v2i32_v2i64 354// Q form - v16i8_v8i16, v8i16_v4i32, v4i32_v2i64 355 356// Cortex A57 Software Optimization Guide Sec 3.14 357// Advance for absolute diff accum, pairwise add and accumulate, shift accumulate 358def A57ReadIVA3 : SchedReadAdvance<3, [A57Write_4cyc_1X_NonMul_Forward, A57Write_5cyc_2X_NonMul_Forward]>; 359 360// ASIMD absolute diff accum, D-form 361def : InstRW<[A57Write_4cyc_1X_NonMul_Forward, A57ReadIVA3], (instregex "^[SU]ABA(v8i8|v4i16|v2i32)$")>; 362// ASIMD absolute diff accum, Q-form 363def : InstRW<[A57Write_5cyc_2X_NonMul_Forward, A57ReadIVA3], (instregex "^[SU]ABA(v16i8|v8i16|v4i32)$")>; 364// ASIMD absolute diff accum long 365def : InstRW<[A57Write_4cyc_1X_NonMul_Forward, A57ReadIVA3], (instregex "^[SU]ABAL")>; 366 367// ASIMD arith, reduce, 4H/4S 368def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>; 369// ASIMD arith, reduce, 8B/8H 370def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU]?ADDL?V(v8i16|v4i32)v$")>; 371// ASIMD arith, reduce, 16B 372def : InstRW<[A57Write_8cyc_2X], (instregex "^[SU]?ADDL?Vv16i8v$")>; 373 374// ASIMD max/min, reduce, 4H/4S 375def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU](MIN|MAX)V(v4i16|v4i32)v$")>; 376// ASIMD max/min, reduce, 8B/8H 377def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>; 378// ASIMD max/min, reduce, 16B 379def : InstRW<[A57Write_8cyc_2X], (instregex "^[SU](MIN|MAX)Vv16i8v$")>; 380 381// ASIMD multiply, D-form 382// MUL 383def : InstRW<[A57Write_5cyc_1W_Mul_Forward], (instregex "^MUL(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)(_indexed)?$")>; 384// PMUL, SQDMULH, SQRDMULH 385def : InstRW<[A57Write_5cyc_1W], (instregex "^(PMUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)(_indexed)?$")>; 386 387// ASIMD multiply, Q-form 388// MUL 389def : InstRW<[A57Write_6cyc_2W_Mul_Forward], (instregex "^MUL(v16i8|v8i16|v4i32)(_indexed)?$")>; 390// PMUL, SQDMULH, SQRDMULH 391def : InstRW<[A57Write_6cyc_2W], (instregex "^(PMUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?$")>; 392 393// Cortex A57 Software Optimization Guide Sec 3.14 394def A57ReadIVMA4 : SchedReadAdvance<4 , [A57Write_5cyc_1W_Mul_Forward, A57Write_6cyc_2W_Mul_Forward]>; 395def A57ReadIVMA3 : SchedReadAdvance<3 , [A57Write_5cyc_1W_Mul_Forward, A57Write_6cyc_2W_Mul_Forward]>; 396 397// ASIMD multiply accumulate, D-form 398def : InstRW<[A57Write_5cyc_1W_Mul_Forward, A57ReadIVMA4], (instregex "^ML[AS](v8i8|v4i16|v2i32)(_indexed)?$")>; 399// ASIMD multiply accumulate, Q-form 400def : InstRW<[A57Write_6cyc_2W_Mul_Forward, A57ReadIVMA4], (instregex "^ML[AS](v16i8|v8i16|v4i32)(_indexed)?$")>; 401 402// ASIMD multiply accumulate long 403// ASIMD multiply accumulate saturating long 404def : InstRW<[A57Write_5cyc_1W_Mul_Forward, A57ReadIVMA4], (instregex "^(S|U)ML[AS]L")>; 405def : InstRW<[A57Write_5cyc_1W_Mul_Forward, A57ReadIVMA3], (instregex "^SQDML[AS]L")>; 406 407// ASIMD multiply long 408def : InstRW<[A57Write_5cyc_1W_Mul_Forward], (instregex "^(S|U)MULL")>; 409def : InstRW<[A57Write_5cyc_1W], (instregex "^SQDMULL")>; 410def : InstRW<[A57Write_5cyc_1W], (instregex "^PMULL(v8i8|v16i8)")>; 411def : InstRW<[A57Write_3cyc_1W], (instregex "^PMULL(v1i64|v2i64)")>; 412 413// ASIMD pairwise add and accumulate 414// ASIMD shift accumulate 415def : InstRW<[A57Write_4cyc_1X_NonMul_Forward, A57ReadIVA3], (instregex "^[SU]ADALP")>; 416def : InstRW<[A57Write_4cyc_1X_NonMul_Forward, A57ReadIVA3], (instregex "^(S|SR|U|UR)SRA")>; 417 418// ASIMD shift by immed, complex 419def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?(Q|R){1,2}SHR")>; 420def : InstRW<[A57Write_4cyc_1X], (instregex "^SQSHLU")>; 421 422 423// ASIMD shift by register, basic, Q-form 424def : InstRW<[A57Write_4cyc_2X], (instregex "^[SU]SHL(v16i8|v8i16|v4i32|v2i64)")>; 425 426// ASIMD shift by register, complex, D-form 427def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>; 428 429// ASIMD shift by register, complex, Q-form 430def : InstRW<[A57Write_5cyc_2X], (instregex "^[SU][QR]{1,2}SHL(v16i8|v8i16|v4i32|v2i64)")>; 431 432 433// Vector - Floating Point 434// ----------------------------------------------------------------------------- 435 436// Reference for forms in this group 437// D form - v2f32 438// Q form - v4f32, v2f64 439// D form - 32, 64 440// D form - v1i32, v1i64 441// D form - v2i32 442// Q form - v4i32, v2i64 443 444// ASIMD FP arith, normal, D-form 445def : InstRW<[A57Write_5cyc_1V], (instregex "^(FABD|FADD|FSUB)(v2f32|32|64|v2i32p)")>; 446// ASIMD FP arith, normal, Q-form 447def : InstRW<[A57Write_5cyc_2V], (instregex "^(FABD|FADD|FSUB)(v4f32|v2f64|v2i64p)")>; 448 449// ASIMD FP arith, pairwise, D-form 450def : InstRW<[A57Write_5cyc_1V], (instregex "^FADDP(v2f32|32|64|v2i32)")>; 451// ASIMD FP arith, pairwise, Q-form 452def : InstRW<[A57Write_9cyc_3V], (instregex "^FADDP(v4f32|v2f64|v2i64)")>; 453 454// ASIMD FP compare, D-form 455def : InstRW<[A57Write_5cyc_1V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v2f32|32|64|v1i32|v2i32|v1i64)")>; 456// ASIMD FP compare, Q-form 457def : InstRW<[A57Write_5cyc_2V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v4f32|v2f64|v4i32|v2i64)")>; 458 459// ASIMD FP convert, long and narrow 460def : InstRW<[A57Write_8cyc_3V], (instregex "^FCVT(L|N|XN)v")>; 461// ASIMD FP convert, other, D-form 462def : InstRW<[A57Write_5cyc_1V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i64)")>; 463// ASIMD FP convert, other, Q-form 464def : InstRW<[A57Write_5cyc_2V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v4f32|v2f64|v4i32|v2i64)")>; 465 466// ASIMD FP divide, D-form, F32 467def : InstRW<[A57Write_17cyc_1W], (instregex "FDIVv2f32")>; 468// ASIMD FP divide, Q-form, F32 469def : InstRW<[A57Write_34cyc_2W], (instregex "FDIVv4f32")>; 470// ASIMD FP divide, Q-form, F64 471def : InstRW<[A57Write_64cyc_2W], (instregex "FDIVv2f64")>; 472 473// Note: These were simply duplicated from ASIMD FDIV because of missing documentation 474// ASIMD FP square root, D-form, F32 475def : InstRW<[A57Write_17cyc_1W], (instregex "FSQRTv2f32")>; 476// ASIMD FP square root, Q-form, F32 477def : InstRW<[A57Write_34cyc_2W], (instregex "FSQRTv4f32")>; 478// ASIMD FP square root, Q-form, F64 479def : InstRW<[A57Write_64cyc_2W], (instregex "FSQRTv2f64")>; 480 481// ASIMD FP max/min, normal, D-form 482def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?(v2f32)")>; 483// ASIMD FP max/min, normal, Q-form 484def : InstRW<[A57Write_5cyc_2V], (instregex "^(FMAX|FMIN)(NM)?(v4f32|v2f64)")>; 485// ASIMD FP max/min, pairwise, D-form 486def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?P(v2f32|v2i32)")>; 487// ASIMD FP max/min, pairwise, Q-form 488def : InstRW<[A57Write_9cyc_3V], (instregex "^(FMAX|FMIN)(NM)?P(v4f32|v2f64|v2i64)")>; 489// ASIMD FP max/min, reduce 490def : InstRW<[A57Write_10cyc_3V], (instregex "^(FMAX|FMIN)(NM)?Vv")>; 491 492// ASIMD FP multiply, D-form, FZ 493def : InstRW<[A57Write_5cyc_1V_FP_Forward], (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>; 494// ASIMD FP multiply, Q-form, FZ 495def : InstRW<[A57Write_5cyc_2V_FP_Forward], (instregex "^FMULX?(v4f32|v2f64|v4i32|v2i64)")>; 496 497// ASIMD FP multiply accumulate, D-form, FZ 498// ASIMD FP multiply accumulate, Q-form, FZ 499def A57WriteFPVMAD : SchedWriteRes<[A57UnitV]> { let Latency = 9; } 500def A57WriteFPVMAQ : SchedWriteRes<[A57UnitV, A57UnitV]> { let Latency = 10; } 501 502// Cortex A57 Software Optimization Guide Sec 3.15 503// Advances from FP mul and mul-accum to mul-accum 504def A57ReadFPVMA5 : SchedReadAdvance<5, [A57WriteFPVMAD, A57WriteFPVMAQ, A57Write_5cyc_1V_FP_Forward, A57Write_5cyc_2V_FP_Forward]>; 505def A57ReadFPVMA6 : SchedReadAdvance<6, [A57WriteFPVMAD, A57WriteFPVMAQ, A57Write_5cyc_1V_FP_Forward, A57Write_5cyc_2V_FP_Forward]>; 506 507def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>; 508def : InstRW<[A57WriteFPVMAQ, A57ReadFPVMA6], (instregex "^FML[AS](v4f32|v2f64|v4i32|v2i64)")>; 509 510// ASIMD FP round, D-form 511def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT[AIMNPXZ](v2f32)")>; 512// ASIMD FP round, Q-form 513def : InstRW<[A57Write_5cyc_2V], (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>; 514 515 516// Vector - Miscellaneous 517// ----------------------------------------------------------------------------- 518 519// Reference for forms in this group 520// D form - v8i8, v4i16, v2i32 521// Q form - v16i8, v8i16, v4i32 522// D form - v1i8, v1i16, v1i32, v1i64 523// Q form - v16i8, v8i16, v4i32, v2i64 524 525// ASIMD bitwise insert, Q-form 526def : InstRW<[A57Write_3cyc_2V], (instregex "^(BIF|BIT|BSL|BSP)v16i8")>; 527 528// ASIMD duplicate, gen reg, D-form and Q-form 529def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^CPY")>; 530def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^DUPv.+gpr")>; 531 532// ASIMD move, saturating 533def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]QXTU?N")>; 534 535// ASIMD reciprocal estimate, D-form 536def : InstRW<[A57Write_5cyc_1V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f32|v1i32|v2i32|v1i64)")>; 537// ASIMD reciprocal estimate, Q-form 538def : InstRW<[A57Write_5cyc_2V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f64|v4f32|v4i32)")>; 539 540// ASIMD reciprocal step, D-form, FZ 541def : InstRW<[A57Write_9cyc_1V], (instregex "^F(RECP|RSQRT)S(v2f32|v1i32|v2i32|v1i64|32|64)")>; 542// ASIMD reciprocal step, Q-form, FZ 543def : InstRW<[A57Write_9cyc_2V], (instregex "^F(RECP|RSQRT)S(v2f64|v4f32|v4i32)")>; 544 545// ASIMD table lookup, D-form 546def : InstRW<[A57Write_3cyc_1V], (instregex "^TB[LX]v8i8One")>; 547def : InstRW<[A57Write_6cyc_2V], (instregex "^TB[LX]v8i8Two")>; 548def : InstRW<[A57Write_9cyc_3V], (instregex "^TB[LX]v8i8Three")>; 549def : InstRW<[A57Write_12cyc_4V], (instregex "^TB[LX]v8i8Four")>; 550// ASIMD table lookup, Q-form 551def : InstRW<[A57Write_6cyc_3V], (instregex "^TB[LX]v16i8One")>; 552def : InstRW<[A57Write_9cyc_5V], (instregex "^TB[LX]v16i8Two")>; 553def : InstRW<[A57Write_12cyc_7V], (instregex "^TB[LX]v16i8Three")>; 554def : InstRW<[A57Write_15cyc_9V], (instregex "^TB[LX]v16i8Four")>; 555 556// ASIMD transfer, element to gen reg 557def : InstRW<[A57Write_6cyc_1I_1L], (instregex "^[SU]MOVv")>; 558 559// ASIMD transfer, gen reg to element 560def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^INSv")>; 561 562// ASIMD unzip/zip, Q-form 563def : InstRW<[A57Write_6cyc_3V], (instregex "^(UZP|ZIP)(1|2)(v16i8|v8i16|v4i32|v2i64)")>; 564 565 566// Remainder 567// ----------------------------------------------------------------------------- 568 569def : InstRW<[A57Write_5cyc_1V], (instregex "^F(ADD|SUB)[DS]rr")>; 570 571// Cortex A57 Software Optimization Guide Sec 3.10 572def A57WriteFPMA : SchedWriteRes<[A57UnitV]> { let Latency = 9; } 573def A57ReadFPMA5 : SchedReadAdvance<5, [A57WriteFPMA, WriteFMul]>; 574def A57ReadFPM : SchedReadAdvance<0>; 575def : InstRW<[A57WriteFPMA, A57ReadFPM, A57ReadFPM, A57ReadFPMA5], (instregex "^FN?M(ADD|SUB)[DS]rrr")>; 576 577def : InstRW<[A57Write_10cyc_1L_1V], (instregex "^[FSU]CVT[AMNPZ][SU](_Int)?[SU]?[XW]?[DS]?[rds]i?")>; 578def : InstRW<[A57Write_10cyc_1L_1V], (instregex "^[SU]CVTF")>; 579 580def : InstRW<[A57Write_32cyc_1W], (instrs FDIVDrr)>; 581def : InstRW<[A57Write_17cyc_1W], (instrs FDIVSrr)>; 582 583def : InstRW<[A57Write_5cyc_1V], (instregex "^F(MAX|MIN).+rr")>; 584 585def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT.+r")>; 586 587def : InstRW<[A57Write_32cyc_1W], (instrs FSQRTDr)>; 588def : InstRW<[A57Write_17cyc_1W], (instrs FSQRTSr)>; 589 590def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDNPDi)>; 591def : InstRW<[A57Write_6cyc_2L, WriteLDHi], (instrs LDNPQi)>; 592def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDNPSi)>; 593def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDPDi)>; 594def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPDpost)>; 595def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPDpre)>; 596def : InstRW<[A57Write_6cyc_2L, WriteLDHi], (instrs LDPQi)>; 597def : InstRW<[A57Write_6cyc_2L, WriteLDHi, WriteAdr], (instrs LDPQpost)>; 598def : InstRW<[A57Write_6cyc_2L, WriteLDHi, WriteAdr], (instrs LDPQpre)>; 599def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi], (instrs LDPSWi)>; 600def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi, WriteAdr], (instrs LDPSWpost)>; 601def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi, WriteAdr], (instrs LDPSWpre)>; 602def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDPSi)>; 603def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPSpost)>; 604def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPSpre)>; 605def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRBpost)>; 606def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRBpre)>; 607def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRBroW)>; 608def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRBroX)>; 609def : InstRW<[A57Write_5cyc_1L], (instrs LDRBui)>; 610def : InstRW<[A57Write_5cyc_1L], (instrs LDRDl)>; 611def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRDpost)>; 612def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRDpre)>; 613def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRDroW)>; 614def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRDroX)>; 615def : InstRW<[A57Write_5cyc_1L], (instrs LDRDui)>; 616def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRHHroW)>; 617def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRHHroX)>; 618def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRHpost)>; 619def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRHpre)>; 620def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRHroW)>; 621def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRHroX)>; 622def : InstRW<[A57Write_5cyc_1L], (instrs LDRHui)>; 623def : InstRW<[A57Write_5cyc_1L], (instrs LDRQl)>; 624def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRQpost)>; 625def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRQpre)>; 626def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRQroW)>; 627def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRQroX)>; 628def : InstRW<[A57Write_5cyc_1L], (instrs LDRQui)>; 629def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHWroW)>; 630def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHWroX)>; 631def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHXroW)>; 632def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHXroX)>; 633def : InstRW<[A57Write_5cyc_1L], (instrs LDRSl)>; 634def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRSpost)>; 635def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRSpre)>; 636def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRSroW)>; 637def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRSroX)>; 638def : InstRW<[A57Write_5cyc_1L], (instrs LDRSui)>; 639def : InstRW<[A57Write_5cyc_1L], (instrs LDURBi)>; 640def : InstRW<[A57Write_5cyc_1L], (instrs LDURDi)>; 641def : InstRW<[A57Write_5cyc_1L], (instrs LDURHi)>; 642def : InstRW<[A57Write_5cyc_1L], (instrs LDURQi)>; 643def : InstRW<[A57Write_5cyc_1L], (instrs LDURSi)>; 644 645def : InstRW<[A57Write_2cyc_2S], (instrs STNPDi)>; 646def : InstRW<[A57Write_4cyc_1I_4S], (instrs STNPQi)>; 647def : InstRW<[A57Write_2cyc_2S], (instrs STNPXi)>; 648def : InstRW<[A57Write_2cyc_2S], (instrs STPDi)>; 649def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPDpost)>; 650def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPDpre)>; 651def : InstRW<[A57Write_4cyc_1I_4S], (instrs STPQi)>; 652def : InstRW<[WriteAdr, A57Write_4cyc_1I_4S], (instrs STPQpost)>; 653def : InstRW<[WriteAdr, A57Write_4cyc_2I_4S], (instrs STPQpre)>; 654def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPSpost)>; 655def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPSpre)>; 656def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPWpost)>; 657def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPWpre)>; 658def : InstRW<[A57Write_2cyc_2S], (instrs STPXi)>; 659def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPXpost)>; 660def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPXpre)>; 661def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBBpost)>; 662def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBBpre)>; 663def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBpost)>; 664def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRBpre)>; 665def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRBroW)>; 666def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRBroX)>; 667def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRDpost)>; 668def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRDpre)>; 669def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHHpost)>; 670def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHHpre)>; 671def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHHroW)>; 672def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHHroX)>; 673def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHpost)>; 674def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRHpre)>; 675def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHroW)>; 676def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHroX)>; 677def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQpost)>; 678def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STRQpre)>; 679def : InstRW<[A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQroW)>; 680def : InstRW<[A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQroX)>; 681def : InstRW<[A57Write_2cyc_1I_2S], (instrs STRQui)>; 682def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRSpost)>; 683def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRSpre)>; 684def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRWpost)>; 685def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRWpre)>; 686def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRXpost)>; 687def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRXpre)>; 688def : InstRW<[A57Write_2cyc_2S], (instrs STURQi)>; 689 690} // SchedModel = CortexA57Model 691