1//=- AArch64SchedExynosM3.td - Samsung Exynos M3 Sched Defs --*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for the Samsung Exynos M3 to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// The Exynos-M3 is an advanced superscalar microprocessor with a 6-wide 16// in-order stage for decode and dispatch and a wider issue stage. 17// The execution units and loads and stores are out-of-order. 18 19def ExynosM3Model : SchedMachineModel { 20 let IssueWidth = 6; // Up to 6 uops per cycle. 21 let MicroOpBufferSize = 228; // ROB size. 22 let LoopMicroOpBufferSize = 40; // Based on the instruction queue size. 23 let LoadLatency = 4; // Optimistic load cases. 24 let MispredictPenalty = 16; // Minimum branch misprediction penalty. 25 let CompleteModel = 1; // Use the default model otherwise. 26 27 list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F, 28 PAUnsupported.F, 29 SMEUnsupported.F); 30} 31 32//===----------------------------------------------------------------------===// 33// Define each kind of processor resource and number available on the Exynos-M3, 34// which has 12 pipelines, each with its own queue with out-of-order dispatch. 35 36let SchedModel = ExynosM3Model in { 37 38def M3UnitA : ProcResource<2>; // Simple integer 39def M3UnitC : ProcResource<2>; // Simple and complex integer 40def M3UnitD : ProcResource<1>; // Integer division (inside C0, serialized) 41def M3UnitB : ProcResource<2>; // Branch 42def M3UnitL : ProcResource<2>; // Load 43def M3UnitS : ProcResource<1>; // Store 44def M3PipeF0 : ProcResource<1>; // FP #0 45let Super = M3PipeF0 in { 46 def M3UnitFMAC0 : ProcResource<1>; // FP multiplication 47 def M3UnitFADD0 : ProcResource<1>; // Simple FP 48 def M3UnitFCVT0 : ProcResource<1>; // FP conversion 49 def M3UnitFSQR : ProcResource<2>; // FP square root (serialized) 50 def M3UnitNALU0 : ProcResource<1>; // Simple vector 51 def M3UnitNMSC : ProcResource<1>; // FP and vector miscellanea 52 def M3UnitNSHT0 : ProcResource<1>; // Vector shifting 53 def M3UnitNSHF0 : ProcResource<1>; // Vector shuffling 54} 55def M3PipeF1 : ProcResource<1>; // FP #1 56let Super = M3PipeF1 in { 57 def M3UnitFMAC1 : ProcResource<1>; // FP multiplication 58 def M3UnitFADD1 : ProcResource<1>; // Simple FP 59 def M3UnitFDIV0 : ProcResource<2>; // FP division (serialized) 60 def M3UnitFCVT1 : ProcResource<1>; // FP conversion 61 def M3UnitFST0 : ProcResource<1>; // FP store 62 def M3UnitNALU1 : ProcResource<1>; // Simple vector 63 def M3UnitNCRY0 : ProcResource<1>; // Cryptographic 64 def M3UnitNMUL : ProcResource<1>; // Vector multiplication 65 def M3UnitNSHT1 : ProcResource<1>; // Vector shifting 66 def M3UnitNSHF1 : ProcResource<1>; // Vector shuffling 67} 68def M3PipeF2 : ProcResource<1>; // FP #2 69let Super = M3PipeF2 in { 70 def M3UnitFMAC2 : ProcResource<1>; // FP multiplication 71 def M3UnitFADD2 : ProcResource<1>; // Simple FP 72 def M3UnitFDIV1 : ProcResource<2>; // FP division (serialized) 73 def M3UnitFST1 : ProcResource<1>; // FP store 74 def M3UnitNALU2 : ProcResource<1>; // Simple vector 75 def M3UnitNCRY1 : ProcResource<1>; // Cryptographic 76 def M3UnitNSHT2 : ProcResource<1>; // Vector shifting 77 def M3UnitNSHF2 : ProcResource<1>; // Vector shuffling 78} 79 80 81def M3UnitALU : ProcResGroup<[M3UnitA, 82 M3UnitC]>; 83def M3UnitFMAC : ProcResGroup<[M3UnitFMAC0, 84 M3UnitFMAC1, 85 M3UnitFMAC2]>; 86def M3UnitFADD : ProcResGroup<[M3UnitFADD0, 87 M3UnitFADD1, 88 M3UnitFADD2]>; 89def M3UnitFDIV : ProcResGroup<[M3UnitFDIV0, 90 M3UnitFDIV1]>; 91def M3UnitFCVT : ProcResGroup<[M3UnitFCVT0, 92 M3UnitFCVT1]>; 93def M3UnitFST : ProcResGroup<[M3UnitFST0, 94 M3UnitFST1]>; 95def M3UnitNALU : ProcResGroup<[M3UnitNALU0, 96 M3UnitNALU1, 97 M3UnitNALU2]>; 98def M3UnitNCRY : ProcResGroup<[M3UnitNCRY0, 99 M3UnitNCRY1]>; 100def M3UnitNSHT : ProcResGroup<[M3UnitNSHT0, 101 M3UnitNSHT1, 102 M3UnitNSHT2]>; 103def M3UnitNSHF : ProcResGroup<[M3UnitNSHF0, 104 M3UnitNSHF1, 105 M3UnitNSHF2]>; 106 107//===----------------------------------------------------------------------===// 108// Coarse scheduling model. 109 110def M3WriteZ0 : SchedWriteRes<[]> { let Latency = 0; 111 let NumMicroOps = 1; } 112def M3WriteZ1 : SchedWriteRes<[]> { let Latency = 1; 113 let NumMicroOps = 0; } 114 115def M3WriteA1 : SchedWriteRes<[M3UnitALU]> { let Latency = 1; } 116def M3WriteAA : SchedWriteRes<[M3UnitALU]> { let Latency = 2; 117 let ResourceCycles = [2]; } 118def M3WriteAB : SchedWriteRes<[M3UnitALU, 119 M3UnitC]> { let Latency = 1; 120 let NumMicroOps = 2; } 121def M3WriteAC : SchedWriteRes<[M3UnitALU, 122 M3UnitALU, 123 M3UnitC]> { let Latency = 2; 124 let NumMicroOps = 3; } 125def M3WriteAD : SchedWriteRes<[M3UnitALU, 126 M3UnitC]> { let Latency = 2; 127 let NumMicroOps = 2; } 128def M3WriteC1 : SchedWriteRes<[M3UnitC]> { let Latency = 1; } 129def M3WriteC2 : SchedWriteRes<[M3UnitC]> { let Latency = 2; } 130def M3WriteAU : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M3WriteZ0]>, 131 SchedVar<ExynosArithPred, [M3WriteA1]>, 132 SchedVar<ExynosLogicPred, [M3WriteA1]>, 133 SchedVar<NoSchedPred, [M3WriteAA]>]>; 134def M3WriteAV : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M3WriteZ0]>, 135 SchedVar<ExynosArithPred, [M3WriteA1]>, 136 SchedVar<NoSchedPred, [M3WriteAA]>]>; 137def M3WriteAW : SchedWriteVariant<[SchedVar<IsZeroIdiomPred, [M3WriteZ0]>, 138 SchedVar<ExynosLogicPred, [M3WriteA1]>, 139 SchedVar<NoSchedPred, [M3WriteAA]>]>; 140def M3WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred, [M3WriteA1]>, 141 SchedVar<ExynosLogicPred, [M3WriteA1]>, 142 SchedVar<NoSchedPred, [M3WriteAA]>]>; 143def M3WriteAY : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M3WriteA1]>, 144 SchedVar<NoSchedPred, [M3WriteAA]>]>; 145 146def M3WriteB1 : SchedWriteRes<[M3UnitB]> { let Latency = 1; } 147def M3WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M3WriteAC]>, 148 SchedVar<NoSchedPred, [M3WriteAB]>]>; 149 150def M3WriteL4 : SchedWriteRes<[M3UnitL]> { let Latency = 4; } 151def M3WriteL5 : SchedWriteRes<[M3UnitL]> { let Latency = 5; } 152def M3WriteLA : SchedWriteRes<[M3UnitL, 153 M3UnitL]> { let Latency = 5; 154 let NumMicroOps = 1; } 155def M3WriteLB : SchedWriteRes<[M3UnitA, 156 M3UnitL]> { let Latency = 5; 157 let NumMicroOps = 2; } 158def M3WriteLC : SchedWriteRes<[M3UnitA, 159 M3UnitL, 160 M3UnitL]> { let Latency = 5; 161 let NumMicroOps = 2; } 162def M3WriteLD : SchedWriteRes<[M3UnitA, 163 M3UnitL]> { let Latency = 4; 164 let NumMicroOps = 2; } 165def M3WriteLE : SchedWriteRes<[M3UnitA, 166 M3UnitL]> { let Latency = 6; 167 let NumMicroOps = 2; } 168def M3WriteLH : SchedWriteRes<[]> { let Latency = 5; 169 let NumMicroOps = 0; } 170def M3WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteL5]>, 171 SchedVar<NoSchedPred, [M3WriteL4]>]>; 172def M3WriteLY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteLE]>, 173 SchedVar<NoSchedPred, [M3WriteL5]>]>; 174 175def M3WriteS1 : SchedWriteRes<[M3UnitS]> { let Latency = 1; } 176def M3WriteSA : SchedWriteRes<[M3UnitA, 177 M3UnitS, 178 M3UnitFST]> { let Latency = 3; 179 let NumMicroOps = 2; } 180def M3WriteSB : SchedWriteRes<[M3UnitA, 181 M3UnitS]> { let Latency = 2; 182 let NumMicroOps = 2; } 183def M3WriteSC : SchedWriteRes<[M3UnitA, 184 M3UnitS, 185 M3UnitFST]> { let Latency = 1; 186 let NumMicroOps = 2; } 187def M3WriteSY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteSA]>, 188 SchedVar<NoSchedPred, [WriteVST]>]>; 189 190def M3ReadAdrBase : SchedReadVariant<[SchedVar<ExynosScaledIdxPred, [ReadDefault]>, 191 SchedVar<NoSchedPred, [ReadDefault]>]>; 192 193// Branch instructions. 194def : SchedAlias<WriteBr, M3WriteZ0>; 195def : SchedAlias<WriteBrReg, M3WriteC1>; 196 197// Arithmetic and logical integer instructions. 198def : SchedAlias<WriteI, M3WriteA1>; 199def : SchedAlias<WriteISReg, M3WriteA1>; 200def : SchedAlias<WriteIEReg, M3WriteA1>; 201def : SchedAlias<WriteIS, M3WriteA1>; 202 203// Move instructions. 204def : SchedAlias<WriteImm, M3WriteA1>; 205 206// Divide and multiply instructions. 207def : WriteRes<WriteID32, [M3UnitC, 208 M3UnitD]> { let Latency = 12; 209 let ResourceCycles = [1, 12]; } 210def : WriteRes<WriteID64, [M3UnitC, 211 M3UnitD]> { let Latency = 21; 212 let ResourceCycles = [1, 21]; } 213def : WriteRes<WriteIM32, [M3UnitC]> { let Latency = 3; } 214def : WriteRes<WriteIM64, [M3UnitC]> { let Latency = 4; 215 let ResourceCycles = [2]; } 216 217// Miscellaneous instructions. 218def : SchedAlias<WriteExtr, M3WriteAY>; 219 220// Addressing modes. 221def : SchedAlias<WriteAdr, M3WriteZ1>; 222def : SchedAlias<ReadAdrBase, M3ReadAdrBase>; 223 224// Load instructions. 225def : SchedAlias<WriteLD, M3WriteL4>; 226def : WriteRes<WriteLDHi, []> { let Latency = 4; 227 let NumMicroOps = 0; } 228def : SchedAlias<WriteLDIdx, M3WriteLB>; 229 230// Store instructions. 231def : SchedAlias<WriteST, M3WriteS1>; 232def : SchedAlias<WriteSTP, M3WriteS1>; 233def : SchedAlias<WriteSTX, M3WriteS1>; 234def : SchedAlias<WriteSTIdx, M3WriteSB>; 235 236// FP data instructions. 237def : WriteRes<WriteF, [M3UnitFADD]> { let Latency = 2; } 238def : WriteRes<WriteFCmp, [M3UnitNMSC]> { let Latency = 2; } 239def : WriteRes<WriteFDiv, [M3UnitFDIV]> { let Latency = 12; 240 let ResourceCycles = [12]; } 241def : WriteRes<WriteFMul, [M3UnitFMAC]> { let Latency = 4; } 242 243// FP miscellaneous instructions. 244def : WriteRes<WriteFCvt, [M3UnitFCVT]> { let Latency = 3; } 245def : WriteRes<WriteFImm, [M3UnitNALU]> { let Latency = 1; } 246def : WriteRes<WriteFCopy, [M3UnitNALU]> { let Latency = 1; } 247 248// FP load instructions. 249def : SchedAlias<WriteVLD, M3WriteL5>; 250 251// FP store instructions. 252def : WriteRes<WriteVST, [M3UnitS, 253 M3UnitFST]> { let Latency = 1; 254 let NumMicroOps = 1; } 255 256// ASIMD FP instructions. 257def : WriteRes<WriteVd, [M3UnitNALU]> { let Latency = 3; } 258def : WriteRes<WriteVq, [M3UnitNALU]> { let Latency = 3; } 259 260// Other miscellaneous instructions. 261def : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 262def : WriteRes<WriteBarrier, []> { let Latency = 1; } 263def : WriteRes<WriteHint, []> { let Latency = 1; } 264def : WriteRes<WriteSys, []> { let Latency = 1; } 265 266//===----------------------------------------------------------------------===// 267// Generic fast forwarding. 268 269// TODO: Add FP register forwarding rules. 270 271def : ReadAdvance<ReadI, 0>; 272def : ReadAdvance<ReadISReg, 0>; 273def : ReadAdvance<ReadIEReg, 0>; 274def : ReadAdvance<ReadIM, 0>; 275// TODO: The forwarding for 32 bits actually saves 2 cycles. 276def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>; 277def : ReadAdvance<ReadID, 0>; 278def : ReadAdvance<ReadExtrHi, 0>; 279def : ReadAdvance<ReadAdrBase, 0>; 280def : ReadAdvance<ReadVLD, 0>; 281def : ReadAdvance<ReadST, 0>; 282 283//===----------------------------------------------------------------------===// 284// Finer scheduling model. 285 286def M3WriteNEONA : SchedWriteRes<[M3UnitNSHF, 287 M3UnitFADD]> { let Latency = 3; 288 let NumMicroOps = 2; } 289def M3WriteNEONB : SchedWriteRes<[M3UnitNALU, 290 M3UnitFST]> { let Latency = 10; 291 let NumMicroOps = 2; } 292def M3WriteNEOND : SchedWriteRes<[M3UnitNSHF, 293 M3UnitFST]> { let Latency = 6; 294 let NumMicroOps = 2; } 295def M3WriteNEONH : SchedWriteRes<[M3UnitNALU, 296 M3UnitS]> { let Latency = 5; 297 let NumMicroOps = 2; } 298def M3WriteNEONI : SchedWriteRes<[M3UnitNSHF, 299 M3UnitS]> { let Latency = 5; 300 let NumMicroOps = 2; } 301def M3WriteNEONV : SchedWriteRes<[M3UnitFDIV0, 302 M3UnitFDIV1]> { let Latency = 7; 303 let NumMicroOps = 2; 304 let ResourceCycles = [8, 8]; } 305def M3WriteNEONW : SchedWriteRes<[M3UnitFDIV0, 306 M3UnitFDIV1]> { let Latency = 12; 307 let NumMicroOps = 2; 308 let ResourceCycles = [13, 13]; } 309def M3WriteNEONX : SchedWriteRes<[M3UnitFSQR, 310 M3UnitFSQR]> { let Latency = 18; 311 let NumMicroOps = 2; 312 let ResourceCycles = [19, 19]; } 313def M3WriteNEONY : SchedWriteRes<[M3UnitFSQR, 314 M3UnitFSQR]> { let Latency = 25; 315 let NumMicroOps = 2; 316 let ResourceCycles = [26, 26]; } 317def M3WriteNEONZ : SchedWriteRes<[M3UnitNMSC, 318 M3UnitNMSC]> { let Latency = 5; 319 let NumMicroOps = 2; } 320def M3WriteFADD2 : SchedWriteRes<[M3UnitFADD]> { let Latency = 2; } 321def M3WriteFCVT2 : SchedWriteRes<[M3UnitFCVT]> { let Latency = 2; } 322def M3WriteFCVT3 : SchedWriteRes<[M3UnitFCVT]> { let Latency = 3; } 323def M3WriteFCVT3A : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 3; } 324def M3WriteFCVT4A : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 4; } 325def M3WriteFCVT4 : SchedWriteRes<[M3UnitFCVT]> { let Latency = 4; } 326def M3WriteFDIV10 : SchedWriteRes<[M3UnitFDIV]> { let Latency = 7; 327 let ResourceCycles = [8]; } 328def M3WriteFDIV12 : SchedWriteRes<[M3UnitFDIV]> { let Latency = 12; 329 let ResourceCycles = [13]; } 330def M3WriteFMAC3 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 3; } 331def M3WriteFMAC4 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 4; } 332def M3WriteFMAC5 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 5; } 333def M3WriteFSQR17 : SchedWriteRes<[M3UnitFSQR]> { let Latency = 18; 334 let ResourceCycles = [19]; } 335def M3WriteFSQR25 : SchedWriteRes<[M3UnitFSQR]> { let Latency = 25; 336 let ResourceCycles = [26]; } 337def M3WriteNALU1 : SchedWriteRes<[M3UnitNALU]> { let Latency = 1; } 338def M3WriteNCRY1A : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 1; } 339def M3WriteNCRY3A : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 3; } 340def M3WriteNCRY5A : SchedWriteRes<[M3UnitNCRY]> { let Latency = 5; } 341def M3WriteNMSC1 : SchedWriteRes<[M3UnitNMSC]> { let Latency = 1; } 342def M3WriteNMSC2 : SchedWriteRes<[M3UnitNMSC]> { let Latency = 2; } 343def M3WriteNMSC3 : SchedWriteRes<[M3UnitNMSC]> { let Latency = 3; } 344def M3WriteNMUL3 : SchedWriteRes<[M3UnitNMUL]> { let Latency = 3; } 345def M3WriteNSHF1 : SchedWriteRes<[M3UnitNSHF]> { let Latency = 1; } 346def M3WriteNSHF3 : SchedWriteRes<[M3UnitNSHF]> { let Latency = 3; } 347def M3WriteNSHT1 : SchedWriteRes<[M3UnitNSHT]> { let Latency = 1; } 348def M3WriteNSHT2 : SchedWriteRes<[M3UnitNSHT]> { let Latency = 2; } 349def M3WriteNSHT3 : SchedWriteRes<[M3UnitNSHT]> { let Latency = 3; } 350def M3WriteVLDA : SchedWriteRes<[M3UnitL, 351 M3UnitL]> { let Latency = 5; 352 let NumMicroOps = 2; } 353def M3WriteVLDB : SchedWriteRes<[M3UnitL, 354 M3UnitL, 355 M3UnitL]> { let Latency = 6; 356 let NumMicroOps = 3; } 357def M3WriteVLDC : SchedWriteRes<[M3UnitL, 358 M3UnitL, 359 M3UnitL, 360 M3UnitL]> { let Latency = 6; 361 let NumMicroOps = 4; } 362def M3WriteVLDD : SchedWriteRes<[M3UnitL, 363 M3UnitNALU]> { let Latency = 7; 364 let NumMicroOps = 2; 365 let ResourceCycles = [2, 1]; } 366def M3WriteVLDE : SchedWriteRes<[M3UnitL, 367 M3UnitNALU]> { let Latency = 6; 368 let NumMicroOps = 2; 369 let ResourceCycles = [2, 1]; } 370def M3WriteVLDF : SchedWriteRes<[M3UnitL, 371 M3UnitL]> { let Latency = 10; 372 let NumMicroOps = 2; 373 let ResourceCycles = [5, 5]; } 374def M3WriteVLDG : SchedWriteRes<[M3UnitL, 375 M3UnitNALU, 376 M3UnitNALU]> { let Latency = 7; 377 let NumMicroOps = 3; 378 let ResourceCycles = [2, 1, 1]; } 379def M3WriteVLDH : SchedWriteRes<[M3UnitL, 380 M3UnitNALU, 381 M3UnitNALU]> { let Latency = 6; 382 let NumMicroOps = 3; 383 let ResourceCycles = [2, 1, 1]; } 384def M3WriteVLDI : SchedWriteRes<[M3UnitL, 385 M3UnitL, 386 M3UnitL]> { let Latency = 12; 387 let NumMicroOps = 3; 388 let ResourceCycles = [6, 6, 6]; } 389def M3WriteVLDJ : SchedWriteRes<[M3UnitL, 390 M3UnitNALU, 391 M3UnitNALU, 392 M3UnitNALU]> { let Latency = 7; 393 let NumMicroOps = 4; 394 let ResourceCycles = [2, 1, 1, 1]; } 395def M3WriteVLDK : SchedWriteRes<[M3UnitL, 396 M3UnitNALU, 397 M3UnitNALU, 398 M3UnitNALU, 399 M3UnitNALU]> { let Latency = 9; 400 let NumMicroOps = 5; 401 let ResourceCycles = [4, 1, 1, 1, 1]; } 402def M3WriteVLDL : SchedWriteRes<[M3UnitL, 403 M3UnitNALU, 404 M3UnitNALU, 405 M3UnitL, 406 M3UnitNALU]> { let Latency = 6; 407 let NumMicroOps = 5; 408 let ResourceCycles = [6, 1, 1, 6, 1]; } 409def M3WriteVLDM : SchedWriteRes<[M3UnitL, 410 M3UnitNALU, 411 M3UnitNALU, 412 M3UnitL, 413 M3UnitNALU, 414 M3UnitNALU]> { let Latency = 7; 415 let NumMicroOps = 6; 416 let ResourceCycles = [6, 1, 1, 6, 1, 1]; } 417def M3WriteVLDN : SchedWriteRes<[M3UnitL, 418 M3UnitL, 419 M3UnitL, 420 M3UnitL]> { let Latency = 14; 421 let NumMicroOps = 4; 422 let ResourceCycles = [6, 6, 6, 6]; } 423def M3WriteVSTA : WriteSequence<[WriteVST], 2>; 424def M3WriteVSTB : WriteSequence<[WriteVST], 3>; 425def M3WriteVSTC : WriteSequence<[WriteVST], 4>; 426def M3WriteVSTD : SchedWriteRes<[M3UnitS, 427 M3UnitFST, 428 M3UnitS, 429 M3UnitFST]> { let Latency = 7; 430 let NumMicroOps = 4; 431 let ResourceCycles = [1, 3, 1, 3]; } 432def M3WriteVSTE : SchedWriteRes<[M3UnitS, 433 M3UnitFST, 434 M3UnitS, 435 M3UnitFST, 436 M3UnitS, 437 M3UnitFST]> { let Latency = 8; 438 let NumMicroOps = 6; 439 let ResourceCycles = [1, 3, 1, 3, 1, 3]; } 440def M3WriteVSTF : SchedWriteRes<[M3UnitNALU, 441 M3UnitFST, 442 M3UnitFST, 443 M3UnitS, 444 M3UnitFST, 445 M3UnitS, 446 M3UnitFST]> { let Latency = 15; 447 let NumMicroOps = 7; 448 let ResourceCycles = [1, 3, 3, 1, 3, 1, 3]; } 449def M3WriteVSTG : SchedWriteRes<[M3UnitNALU, 450 M3UnitFST, 451 M3UnitFST, 452 M3UnitS, 453 M3UnitFST, 454 M3UnitS, 455 M3UnitFST, 456 M3UnitS, 457 M3UnitFST]> { let Latency = 16; 458 let NumMicroOps = 9; 459 let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; } 460def M3WriteVSTH : SchedWriteRes<[M3UnitNALU, 461 M3UnitFST, 462 M3UnitFST, 463 M3UnitS, 464 M3UnitFST]> { let Latency = 14; 465 let NumMicroOps = 5; 466 let ResourceCycles = [1, 3, 3, 1, 3]; } 467def M3WriteVSTI : SchedWriteRes<[M3UnitNALU, 468 M3UnitFST, 469 M3UnitFST, 470 M3UnitS, 471 M3UnitFST, 472 M3UnitS, 473 M3UnitFST, 474 M3UnitS, 475 M3UnitFST]> { let Latency = 17; 476 let NumMicroOps = 9; 477 let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; } 478 479// Special cases. 480def M3WriteAES : SchedWriteRes<[M3UnitNCRY]> { let Latency = 1; } 481def M3WriteCOPY : SchedWriteVariant<[SchedVar<ExynosFPPred, [M3WriteNALU1]>, 482 SchedVar<NoSchedPred, [M3WriteZ0]>]>; 483def M3WriteMOVI : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M3WriteZ0]>, 484 SchedVar<NoSchedPred, [M3WriteNALU1]>]>; 485 486// Fast forwarding. 487def M3ReadAES : SchedReadAdvance<1, [M3WriteAES]>; 488def M3ReadFMAC : SchedReadAdvance<1, [M3WriteFMAC4, 489 M3WriteFMAC5]>; 490def M3ReadNMUL : SchedReadAdvance<1, [M3WriteNMUL3]>; 491 492// Branch instructions 493def : InstRW<[M3WriteB1], (instrs Bcc)>; 494def : InstRW<[M3WriteA1], (instrs BL)>; 495def : InstRW<[M3WriteBX], (instrs BLR)>; 496def : InstRW<[M3WriteC1], (instregex "^CBN?Z[WX]")>; 497def : InstRW<[M3WriteAD], (instregex "^TBN?Z[WX]")>; 498 499// Arithmetic and logical integer instructions. 500def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>; 501def : InstRW<[M3WriteAU], (instrs ORRWrs, ORRXrs)>; 502def : InstRW<[M3WriteAX], (instregex "^(ADD|SUB)S?[WX]rx(64)?$")>; 503def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|SUB)S[WX]rs$")>; 504def : InstRW<[M3WriteAV], (instrs ADDWri, ADDXri)>; 505def : InstRW<[M3WriteAW], (instrs ORRWri, ORRXri)>; 506 507// Move instructions. 508def : InstRW<[M3WriteCOPY], (instrs COPY)>; 509def : InstRW<[M3WriteZ0], (instrs ADR, ADRP)>; 510def : InstRW<[M3WriteZ0], (instregex "^MOV[NZ][WX]i")>; 511 512// Divide and multiply instructions. 513 514// Miscellaneous instructions. 515 516// Load instructions. 517def : InstRW<[M3WriteLD, 518 WriteLDHi, 519 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>; 520def : InstRW<[M3WriteLB, 521 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>; 522def : InstRW<[M3WriteLX, 523 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>; 524def : InstRW<[M3WriteLB, 525 ReadAdrBase], (instrs PRFMroW)>; 526def : InstRW<[M3WriteLX, 527 ReadAdrBase], (instrs PRFMroX)>; 528 529// Store instructions. 530def : InstRW<[M3WriteSB, 531 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>; 532def : InstRW<[WriteST, 533 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>; 534 535// FP data instructions. 536def : InstRW<[M3WriteNSHF1], (instregex "^FABS[DS]r")>; 537def : InstRW<[M3WriteFADD2], (instregex "^F(ADD|SUB)[DS]rr")>; 538def : InstRW<[M3WriteFDIV10], (instrs FDIVSrr)>; 539def : InstRW<[M3WriteFDIV12], (instrs FDIVDrr)>; 540def : InstRW<[M3WriteNMSC1], (instregex "^F(MAX|MIN).+rr")>; 541def : InstRW<[M3WriteFMAC3], (instregex "^FN?MUL[DS]rr")>; 542def : InstRW<[M3WriteFMAC4, 543 M3ReadFMAC], (instregex "^FN?M(ADD|SUB)[DS]rrr")>; 544def : InstRW<[M3WriteNALU1], (instregex "^FNEG[DS]r")>; 545def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT.+r")>; 546def : InstRW<[M3WriteNEONH], (instregex "^FCSEL[DS]rrr")>; 547def : InstRW<[M3WriteFSQR17], (instrs FSQRTSr)>; 548def : InstRW<[M3WriteFSQR25], (instrs FSQRTDr)>; 549 550// FP miscellaneous instructions. 551def : InstRW<[M3WriteFCVT3], (instregex "^FCVT[DHS][DHS]r")>; 552def : InstRW<[M3WriteFCVT4A], (instregex "^[SU]CVTF[SU][XW][DHS]ri")>; 553def : InstRW<[M3WriteFCVT3A], (instregex "^FCVT[AMNPZ][SU]U[XW][DHS]r")>; 554def : InstRW<[M3WriteFCVT3A], (instregex "^FCVTZ[SU][dhs]")>; 555def : InstRW<[M3WriteNALU1], (instregex "^FMOV[DS][ir]")>; 556def : InstRW<[M3WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev1")>; 557def : InstRW<[M3WriteNMSC1], (instregex "^FRECPXv1")>; 558def : InstRW<[M3WriteFMAC4, 559 M3ReadFMAC], (instregex "^F(RECP|RSQRT)S(16|32|64)")>; 560def : InstRW<[M3WriteNALU1], (instregex "^FMOV[WX][DS]r")>; 561def : InstRW<[M3WriteNALU1], (instregex "^FMOV[DS][WX]r")>; 562def : InstRW<[M3WriteNEONI], (instregex "^FMOV(DX|XD)Highr")>; 563 564// FP load instructions. 565def : InstRW<[WriteVLD], (instregex "^LDR[DSQ]l")>; 566def : InstRW<[WriteVLD], (instregex "^LDUR[BDHSQ]i")>; 567def : InstRW<[WriteVLD, 568 WriteAdr], (instregex "^LDR[BDHSQ](post|pre)")>; 569def : InstRW<[WriteVLD], (instregex "^LDR[BDHSQ]ui")>; 570def : InstRW<[M3WriteLE, 571 ReadAdrBase], (instregex "^LDR[BDHS]roW")>; 572def : InstRW<[WriteVLD, 573 ReadAdrBase], (instregex "^LDR[BDHS]roX")>; 574def : InstRW<[M3WriteLY, 575 ReadAdrBase], (instregex "^LDRQro[WX]")>; 576def : InstRW<[WriteVLD, 577 M3WriteLH], (instregex "^LDN?P[DS]i")>; 578def : InstRW<[M3WriteLA, 579 M3WriteLH], (instregex "^LDN?PQi")>; 580def : InstRW<[M3WriteLB, 581 M3WriteLH, 582 WriteAdr], (instregex "^LDP[DS](post|pre)")>; 583def : InstRW<[M3WriteLC, 584 M3WriteLH, 585 WriteAdr], (instregex "^LDPQ(post|pre)")>; 586 587// FP store instructions. 588def : InstRW<[WriteVST], (instregex "^STUR[BDHSQ]i")>; 589def : InstRW<[WriteVST, 590 WriteAdr], (instregex "^STR[BDHSQ](post|pre)")>; 591def : InstRW<[WriteVST], (instregex "^STR[BDHSQ]ui")>; 592def : InstRW<[M3WriteSA, 593 ReadAdrBase], (instregex "^STR[BDHS]roW")>; 594def : InstRW<[M3WriteSA, 595 ReadAdrBase], (instregex "^STRQroW")>; 596def : InstRW<[WriteVST, 597 ReadAdrBase], (instregex "^STR[BDHS]roX")>; 598def : InstRW<[M3WriteSY, 599 ReadAdrBase], (instregex "^STRQroX")>; 600def : InstRW<[WriteVST], (instregex "^STN?P[DSQ]i")>; 601def : InstRW<[WriteVST, 602 WriteAdr], (instregex "^STP[DS](post|pre)")>; 603def : InstRW<[M3WriteSC, 604 WriteAdr], (instregex "^STPQ(post|pre)")>; 605 606// ASIMD instructions. 607def : InstRW<[M3WriteNMSC3], (instregex "^[SU]ABAL?v")>; 608def : InstRW<[M3WriteNMSC1], (instregex "^[SU]ABDL?v")>; 609def : InstRW<[M3WriteNMSC1], (instregex "^((SQ)?ABS|SQNEG)v")>; 610def : InstRW<[M3WriteNALU1], (instregex "^(ADD|NEG|SUB)v")>; 611def : InstRW<[M3WriteNMSC3], (instregex "^[SU]?ADDL?Pv")>; 612def : InstRW<[M3WriteNMSC3], (instregex "^[SU]H(ADD|SUB)v")>; 613def : InstRW<[M3WriteNMSC3], (instregex "^[SU](ADD|SUB)[LW]V?v")>; 614def : InstRW<[M3WriteNMSC3], (instregex "^R?(ADD|SUB)HN2?v")>; 615def : InstRW<[M3WriteNMSC3], (instregex "^[SU]Q(ADD|SUB)v")>; 616def : InstRW<[M3WriteNMSC3], (instregex "^(SU|US)QADDv")>; 617def : InstRW<[M3WriteNMSC3], (instregex "^[SU]RHADDv")>; 618def : InstRW<[M3WriteNMSC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>; 619def : InstRW<[M3WriteNALU1], (instregex "^CMTSTv")>; 620def : InstRW<[M3WriteNALU1], (instregex "^(AND|BIC|EOR|MVNI|NOT|ORN|ORR)v")>; 621def : InstRW<[M3WriteNMSC1], (instregex "^[SU](MIN|MAX)v")>; 622def : InstRW<[M3WriteNMSC2], (instregex "^[SU](MIN|MAX)Pv")>; 623def : InstRW<[M3WriteNMSC3], (instregex "^[SU](MIN|MAX)Vv")>; 624def : InstRW<[M3WriteNMUL3], (instregex "^(MUL|SQR?DMULH)v")>; 625def : InstRW<[M3WriteNMUL3, 626 M3ReadNMUL], (instregex "^ML[AS]v")>; 627def : InstRW<[M3WriteNMUL3], (instregex "^[SU]ML[AS]Lv")>; 628def : InstRW<[M3WriteNMUL3], (instregex "^SQDML[AS]L")>; 629def : InstRW<[M3WriteNMUL3], (instregex "^(S|U|SQD)MULLv")>; 630def : InstRW<[M3WriteNMSC3], (instregex "^[SU]ADALPv")>; 631def : InstRW<[M3WriteNSHT3], (instregex "^[SU]R?SRAv")>; 632def : InstRW<[M3WriteNSHT1], (instregex "^SHL[dv]")>; 633def : InstRW<[M3WriteNSHT1], (instregex "^[SU]SH[LR][dv]")>; 634def : InstRW<[M3WriteNSHT1], (instregex "^S[RS]I[dv]")>; 635def : InstRW<[M3WriteNSHT2], (instregex "^[SU]?SHLLv")>; 636def : InstRW<[M3WriteNSHT3], (instregex "^(([SU]Q)?R)?SHRU?N[bhsv]")>; 637def : InstRW<[M3WriteNSHT3], (instregex "^[SU]RSH[LR][dv]")>; 638def : InstRW<[M3WriteNSHT3], (instregex "^[SU]QR?SHLU?[bdhsv]")>; 639 640// ASIMD FP instructions. 641def : InstRW<[M3WriteNSHF1], (instregex "^FABSv")>; 642def : InstRW<[M3WriteFADD2], (instregex "^F(ABD|ADD|SUB)v")>; 643def : InstRW<[M3WriteNEONA], (instregex "^FADDP")>; 644def : InstRW<[M3WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>; 645def : InstRW<[M3WriteFCVT3], (instregex "^FCVT(L|N|XN)v")>; 646def : InstRW<[M3WriteFCVT2], (instregex "^FCVT[AMNPZ][SU]v")>; 647def : InstRW<[M3WriteFCVT2], (instregex "^[SU]CVTFv")>; 648def : InstRW<[M3WriteFDIV10], (instrs FDIVv2f32)>; 649def : InstRW<[M3WriteNEONV], (instrs FDIVv4f32)>; 650def : InstRW<[M3WriteNEONW], (instrs FDIVv2f64)>; 651def : InstRW<[M3WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?v")>; 652def : InstRW<[M3WriteNMSC2], (instregex "^F(MAX|MIN)(NM)?Pv")>; 653def : InstRW<[M3WriteNEONZ], (instregex "^F(MAX|MIN)(NM)?Vv")>; 654def : InstRW<[M3WriteFMAC3], (instregex "^FMULX?v.[fi]")>; 655def : InstRW<[M3WriteFMAC4, 656 M3ReadFMAC], (instregex "^FML[AS]v.f")>; 657def : InstRW<[M3WriteFMAC5, 658 M3ReadFMAC], (instregex "^FML[AS]v.i")>; 659def : InstRW<[M3WriteNALU1], (instregex "^FNEGv")>; 660def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>; 661def : InstRW<[M3WriteFSQR17], (instrs FSQRTv2f32)>; 662def : InstRW<[M3WriteNEONX], (instrs FSQRTv4f32)>; 663def : InstRW<[M3WriteNEONY], (instrs FSQRTv2f64)>; 664 665// ASIMD miscellaneous instructions. 666def : InstRW<[M3WriteNALU1], (instregex "^RBITv")>; 667def : InstRW<[M3WriteNALU1], (instregex "^(BIF|BIT|BSL|BSP)v")>; 668def : InstRW<[M3WriteNEONB], (instregex "^DUPv.+gpr")>; 669def : InstRW<[M3WriteNSHF1], (instregex "^DUPv.+lane")>; 670def : InstRW<[M3WriteNSHF1], (instregex "^EXTv")>; 671def : InstRW<[M3WriteNSHF1], (instregex "^[SU]?Q?XTU?Nv")>; 672def : InstRW<[M3WriteNSHF1], (instregex "^CPY")>; 673def : InstRW<[M3WriteNSHF1], (instregex "^INSv.+lane")>; 674def : InstRW<[M3WriteMOVI], (instregex "^MOVI")>; 675def : InstRW<[M3WriteNALU1], (instregex "^FMOVv")>; 676def : InstRW<[M3WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev[248]")>; 677def : InstRW<[M3WriteFMAC4, 678 M3ReadFMAC], (instregex "^F(RECP|RSQRT)Sv")>; 679def : InstRW<[M3WriteNSHF1], (instregex "^REV(16|32|64)v")>; 680def : InstRW<[M3WriteNSHF1], (instregex "^TB[LX]v")>; 681def : InstRW<[M3WriteNEOND], (instregex "^[SU]MOVv")>; 682def : InstRW<[M3WriteNSHF3], (instregex "^INSv.+gpr")>; 683def : InstRW<[M3WriteNSHF1], (instregex "^(TRN|UZP|ZIP)[12]v")>; 684 685// ASIMD load instructions. 686def : InstRW<[M3WriteL5], (instregex "LD1Onev(8b|4h|2s|1d)$")>; 687def : InstRW<[M3WriteL5, 688 M3WriteA1], (instregex "LD1Onev(8b|4h|2s|1d)_POST")>; 689def : InstRW<[M3WriteL5], (instregex "LD1Onev(16b|8h|4s|2d)$")>; 690def : InstRW<[M3WriteL5, 691 M3WriteA1], (instregex "LD1Onev(16b|8h|4s|2d)_POST")>; 692 693def : InstRW<[M3WriteVLDA], (instregex "LD1Twov(8b|4h|2s|1d)$")>; 694def : InstRW<[M3WriteVLDA, 695 M3WriteA1], (instregex "LD1Twov(8b|4h|2s|1d)_POST")>; 696def : InstRW<[M3WriteVLDA], (instregex "LD1Twov(16b|8h|4s|2d)$")>; 697def : InstRW<[M3WriteVLDA, 698 M3WriteA1], (instregex "LD1Twov(16b|8h|4s|2d)_POST")>; 699 700def : InstRW<[M3WriteVLDB], (instregex "LD1Threev(8b|4h|2s|1d)$")>; 701def : InstRW<[M3WriteVLDB, 702 M3WriteA1], (instregex "LD1Threev(8b|4h|2s|1d)_POST")>; 703def : InstRW<[M3WriteVLDB], (instregex "LD1Threev(16b|8h|4s|2d)$")>; 704def : InstRW<[M3WriteVLDB, 705 M3WriteA1], (instregex "LD1Threev(16b|8h|4s|2d)_POST")>; 706 707def : InstRW<[M3WriteVLDC], (instregex "LD1Fourv(8b|4h|2s|1d)$")>; 708def : InstRW<[M3WriteVLDC, 709 M3WriteA1], (instregex "LD1Fourv(8b|4h|2s|1d)_POST")>; 710def : InstRW<[M3WriteVLDC], (instregex "LD1Fourv(16b|8h|4s|2d)$")>; 711def : InstRW<[M3WriteVLDC, 712 M3WriteA1], (instregex "LD1Fourv(16b|8h|4s|2d)_POST")>; 713 714def : InstRW<[M3WriteVLDD], (instregex "LD1i(8|16|32)$")>; 715def : InstRW<[M3WriteVLDD, 716 M3WriteA1], (instregex "LD1i(8|16|32)_POST")>; 717def : InstRW<[M3WriteVLDE], (instregex "LD1i(64)$")>; 718def : InstRW<[M3WriteVLDE, 719 M3WriteA1], (instregex "LD1i(64)_POST")>; 720 721def : InstRW<[M3WriteL5], (instregex "LD1Rv(8b|4h|2s|1d)$")>; 722def : InstRW<[M3WriteL5, 723 M3WriteA1], (instregex "LD1Rv(8b|4h|2s|1d)_POST")>; 724def : InstRW<[M3WriteL5], (instregex "LD1Rv(16b|8h|4s|2d)$")>; 725def : InstRW<[M3WriteL5, 726 M3WriteA1], (instregex "LD1Rv(16b|8h|4s|2d)_POST")>; 727 728def : InstRW<[M3WriteVLDF], (instregex "LD2Twov(8b|4h|2s)$")>; 729def : InstRW<[M3WriteVLDF, 730 M3WriteA1], (instregex "LD2Twov(8b|4h|2s)_POST")>; 731def : InstRW<[M3WriteVLDF], (instregex "LD2Twov(16b|8h|4s|2d)$")>; 732def : InstRW<[M3WriteVLDF, 733 M3WriteA1], (instregex "LD2Twov(16b|8h|4s|2d)_POST")>; 734 735def : InstRW<[M3WriteVLDG], (instregex "LD2i(8|16|32)$")>; 736def : InstRW<[M3WriteVLDG, 737 M3WriteA1], (instregex "LD2i(8|16|32)_POST")>; 738def : InstRW<[M3WriteVLDH], (instregex "LD2i(64)$")>; 739def : InstRW<[M3WriteVLDH, 740 M3WriteA1], (instregex "LD2i(64)_POST")>; 741 742def : InstRW<[M3WriteVLDA], (instregex "LD2Rv(8b|4h|2s|1d)$")>; 743def : InstRW<[M3WriteVLDA, 744 M3WriteA1], (instregex "LD2Rv(8b|4h|2s|1d)_POST")>; 745def : InstRW<[M3WriteVLDA], (instregex "LD2Rv(16b|8h|4s|2d)$")>; 746def : InstRW<[M3WriteVLDA, 747 M3WriteA1], (instregex "LD2Rv(16b|8h|4s|2d)_POST")>; 748 749def : InstRW<[M3WriteVLDI], (instregex "LD3Threev(8b|4h|2s)$")>; 750def : InstRW<[M3WriteVLDI, 751 M3WriteA1], (instregex "LD3Threev(8b|4h|2s)_POST")>; 752def : InstRW<[M3WriteVLDI], (instregex "LD3Threev(16b|8h|4s|2d)$")>; 753def : InstRW<[M3WriteVLDI, 754 M3WriteA1], (instregex "LD3Threev(16b|8h|4s|2d)_POST")>; 755 756def : InstRW<[M3WriteVLDJ], (instregex "LD3i(8|16|32)$")>; 757def : InstRW<[M3WriteVLDJ, 758 M3WriteA1], (instregex "LD3i(8|16|32)_POST")>; 759def : InstRW<[M3WriteVLDL], (instregex "LD3i(64)$")>; 760def : InstRW<[M3WriteVLDL, 761 M3WriteA1], (instregex "LD3i(64)_POST")>; 762 763def : InstRW<[M3WriteVLDB], (instregex "LD3Rv(8b|4h|2s|1d)$")>; 764def : InstRW<[M3WriteVLDB, 765 M3WriteA1], (instregex "LD3Rv(8b|4h|2s|1d)_POST")>; 766def : InstRW<[M3WriteVLDB], (instregex "LD3Rv(16b|8h|4s|2d)$")>; 767def : InstRW<[M3WriteVLDB, 768 M3WriteA1], (instregex "LD3Rv(16b|8h|4s|2d)_POST")>; 769 770def : InstRW<[M3WriteVLDN], (instregex "LD4Fourv(8b|4h|2s)$")>; 771def : InstRW<[M3WriteVLDN, 772 M3WriteA1], (instregex "LD4Fourv(8b|4h|2s)_POST")>; 773def : InstRW<[M3WriteVLDN], (instregex "LD4Fourv(16b|8h|4s|2d)$")>; 774def : InstRW<[M3WriteVLDN, 775 M3WriteA1], (instregex "LD4Fourv(16b|8h|4s|2d)_POST")>; 776 777def : InstRW<[M3WriteVLDK], (instregex "LD4i(8|16|32)$")>; 778def : InstRW<[M3WriteVLDK, 779 M3WriteA1], (instregex "LD4i(8|16|32)_POST")>; 780def : InstRW<[M3WriteVLDM], (instregex "LD4i(64)$")>; 781def : InstRW<[M3WriteVLDM, 782 M3WriteA1], (instregex "LD4i(64)_POST")>; 783 784def : InstRW<[M3WriteVLDC], (instregex "LD4Rv(8b|4h|2s|1d)$")>; 785def : InstRW<[M3WriteVLDC, 786 M3WriteA1], (instregex "LD4Rv(8b|4h|2s|1d)_POST")>; 787def : InstRW<[M3WriteVLDC], (instregex "LD4Rv(16b|8h|4s|2d)$")>; 788def : InstRW<[M3WriteVLDC, 789 M3WriteA1], (instregex "LD4Rv(16b|8h|4s|2d)_POST")>; 790 791// ASIMD store instructions. 792def : InstRW<[WriteVST], (instregex "ST1Onev(8b|4h|2s|1d)$")>; 793def : InstRW<[WriteVST, 794 WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d)_POST")>; 795def : InstRW<[WriteVST], (instregex "ST1Onev(16b|8h|4s|2d)$")>; 796def : InstRW<[WriteVST, 797 WriteAdr], (instregex "ST1Onev(16b|8h|4s|2d)_POST")>; 798 799def : InstRW<[M3WriteVSTA], (instregex "ST1Twov(8b|4h|2s|1d)$")>; 800def : InstRW<[M3WriteVSTA, 801 WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d)_POST")>; 802def : InstRW<[M3WriteVSTA], (instregex "ST1Twov(16b|8h|4s|2d)$")>; 803def : InstRW<[M3WriteVSTA, 804 WriteAdr], (instregex "ST1Twov(16b|8h|4s|2d)_POST")>; 805 806def : InstRW<[M3WriteVSTB], (instregex "ST1Threev(8b|4h|2s|1d)$")>; 807def : InstRW<[M3WriteVSTB, 808 WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d)_POST")>; 809def : InstRW<[M3WriteVSTB], (instregex "ST1Threev(16b|8h|4s|2d)$")>; 810def : InstRW<[M3WriteVSTB, 811 WriteAdr], (instregex "ST1Threev(16b|8h|4s|2d)_POST")>; 812 813def : InstRW<[M3WriteVSTC], (instregex "ST1Fourv(8b|4h|2s|1d)$")>; 814def : InstRW<[M3WriteVSTC, 815 WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d)_POST")>; 816def : InstRW<[M3WriteVSTC], (instregex "ST1Fourv(16b|8h|4s|2d)$")>; 817def : InstRW<[M3WriteVSTC, 818 WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST")>; 819 820def : InstRW<[M3WriteVSTD], (instregex "ST1i(8|16|32|64)$")>; 821def : InstRW<[M3WriteVSTD, 822 WriteAdr], (instregex "ST1i(8|16|32|64)_POST")>; 823 824def : InstRW<[M3WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>; 825def : InstRW<[M3WriteVSTD, 826 WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST")>; 827def : InstRW<[M3WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>; 828def : InstRW<[M3WriteVSTE, 829 WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST")>; 830 831def : InstRW<[M3WriteVSTD], (instregex "ST2i(8|16|32)$")>; 832def : InstRW<[M3WriteVSTD, 833 WriteAdr], (instregex "ST2i(8|16|32)_POST")>; 834def : InstRW<[M3WriteVSTD], (instregex "ST2i(64)$")>; 835def : InstRW<[M3WriteVSTD, 836 WriteAdr], (instregex "ST2i(64)_POST")>; 837 838def : InstRW<[M3WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>; 839def : InstRW<[M3WriteVSTF, 840 WriteAdr], (instregex "ST3Threev(8b|4h|2s)_POST")>; 841def : InstRW<[M3WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>; 842def : InstRW<[M3WriteVSTG, 843 WriteAdr], (instregex "ST3Threev(16b|8h|4s|2d)_POST")>; 844 845def : InstRW<[M3WriteVSTH], (instregex "ST3i(8|16|32)$")>; 846def : InstRW<[M3WriteVSTH, 847 WriteAdr], (instregex "ST3i(8|16|32)_POST")>; 848def : InstRW<[M3WriteVSTF], (instregex "ST3i(64)$")>; 849def : InstRW<[M3WriteVSTF, 850 WriteAdr], (instregex "ST3i(64)_POST")>; 851 852def : InstRW<[M3WriteVSTF], (instregex "ST4Fourv(8b|4h|2s)$")>; 853def : InstRW<[M3WriteVSTF, 854 WriteAdr], (instregex "ST4Fourv(8b|4h|2s)_POST")>; 855def : InstRW<[M3WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>; 856def : InstRW<[M3WriteVSTI, 857 WriteAdr], (instregex "ST4Fourv(16b|8h|4s|2d)_POST")>; 858 859def : InstRW<[M3WriteVSTF], (instregex "ST4i(8|16|32|64)$")>; 860def : InstRW<[M3WriteVSTF, 861 WriteAdr], (instregex "ST4i(8|16|32|64)_POST")>; 862 863// Cryptography instructions. 864def : InstRW<[M3WriteAES], (instregex "^AES[DE]")>; 865def : InstRW<[M3WriteAES, 866 M3ReadAES], (instregex "^AESI?MC")>; 867 868def : InstRW<[M3WriteNCRY3A], (instregex "^PMULL?v")>; 869 870def : InstRW<[M3WriteNCRY1A], (instregex "^SHA1([CHMP]|SU[01])")>; 871def : InstRW<[M3WriteNCRY1A], (instregex "^SHA256SU0")>; 872def : InstRW<[M3WriteNCRY5A], (instregex "^SHA256(H2?|SU1)")>; 873 874// CRC instructions. 875def : InstRW<[M3WriteC2], (instregex "^CRC32")>; 876 877} // SchedModel = ExynosM3Model 878