1 //===-- ARM.h - Top-level interface for ARM representation ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the entry points for global functions defined in the LLVM
10 // ARM back-end.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_ARM_ARM_H
15 #define LLVM_LIB_TARGET_ARM_ARM_H
16 
17 #include "llvm/IR/LegacyPassManager.h"
18 #include "llvm/Support/CodeGen.h"
19 #include <functional>
20 #include <vector>
21 
22 namespace llvm {
23 
24 class ARMAsmPrinter;
25 class ARMBaseTargetMachine;
26 class ARMRegisterBankInfo;
27 class ARMSubtarget;
28 struct BasicBlockInfo;
29 class Function;
30 class FunctionPass;
31 class InstructionSelector;
32 class MachineBasicBlock;
33 class MachineFunction;
34 class MachineInstr;
35 class MCInst;
36 class PassRegistry;
37 
38 Pass *createMVETailPredicationPass();
39 FunctionPass *createARMLowOverheadLoopsPass();
40 FunctionPass *createARMBlockPlacementPass();
41 Pass *createARMParallelDSPPass();
42 FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM,
43                                CodeGenOpt::Level OptLevel);
44 FunctionPass *createA15SDOptimizerPass();
45 FunctionPass *createARMLoadStoreOptimizationPass(bool PreAlloc = false);
46 FunctionPass *createARMExpandPseudoPass();
47 FunctionPass *createARMConstantIslandPass();
48 FunctionPass *createMLxExpansionPass();
49 FunctionPass *createThumb2ITBlockPass();
50 FunctionPass *createMVEVPTBlockPass();
51 FunctionPass *createMVETPAndVPTOptimisationsPass();
52 FunctionPass *createARMOptimizeBarriersPass();
53 FunctionPass *createThumb2SizeReductionPass(
54     std::function<bool(const Function &)> Ftor = nullptr);
55 InstructionSelector *
56 createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI,
57                              const ARMRegisterBankInfo &RBI);
58 Pass *createMVEGatherScatterLoweringPass();
59 FunctionPass *createARMSLSHardeningPass();
60 FunctionPass *createARMIndirectThunks();
61 Pass *createMVELaneInterleavingPass();
62 
63 void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
64                                   ARMAsmPrinter &AP);
65 
66 void initializeARMParallelDSPPass(PassRegistry &);
67 void initializeARMLoadStoreOptPass(PassRegistry &);
68 void initializeARMPreAllocLoadStoreOptPass(PassRegistry &);
69 void initializeARMConstantIslandsPass(PassRegistry &);
70 void initializeARMExpandPseudoPass(PassRegistry &);
71 void initializeThumb2SizeReducePass(PassRegistry &);
72 void initializeThumb2ITBlockPass(PassRegistry &);
73 void initializeMVEVPTBlockPass(PassRegistry &);
74 void initializeMVETPAndVPTOptimisationsPass(PassRegistry &);
75 void initializeARMLowOverheadLoopsPass(PassRegistry &);
76 void initializeARMBlockPlacementPass(PassRegistry &);
77 void initializeMVETailPredicationPass(PassRegistry &);
78 void initializeMVEGatherScatterLoweringPass(PassRegistry &);
79 void initializeARMSLSHardeningPass(PassRegistry &);
80 void initializeMVELaneInterleavingPass(PassRegistry &);
81 
82 } // end namespace llvm
83 
84 #endif // LLVM_LIB_TARGET_ARM_ARM_H
85