1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Base ARM implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
14 #define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
15
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/MachineInstr.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineOperand.h"
23 #include "llvm/CodeGen/TargetInstrInfo.h"
24 #include "llvm/IR/IntrinsicInst.h"
25 #include "llvm/IR/IntrinsicsARM.h"
26 #include <array>
27 #include <cstdint>
28
29 #define GET_INSTRINFO_HEADER
30 #include "ARMGenInstrInfo.inc"
31
32 namespace llvm {
33
34 class ARMBaseRegisterInfo;
35 class ARMSubtarget;
36
37 class ARMBaseInstrInfo : public ARMGenInstrInfo {
38 const ARMSubtarget &Subtarget;
39
40 protected:
41 // Can be only subclassed.
42 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
43
44 void expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
45 unsigned LoadImmOpc, unsigned LoadOpc) const;
46
47 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
48 /// and \p DefIdx.
49 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
50 /// the list is modeled as <Reg:SubReg, SubIdx>.
51 /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
52 /// two elements:
53 /// - %1:sub1, sub0
54 /// - %2<:0>, sub1
55 ///
56 /// \returns true if it is possible to build such an input sequence
57 /// with the pair \p MI, \p DefIdx. False otherwise.
58 ///
59 /// \pre MI.isRegSequenceLike().
60 bool getRegSequenceLikeInputs(
61 const MachineInstr &MI, unsigned DefIdx,
62 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override;
63
64 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
65 /// and \p DefIdx.
66 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
67 /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
68 /// - %1:sub1, sub0
69 ///
70 /// \returns true if it is possible to build such an input sequence
71 /// with the pair \p MI, \p DefIdx. False otherwise.
72 ///
73 /// \pre MI.isExtractSubregLike().
74 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
75 RegSubRegPairAndIdx &InputReg) const override;
76
77 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
78 /// and \p DefIdx.
79 /// \p [out] BaseReg and \p [out] InsertedReg contain
80 /// the equivalent inputs of INSERT_SUBREG.
81 /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
82 /// - BaseReg: %0:sub0
83 /// - InsertedReg: %1:sub1, sub3
84 ///
85 /// \returns true if it is possible to build such an input sequence
86 /// with the pair \p MI, \p DefIdx. False otherwise.
87 ///
88 /// \pre MI.isInsertSubregLike().
89 bool
90 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
91 RegSubRegPair &BaseReg,
92 RegSubRegPairAndIdx &InsertedReg) const override;
93
94 /// Commutes the operands in the given instruction.
95 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
96 ///
97 /// Do not call this method for a non-commutable instruction or for
98 /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
99 /// Even though the instruction is commutable, the method may still
100 /// fail to commute the operands, null pointer is returned in such cases.
101 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
102 unsigned OpIdx1,
103 unsigned OpIdx2) const override;
104 /// If the specific machine instruction is an instruction that moves/copies
105 /// value from one register to another register return destination and source
106 /// registers as machine operands.
107 Optional<DestSourcePair>
108 isCopyInstrImpl(const MachineInstr &MI) const override;
109
110 /// Specialization of \ref TargetInstrInfo::describeLoadedValue, used to
111 /// enhance debug entry value descriptions for ARM targets.
112 Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI,
113 Register Reg) const override;
114
115 public:
116 // Return whether the target has an explicit NOP encoding.
117 bool hasNOP() const;
118
119 // Return the non-pre/post incrementing version of 'Opc'. Return 0
120 // if there is not such an opcode.
121 virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
122
123 MachineInstr *convertToThreeAddress(MachineInstr &MI,
124 LiveVariables *LV) const override;
125
126 virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
getSubtarget()127 const ARMSubtarget &getSubtarget() const { return Subtarget; }
128
129 ScheduleHazardRecognizer *
130 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
131 const ScheduleDAG *DAG) const override;
132
133 ScheduleHazardRecognizer *
134 CreateTargetMIHazardRecognizer(const InstrItineraryData *II,
135 const ScheduleDAGMI *DAG) const override;
136
137 ScheduleHazardRecognizer *
138 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
139 const ScheduleDAG *DAG) const override;
140
141 // Branch analysis.
142 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
143 MachineBasicBlock *&FBB,
144 SmallVectorImpl<MachineOperand> &Cond,
145 bool AllowModify = false) const override;
146 unsigned removeBranch(MachineBasicBlock &MBB,
147 int *BytesRemoved = nullptr) const override;
148 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
149 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
150 const DebugLoc &DL,
151 int *BytesAdded = nullptr) const override;
152
153 bool
154 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
155
156 // Predication support.
157 bool isPredicated(const MachineInstr &MI) const override;
158
159 // MIR printer helper function to annotate Operands with a comment.
160 std::string
161 createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op,
162 unsigned OpIdx,
163 const TargetRegisterInfo *TRI) const override;
164
getPredicate(const MachineInstr & MI)165 ARMCC::CondCodes getPredicate(const MachineInstr &MI) const {
166 int PIdx = MI.findFirstPredOperandIdx();
167 return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm()
168 : ARMCC::AL;
169 }
170
171 bool PredicateInstruction(MachineInstr &MI,
172 ArrayRef<MachineOperand> Pred) const override;
173
174 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
175 ArrayRef<MachineOperand> Pred2) const override;
176
177 bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
178 bool SkipDead) const override;
179
180 bool isPredicable(const MachineInstr &MI) const override;
181
182 // CPSR defined in instruction
183 static bool isCPSRDefined(const MachineInstr &MI);
184
185 /// GetInstSize - Returns the size of the specified MachineInstr.
186 ///
187 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
188
189 unsigned isLoadFromStackSlot(const MachineInstr &MI,
190 int &FrameIndex) const override;
191 unsigned isStoreToStackSlot(const MachineInstr &MI,
192 int &FrameIndex) const override;
193 unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
194 int &FrameIndex) const override;
195 unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
196 int &FrameIndex) const override;
197
198 void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
199 unsigned SrcReg, bool KillSrc,
200 const ARMSubtarget &Subtarget) const;
201 void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
202 unsigned DestReg, bool KillSrc,
203 const ARMSubtarget &Subtarget) const;
204
205 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
206 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
207 bool KillSrc) const override;
208
209 void storeRegToStackSlot(MachineBasicBlock &MBB,
210 MachineBasicBlock::iterator MBBI,
211 Register SrcReg, bool isKill, int FrameIndex,
212 const TargetRegisterClass *RC,
213 const TargetRegisterInfo *TRI) const override;
214
215 void loadRegFromStackSlot(MachineBasicBlock &MBB,
216 MachineBasicBlock::iterator MBBI,
217 Register DestReg, int FrameIndex,
218 const TargetRegisterClass *RC,
219 const TargetRegisterInfo *TRI) const override;
220
221 bool expandPostRAPseudo(MachineInstr &MI) const override;
222
223 bool shouldSink(const MachineInstr &MI) const override;
224
225 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
226 Register DestReg, unsigned SubIdx,
227 const MachineInstr &Orig,
228 const TargetRegisterInfo &TRI) const override;
229
230 MachineInstr &
231 duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
232 const MachineInstr &Orig) const override;
233
234 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
235 unsigned SubIdx, unsigned State,
236 const TargetRegisterInfo *TRI) const;
237
238 bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
239 const MachineRegisterInfo *MRI) const override;
240
241 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
242 /// determine if two loads are loading from the same base address. It should
243 /// only return true if the base pointers are the same and the only
244 /// differences between the two addresses is the offset. It also returns the
245 /// offsets by reference.
246 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
247 int64_t &Offset2) const override;
248
249 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
250 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
251 /// should be scheduled togther. On some targets if two loads are loading from
252 /// addresses in the same cache line, it's better if they are scheduled
253 /// together. This function takes two integers that represent the load offsets
254 /// from the common base address. It returns true if it decides it's desirable
255 /// to schedule the two loads together. "NumLoads" is the number of loads that
256 /// have already been scheduled after Load1.
257 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
258 int64_t Offset1, int64_t Offset2,
259 unsigned NumLoads) const override;
260
261 bool isSchedulingBoundary(const MachineInstr &MI,
262 const MachineBasicBlock *MBB,
263 const MachineFunction &MF) const override;
264
265 bool isProfitableToIfCvt(MachineBasicBlock &MBB,
266 unsigned NumCycles, unsigned ExtraPredCycles,
267 BranchProbability Probability) const override;
268
269 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
270 unsigned ExtraT, MachineBasicBlock &FMBB,
271 unsigned NumF, unsigned ExtraF,
272 BranchProbability Probability) const override;
273
isProfitableToDupForIfCvt(MachineBasicBlock & MBB,unsigned NumCycles,BranchProbability Probability)274 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
275 BranchProbability Probability) const override {
276 return NumCycles == 1;
277 }
278
279 unsigned extraSizeToPredicateInstructions(const MachineFunction &MF,
280 unsigned NumInsts) const override;
281 unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const override;
282
283 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
284 MachineBasicBlock &FMBB) const override;
285
286 /// analyzeCompare - For a comparison instruction, return the source registers
287 /// in SrcReg and SrcReg2 if having two register operands, and the value it
288 /// compares against in CmpValue. Return true if the comparison instruction
289 /// can be analyzed.
290 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
291 Register &SrcReg2, int64_t &CmpMask,
292 int64_t &CmpValue) const override;
293
294 /// optimizeCompareInstr - Convert the instruction to set the zero flag so
295 /// that we can remove a "comparison with zero"; Remove a redundant CMP
296 /// instruction if the flags can be updated in the same way by an earlier
297 /// instruction such as SUB.
298 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
299 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
300 const MachineRegisterInfo *MRI) const override;
301
302 bool analyzeSelect(const MachineInstr &MI,
303 SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
304 unsigned &FalseOp, bool &Optimizable) const override;
305
306 MachineInstr *optimizeSelect(MachineInstr &MI,
307 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
308 bool) const override;
309
310 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
311 /// instruction, try to fold the immediate into the use instruction.
312 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
313 MachineRegisterInfo *MRI) const override;
314
315 unsigned getNumMicroOps(const InstrItineraryData *ItinData,
316 const MachineInstr &MI) const override;
317
318 int getOperandLatency(const InstrItineraryData *ItinData,
319 const MachineInstr &DefMI, unsigned DefIdx,
320 const MachineInstr &UseMI,
321 unsigned UseIdx) const override;
322 int getOperandLatency(const InstrItineraryData *ItinData,
323 SDNode *DefNode, unsigned DefIdx,
324 SDNode *UseNode, unsigned UseIdx) const override;
325
326 /// VFP/NEON execution domains.
327 std::pair<uint16_t, uint16_t>
328 getExecutionDomain(const MachineInstr &MI) const override;
329 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
330
331 unsigned
332 getPartialRegUpdateClearance(const MachineInstr &, unsigned,
333 const TargetRegisterInfo *) const override;
334 void breakPartialRegDependency(MachineInstr &, unsigned,
335 const TargetRegisterInfo *TRI) const override;
336
337 /// Get the number of addresses by LDM or VLDM or zero for unknown.
338 unsigned getNumLDMAddresses(const MachineInstr &MI) const;
339
340 std::pair<unsigned, unsigned>
341 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
342 ArrayRef<std::pair<unsigned, const char *>>
343 getSerializableDirectMachineOperandTargetFlags() const override;
344 ArrayRef<std::pair<unsigned, const char *>>
345 getSerializableBitmaskMachineOperandTargetFlags() const override;
346
347 /// ARM supports the MachineOutliner.
348 bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
349 bool OutlineFromLinkOnceODRs) const override;
350 outliner::OutlinedFunction getOutliningCandidateInfo(
351 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
352 outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT,
353 unsigned Flags) const override;
354 bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
355 unsigned &Flags) const override;
356 void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
357 const outliner::OutlinedFunction &OF) const override;
358 MachineBasicBlock::iterator
359 insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
360 MachineBasicBlock::iterator &It, MachineFunction &MF,
361 const outliner::Candidate &C) const override;
362
363 /// Enable outlining by default at -Oz.
364 bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
365
isUnspillableTerminatorImpl(const MachineInstr * MI)366 bool isUnspillableTerminatorImpl(const MachineInstr *MI) const override {
367 return MI->getOpcode() == ARM::t2LoopEndDec ||
368 MI->getOpcode() == ARM::t2DoLoopStartTP ||
369 MI->getOpcode() == ARM::t2WhileLoopStartLR ||
370 MI->getOpcode() == ARM::t2WhileLoopStartTP;
371 }
372
373 private:
374 /// Returns an unused general-purpose register which can be used for
375 /// constructing an outlined call if one exists. Returns 0 otherwise.
376 unsigned findRegisterToSaveLRTo(const outliner::Candidate &C) const;
377
378 // Adds an instruction which saves the link register on top of the stack into
379 /// the MachineBasicBlock \p MBB at position \p It.
380 void saveLROnStack(MachineBasicBlock &MBB,
381 MachineBasicBlock::iterator It) const;
382
383 /// Adds an instruction which restores the link register from the top the
384 /// stack into the MachineBasicBlock \p MBB at position \p It.
385 void restoreLRFromStack(MachineBasicBlock &MBB,
386 MachineBasicBlock::iterator It) const;
387
388 /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It,
389 /// for the case when the LR is saved on the stack.
390 void emitCFIForLRSaveOnStack(MachineBasicBlock &MBB,
391 MachineBasicBlock::iterator It) const;
392
393 /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It,
394 /// for the case when the LR is saved in the register \p Reg.
395 void emitCFIForLRSaveToReg(MachineBasicBlock &MBB,
396 MachineBasicBlock::iterator It,
397 Register Reg) const;
398
399 /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It,
400 /// after the LR is was restored from the stack.
401 void emitCFIForLRRestoreFromStack(MachineBasicBlock &MBB,
402 MachineBasicBlock::iterator It) const;
403
404 /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It,
405 /// after the LR is was restored from a register.
406 void emitCFIForLRRestoreFromReg(MachineBasicBlock &MBB,
407 MachineBasicBlock::iterator It) const;
408 /// \brief Sets the offsets on outlined instructions in \p MBB which use SP
409 /// so that they will be valid post-outlining.
410 ///
411 /// \param MBB A \p MachineBasicBlock in an outlined function.
412 void fixupPostOutline(MachineBasicBlock &MBB) const;
413
414 /// Returns true if the machine instruction offset can handle the stack fixup
415 /// and updates it if requested.
416 bool checkAndUpdateStackOffset(MachineInstr *MI, int64_t Fixup,
417 bool Updt) const;
418
419 unsigned getInstBundleLength(const MachineInstr &MI) const;
420
421 int getVLDMDefCycle(const InstrItineraryData *ItinData,
422 const MCInstrDesc &DefMCID,
423 unsigned DefClass,
424 unsigned DefIdx, unsigned DefAlign) const;
425 int getLDMDefCycle(const InstrItineraryData *ItinData,
426 const MCInstrDesc &DefMCID,
427 unsigned DefClass,
428 unsigned DefIdx, unsigned DefAlign) const;
429 int getVSTMUseCycle(const InstrItineraryData *ItinData,
430 const MCInstrDesc &UseMCID,
431 unsigned UseClass,
432 unsigned UseIdx, unsigned UseAlign) const;
433 int getSTMUseCycle(const InstrItineraryData *ItinData,
434 const MCInstrDesc &UseMCID,
435 unsigned UseClass,
436 unsigned UseIdx, unsigned UseAlign) const;
437 int getOperandLatency(const InstrItineraryData *ItinData,
438 const MCInstrDesc &DefMCID,
439 unsigned DefIdx, unsigned DefAlign,
440 const MCInstrDesc &UseMCID,
441 unsigned UseIdx, unsigned UseAlign) const;
442
443 int getOperandLatencyImpl(const InstrItineraryData *ItinData,
444 const MachineInstr &DefMI, unsigned DefIdx,
445 const MCInstrDesc &DefMCID, unsigned DefAdj,
446 const MachineOperand &DefMO, unsigned Reg,
447 const MachineInstr &UseMI, unsigned UseIdx,
448 const MCInstrDesc &UseMCID, unsigned UseAdj) const;
449
450 unsigned getPredicationCost(const MachineInstr &MI) const override;
451
452 unsigned getInstrLatency(const InstrItineraryData *ItinData,
453 const MachineInstr &MI,
454 unsigned *PredCost = nullptr) const override;
455
456 int getInstrLatency(const InstrItineraryData *ItinData,
457 SDNode *Node) const override;
458
459 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
460 const MachineRegisterInfo *MRI,
461 const MachineInstr &DefMI, unsigned DefIdx,
462 const MachineInstr &UseMI,
463 unsigned UseIdx) const override;
464 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
465 const MachineInstr &DefMI,
466 unsigned DefIdx) const override;
467
468 /// verifyInstruction - Perform target specific instruction verification.
469 bool verifyInstruction(const MachineInstr &MI,
470 StringRef &ErrInfo) const override;
471
472 virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI) const = 0;
473
474 void expandMEMCPY(MachineBasicBlock::iterator) const;
475
476 /// Identify instructions that can be folded into a MOVCC instruction, and
477 /// return the defining instruction.
478 MachineInstr *canFoldIntoMOVCC(Register Reg, const MachineRegisterInfo &MRI,
479 const TargetInstrInfo *TII) const;
480
481 bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
482 AAResults *AA) const override;
483
484 private:
485 /// Modeling special VFP / NEON fp MLA / MLS hazards.
486
487 /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
488 /// MLx table.
489 DenseMap<unsigned, unsigned> MLxEntryMap;
490
491 /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
492 /// stalls when scheduled together with fp MLA / MLS opcodes.
493 SmallSet<unsigned, 16> MLxHazardOpcodes;
494
495 public:
496 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
497 /// instruction.
isFpMLxInstruction(unsigned Opcode)498 bool isFpMLxInstruction(unsigned Opcode) const {
499 return MLxEntryMap.count(Opcode);
500 }
501
502 /// isFpMLxInstruction - This version also returns the multiply opcode and the
503 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
504 /// the MLX instructions with an extra lane operand.
505 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
506 unsigned &AddSubOpc, bool &NegAcc,
507 bool &HasLane) const;
508
509 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
510 /// will cause stalls when scheduled after (within 4-cycle window) a fp
511 /// MLA / MLS instruction.
canCauseFpMLxStall(unsigned Opcode)512 bool canCauseFpMLxStall(unsigned Opcode) const {
513 return MLxHazardOpcodes.count(Opcode);
514 }
515
516 /// Returns true if the instruction has a shift by immediate that can be
517 /// executed in one cycle less.
518 bool isSwiftFastImmShift(const MachineInstr *MI) const;
519
520 /// Returns predicate register associated with the given frame instruction.
getFramePred(const MachineInstr & MI)521 unsigned getFramePred(const MachineInstr &MI) const {
522 assert(isFrameInstr(MI));
523 // Operands of ADJCALLSTACKDOWN/ADJCALLSTACKUP:
524 // - argument declared in the pattern:
525 // 0 - frame size
526 // 1 - arg of CALLSEQ_START/CALLSEQ_END
527 // 2 - predicate code (like ARMCC::AL)
528 // - added by predOps:
529 // 3 - predicate reg
530 return MI.getOperand(3).getReg();
531 }
532
533 Optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
534 Register Reg) const override;
535 };
536
537 /// Get the operands corresponding to the given \p Pred value. By default, the
538 /// predicate register is assumed to be 0 (no register), but you can pass in a
539 /// \p PredReg if that is not the case.
540 static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred,
541 unsigned PredReg = 0) {
542 return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
543 MachineOperand::CreateReg(PredReg, false)}};
544 }
545
546 /// Get the operand corresponding to the conditional code result. By default,
547 /// this is 0 (no register).
548 static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
549 return MachineOperand::CreateReg(CCReg, false);
550 }
551
552 /// Get the operand corresponding to the conditional code result for Thumb1.
553 /// This operand will always refer to CPSR and it will have the Define flag set.
554 /// You can optionally set the Dead flag by means of \p isDead.
555 static inline MachineOperand t1CondCodeOp(bool isDead = false) {
556 return MachineOperand::CreateReg(ARM::CPSR,
557 /*Define*/ true, /*Implicit*/ false,
558 /*Kill*/ false, isDead);
559 }
560
561 static inline
isUncondBranchOpcode(int Opc)562 bool isUncondBranchOpcode(int Opc) {
563 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
564 }
565
566 // This table shows the VPT instruction variants, i.e. the different
567 // mask field encodings, see also B5.6. Predication/conditional execution in
568 // the ArmARM.
isVPTOpcode(int Opc)569 static inline bool isVPTOpcode(int Opc) {
570 return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 ||
571 Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 ||
572 Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 ||
573 Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 ||
574 Opc == ARM::MVE_VPTv4s32 || Opc == ARM::MVE_VPTv4f32 ||
575 Opc == ARM::MVE_VPTv8f16 || Opc == ARM::MVE_VPTv16i8r ||
576 Opc == ARM::MVE_VPTv16u8r || Opc == ARM::MVE_VPTv16s8r ||
577 Opc == ARM::MVE_VPTv8i16r || Opc == ARM::MVE_VPTv8u16r ||
578 Opc == ARM::MVE_VPTv8s16r || Opc == ARM::MVE_VPTv4i32r ||
579 Opc == ARM::MVE_VPTv4u32r || Opc == ARM::MVE_VPTv4s32r ||
580 Opc == ARM::MVE_VPTv4f32r || Opc == ARM::MVE_VPTv8f16r ||
581 Opc == ARM::MVE_VPST;
582 }
583
584 static inline
VCMPOpcodeToVPT(unsigned Opcode)585 unsigned VCMPOpcodeToVPT(unsigned Opcode) {
586 switch (Opcode) {
587 default:
588 return 0;
589 case ARM::MVE_VCMPf32:
590 return ARM::MVE_VPTv4f32;
591 case ARM::MVE_VCMPf16:
592 return ARM::MVE_VPTv8f16;
593 case ARM::MVE_VCMPi8:
594 return ARM::MVE_VPTv16i8;
595 case ARM::MVE_VCMPi16:
596 return ARM::MVE_VPTv8i16;
597 case ARM::MVE_VCMPi32:
598 return ARM::MVE_VPTv4i32;
599 case ARM::MVE_VCMPu8:
600 return ARM::MVE_VPTv16u8;
601 case ARM::MVE_VCMPu16:
602 return ARM::MVE_VPTv8u16;
603 case ARM::MVE_VCMPu32:
604 return ARM::MVE_VPTv4u32;
605 case ARM::MVE_VCMPs8:
606 return ARM::MVE_VPTv16s8;
607 case ARM::MVE_VCMPs16:
608 return ARM::MVE_VPTv8s16;
609 case ARM::MVE_VCMPs32:
610 return ARM::MVE_VPTv4s32;
611
612 case ARM::MVE_VCMPf32r:
613 return ARM::MVE_VPTv4f32r;
614 case ARM::MVE_VCMPf16r:
615 return ARM::MVE_VPTv8f16r;
616 case ARM::MVE_VCMPi8r:
617 return ARM::MVE_VPTv16i8r;
618 case ARM::MVE_VCMPi16r:
619 return ARM::MVE_VPTv8i16r;
620 case ARM::MVE_VCMPi32r:
621 return ARM::MVE_VPTv4i32r;
622 case ARM::MVE_VCMPu8r:
623 return ARM::MVE_VPTv16u8r;
624 case ARM::MVE_VCMPu16r:
625 return ARM::MVE_VPTv8u16r;
626 case ARM::MVE_VCMPu32r:
627 return ARM::MVE_VPTv4u32r;
628 case ARM::MVE_VCMPs8r:
629 return ARM::MVE_VPTv16s8r;
630 case ARM::MVE_VCMPs16r:
631 return ARM::MVE_VPTv8s16r;
632 case ARM::MVE_VCMPs32r:
633 return ARM::MVE_VPTv4s32r;
634 }
635 }
636
637 static inline
isCondBranchOpcode(int Opc)638 bool isCondBranchOpcode(int Opc) {
639 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
640 }
641
isJumpTableBranchOpcode(int Opc)642 static inline bool isJumpTableBranchOpcode(int Opc) {
643 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 ||
644 Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr ||
645 Opc == ARM::t2BR_JT;
646 }
647
648 static inline
isIndirectBranchOpcode(int Opc)649 bool isIndirectBranchOpcode(int Opc) {
650 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
651 }
652
isIndirectCall(const MachineInstr & MI)653 static inline bool isIndirectCall(const MachineInstr &MI) {
654 int Opc = MI.getOpcode();
655 switch (Opc) {
656 // indirect calls:
657 case ARM::BLX:
658 case ARM::BLX_noip:
659 case ARM::BLX_pred:
660 case ARM::BLX_pred_noip:
661 case ARM::BX_CALL:
662 case ARM::BMOVPCRX_CALL:
663 case ARM::TCRETURNri:
664 case ARM::TAILJMPr:
665 case ARM::TAILJMPr4:
666 case ARM::tBLXr:
667 case ARM::tBLXr_noip:
668 case ARM::tBLXNSr:
669 case ARM::tBLXNS_CALL:
670 case ARM::tBX_CALL:
671 case ARM::tTAILJMPr:
672 assert(MI.isCall(MachineInstr::IgnoreBundle));
673 return true;
674 // direct calls:
675 case ARM::BL:
676 case ARM::BL_pred:
677 case ARM::BMOVPCB_CALL:
678 case ARM::BL_PUSHLR:
679 case ARM::BLXi:
680 case ARM::TCRETURNdi:
681 case ARM::TAILJMPd:
682 case ARM::SVC:
683 case ARM::HVC:
684 case ARM::TPsoft:
685 case ARM::tTAILJMPd:
686 case ARM::t2SMC:
687 case ARM::t2HVC:
688 case ARM::tBL:
689 case ARM::tBLXi:
690 case ARM::tBL_PUSHLR:
691 case ARM::tTAILJMPdND:
692 case ARM::tSVC:
693 case ARM::tTPsoft:
694 assert(MI.isCall(MachineInstr::IgnoreBundle));
695 return false;
696 }
697 assert(!MI.isCall(MachineInstr::IgnoreBundle));
698 return false;
699 }
700
isIndirectControlFlowNotComingBack(const MachineInstr & MI)701 static inline bool isIndirectControlFlowNotComingBack(const MachineInstr &MI) {
702 int opc = MI.getOpcode();
703 return MI.isReturn() || isIndirectBranchOpcode(MI.getOpcode()) ||
704 isJumpTableBranchOpcode(opc);
705 }
706
isSpeculationBarrierEndBBOpcode(int Opc)707 static inline bool isSpeculationBarrierEndBBOpcode(int Opc) {
708 return Opc == ARM::SpeculationBarrierISBDSBEndBB ||
709 Opc == ARM::SpeculationBarrierSBEndBB ||
710 Opc == ARM::t2SpeculationBarrierISBDSBEndBB ||
711 Opc == ARM::t2SpeculationBarrierSBEndBB;
712 }
713
isPopOpcode(int Opc)714 static inline bool isPopOpcode(int Opc) {
715 return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
716 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
717 Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
718 }
719
isPushOpcode(int Opc)720 static inline bool isPushOpcode(int Opc) {
721 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
722 Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
723 }
724
isSubImmOpcode(int Opc)725 static inline bool isSubImmOpcode(int Opc) {
726 return Opc == ARM::SUBri ||
727 Opc == ARM::tSUBi3 || Opc == ARM::tSUBi8 ||
728 Opc == ARM::tSUBSi3 || Opc == ARM::tSUBSi8 ||
729 Opc == ARM::t2SUBri || Opc == ARM::t2SUBri12 || Opc == ARM::t2SUBSri;
730 }
731
isMovRegOpcode(int Opc)732 static inline bool isMovRegOpcode(int Opc) {
733 return Opc == ARM::MOVr || Opc == ARM::tMOVr || Opc == ARM::t2MOVr;
734 }
735 /// isValidCoprocessorNumber - decide whether an explicit coprocessor
736 /// number is legal in generic instructions like CDP. The answer can
737 /// vary with the subtarget.
isValidCoprocessorNumber(unsigned Num,const FeatureBitset & featureBits)738 static inline bool isValidCoprocessorNumber(unsigned Num,
739 const FeatureBitset& featureBits) {
740 // In Armv7 and Armv8-M CP10 and CP11 clash with VFP/NEON, however, the
741 // coprocessor is still valid for CDP/MCR/MRC and friends. Allowing it is
742 // useful for code which is shared with older architectures which do not know
743 // the new VFP/NEON mnemonics.
744
745 // Armv8-A disallows everything *other* than 111x (CP14 and CP15).
746 if (featureBits[ARM::HasV8Ops] && (Num & 0xE) != 0xE)
747 return false;
748
749 // Armv8.1-M disallows 100x (CP8,CP9) and 111x (CP14,CP15)
750 // which clash with MVE.
751 if (featureBits[ARM::HasV8_1MMainlineOps] &&
752 ((Num & 0xE) == 0x8 || (Num & 0xE) == 0xE))
753 return false;
754
755 return true;
756 }
757
758 /// getInstrPredicate - If instruction is predicated, returns its predicate
759 /// condition, otherwise returns AL. It also returns the condition code
760 /// register by reference.
761 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg);
762
763 unsigned getMatchingCondBranchOpcode(unsigned Opc);
764
765 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
766 /// the instruction is encoded with an 'S' bit is determined by the optional
767 /// CPSR def operand.
768 unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
769
770 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
771 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
772 /// code.
773 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
774 MachineBasicBlock::iterator &MBBI,
775 const DebugLoc &dl, Register DestReg,
776 Register BaseReg, int NumBytes,
777 ARMCC::CondCodes Pred, Register PredReg,
778 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
779
780 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
781 MachineBasicBlock::iterator &MBBI,
782 const DebugLoc &dl, Register DestReg,
783 Register BaseReg, int NumBytes,
784 ARMCC::CondCodes Pred, Register PredReg,
785 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
786 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
787 MachineBasicBlock::iterator &MBBI,
788 const DebugLoc &dl, Register DestReg,
789 Register BaseReg, int NumBytes,
790 const TargetInstrInfo &TII,
791 const ARMBaseRegisterInfo &MRI,
792 unsigned MIFlags = 0);
793
794 /// Tries to add registers to the reglist of a given base-updating
795 /// push/pop instruction to adjust the stack by an additional
796 /// NumBytes. This can save a few bytes per function in code-size, but
797 /// obviously generates more memory traffic. As such, it only takes
798 /// effect in functions being optimised for size.
799 bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
800 MachineFunction &MF, MachineInstr *MI,
801 unsigned NumBytes);
802
803 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
804 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
805 /// offset could not be handled directly in MI, and return the left-over
806 /// portion by reference.
807 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
808 Register FrameReg, int &Offset,
809 const ARMBaseInstrInfo &TII);
810
811 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
812 Register FrameReg, int &Offset,
813 const ARMBaseInstrInfo &TII,
814 const TargetRegisterInfo *TRI);
815
816 /// Return true if Reg is defd between From and To
817 bool registerDefinedBetween(unsigned Reg, MachineBasicBlock::iterator From,
818 MachineBasicBlock::iterator To,
819 const TargetRegisterInfo *TRI);
820
821 /// Search backwards from a tBcc to find a tCMPi8 against 0, meaning
822 /// we can convert them to a tCBZ or tCBNZ. Return nullptr if not found.
823 MachineInstr *findCMPToFoldIntoCBZ(MachineInstr *Br,
824 const TargetRegisterInfo *TRI);
825
826 void addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB);
827 void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, Register DestReg);
828
829 void addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond);
830 void addPredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned Cond,
831 unsigned Inactive);
832
833 /// Returns the number of instructions required to materialize the given
834 /// constant in a register, or 3 if a literal pool load is needed.
835 /// If ForCodesize is specified, an approximate cost in bytes is returned.
836 unsigned ConstantMaterializationCost(unsigned Val,
837 const ARMSubtarget *Subtarget,
838 bool ForCodesize = false);
839
840 /// Returns true if Val1 has a lower Constant Materialization Cost than Val2.
841 /// Uses the cost from ConstantMaterializationCost, first with ForCodesize as
842 /// specified. If the scores are equal, return the comparison for !ForCodesize.
843 bool HasLowerConstantMaterializationCost(unsigned Val1, unsigned Val2,
844 const ARMSubtarget *Subtarget,
845 bool ForCodesize = false);
846
847 // Return the immediate if this is ADDri or SUBri, scaled as appropriate.
848 // Returns 0 for unknown instructions.
getAddSubImmediate(MachineInstr & MI)849 inline int getAddSubImmediate(MachineInstr &MI) {
850 int Scale = 1;
851 unsigned ImmOp;
852 switch (MI.getOpcode()) {
853 case ARM::t2ADDri:
854 ImmOp = 2;
855 break;
856 case ARM::t2SUBri:
857 case ARM::t2SUBri12:
858 ImmOp = 2;
859 Scale = -1;
860 break;
861 case ARM::tSUBi3:
862 case ARM::tSUBi8:
863 ImmOp = 3;
864 Scale = -1;
865 break;
866 default:
867 return 0;
868 }
869 return Scale * MI.getOperand(ImmOp).getImm();
870 }
871
872 // Given a memory access Opcode, check that the give Imm would be a valid Offset
873 // for this instruction using its addressing mode.
isLegalAddressImm(unsigned Opcode,int Imm,const TargetInstrInfo * TII)874 inline bool isLegalAddressImm(unsigned Opcode, int Imm,
875 const TargetInstrInfo *TII) {
876 const MCInstrDesc &Desc = TII->get(Opcode);
877 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
878 switch (AddrMode) {
879 case ARMII::AddrModeT2_i7:
880 return std::abs(Imm) < (((1 << 7) * 1) - 1);
881 case ARMII::AddrModeT2_i7s2:
882 return std::abs(Imm) < (((1 << 7) * 2) - 1) && Imm % 2 == 0;
883 case ARMII::AddrModeT2_i7s4:
884 return std::abs(Imm) < (((1 << 7) * 4) - 1) && Imm % 4 == 0;
885 case ARMII::AddrModeT2_i8:
886 return std::abs(Imm) < (((1 << 8) * 1) - 1);
887 case ARMII::AddrMode2:
888 return std::abs(Imm) < (((1 << 12) * 1) - 1);
889 case ARMII::AddrModeT2_i12:
890 return Imm >= 0 && Imm < (((1 << 12) * 1) - 1);
891 case ARMII::AddrModeT2_i8s4:
892 return std::abs(Imm) < (((1 << 8) * 4) - 1) && Imm % 4 == 0;
893 default:
894 llvm_unreachable("Unhandled Addressing mode");
895 }
896 }
897
898 // Return true if the given intrinsic is a gather
isGather(IntrinsicInst * IntInst)899 inline bool isGather(IntrinsicInst *IntInst) {
900 if (IntInst == nullptr)
901 return false;
902 unsigned IntrinsicID = IntInst->getIntrinsicID();
903 return (IntrinsicID == Intrinsic::masked_gather ||
904 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base ||
905 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_predicated ||
906 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb ||
907 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb_predicated ||
908 IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset ||
909 IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset_predicated);
910 }
911
912 // Return true if the given intrinsic is a scatter
isScatter(IntrinsicInst * IntInst)913 inline bool isScatter(IntrinsicInst *IntInst) {
914 if (IntInst == nullptr)
915 return false;
916 unsigned IntrinsicID = IntInst->getIntrinsicID();
917 return (IntrinsicID == Intrinsic::masked_scatter ||
918 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base ||
919 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_predicated ||
920 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb ||
921 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb_predicated ||
922 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset ||
923 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset_predicated);
924 }
925
926 // Return true if the given intrinsic is a gather or scatter
isGatherScatter(IntrinsicInst * IntInst)927 inline bool isGatherScatter(IntrinsicInst *IntInst) {
928 if (IntInst == nullptr)
929 return false;
930 return isGather(IntInst) || isScatter(IntInst);
931 }
932
933 unsigned getBLXOpcode(const MachineFunction &MF);
934 unsigned gettBLXrOpcode(const MachineFunction &MF);
935 unsigned getBLXpredOpcode(const MachineFunction &MF);
936
937 } // end namespace llvm
938
939 #endif // LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
940