1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
3
4define i1 @t32_3_1(i32 %X) nounwind {
5; CHECK-LABEL: t32_3_1:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    mov w8, #43691
8; CHECK-NEXT:    mov w9, #1431655765
9; CHECK-NEXT:    movk w8, #43690, lsl #16
10; CHECK-NEXT:    madd w8, w0, w8, w9
11; CHECK-NEXT:    cmp w8, w9
12; CHECK-NEXT:    cset w0, lo
13; CHECK-NEXT:    ret
14  %urem = urem i32 %X, 3
15  %cmp = icmp eq i32 %urem, 1
16  ret i1 %cmp
17}
18
19define i1 @t32_3_2(i32 %X) nounwind {
20; CHECK-LABEL: t32_3_2:
21; CHECK:       // %bb.0:
22; CHECK-NEXT:    mov w8, #43691
23; CHECK-NEXT:    mov w9, #-1431655766
24; CHECK-NEXT:    movk w8, #43690, lsl #16
25; CHECK-NEXT:    madd w8, w0, w8, w9
26; CHECK-NEXT:    mov w9, #1431655765
27; CHECK-NEXT:    cmp w8, w9
28; CHECK-NEXT:    cset w0, lo
29; CHECK-NEXT:    ret
30  %urem = urem i32 %X, 3
31  %cmp = icmp eq i32 %urem, 2
32  ret i1 %cmp
33}
34
35
36define i1 @t32_5_1(i32 %X) nounwind {
37; CHECK-LABEL: t32_5_1:
38; CHECK:       // %bb.0:
39; CHECK-NEXT:    mov w8, #52429
40; CHECK-NEXT:    mov w9, #858993459
41; CHECK-NEXT:    movk w8, #52428, lsl #16
42; CHECK-NEXT:    madd w8, w0, w8, w9
43; CHECK-NEXT:    cmp w8, w9
44; CHECK-NEXT:    cset w0, lo
45; CHECK-NEXT:    ret
46  %urem = urem i32 %X, 5
47  %cmp = icmp eq i32 %urem, 1
48  ret i1 %cmp
49}
50
51define i1 @t32_5_2(i32 %X) nounwind {
52; CHECK-LABEL: t32_5_2:
53; CHECK:       // %bb.0:
54; CHECK-NEXT:    mov w8, #52429
55; CHECK-NEXT:    mov w9, #1717986918
56; CHECK-NEXT:    movk w8, #52428, lsl #16
57; CHECK-NEXT:    madd w8, w0, w8, w9
58; CHECK-NEXT:    mov w9, #858993459
59; CHECK-NEXT:    cmp w8, w9
60; CHECK-NEXT:    cset w0, lo
61; CHECK-NEXT:    ret
62  %urem = urem i32 %X, 5
63  %cmp = icmp eq i32 %urem, 2
64  ret i1 %cmp
65}
66
67define i1 @t32_5_3(i32 %X) nounwind {
68; CHECK-LABEL: t32_5_3:
69; CHECK:       // %bb.0:
70; CHECK-NEXT:    mov w8, #52429
71; CHECK-NEXT:    mov w9, #-1717986919
72; CHECK-NEXT:    movk w8, #52428, lsl #16
73; CHECK-NEXT:    madd w8, w0, w8, w9
74; CHECK-NEXT:    mov w9, #858993459
75; CHECK-NEXT:    cmp w8, w9
76; CHECK-NEXT:    cset w0, lo
77; CHECK-NEXT:    ret
78  %urem = urem i32 %X, 5
79  %cmp = icmp eq i32 %urem, 3
80  ret i1 %cmp
81}
82
83define i1 @t32_5_4(i32 %X) nounwind {
84; CHECK-LABEL: t32_5_4:
85; CHECK:       // %bb.0:
86; CHECK-NEXT:    mov w8, #52429
87; CHECK-NEXT:    mov w9, #-858993460
88; CHECK-NEXT:    movk w8, #52428, lsl #16
89; CHECK-NEXT:    madd w8, w0, w8, w9
90; CHECK-NEXT:    mov w9, #858993459
91; CHECK-NEXT:    cmp w8, w9
92; CHECK-NEXT:    cset w0, lo
93; CHECK-NEXT:    ret
94  %urem = urem i32 %X, 5
95  %cmp = icmp eq i32 %urem, 4
96  ret i1 %cmp
97}
98
99
100define i1 @t32_6_1(i32 %X) nounwind {
101; CHECK-LABEL: t32_6_1:
102; CHECK:       // %bb.0:
103; CHECK-NEXT:    mov w8, #43691
104; CHECK-NEXT:    mov w9, #1431655765
105; CHECK-NEXT:    movk w8, #43690, lsl #16
106; CHECK-NEXT:    madd w8, w0, w8, w9
107; CHECK-NEXT:    mov w9, #43691
108; CHECK-NEXT:    movk w9, #10922, lsl #16
109; CHECK-NEXT:    ror w8, w8, #1
110; CHECK-NEXT:    cmp w8, w9
111; CHECK-NEXT:    cset w0, lo
112; CHECK-NEXT:    ret
113  %urem = urem i32 %X, 6
114  %cmp = icmp eq i32 %urem, 1
115  ret i1 %cmp
116}
117
118define i1 @t32_6_2(i32 %X) nounwind {
119; CHECK-LABEL: t32_6_2:
120; CHECK:       // %bb.0:
121; CHECK-NEXT:    mov w8, #43691
122; CHECK-NEXT:    mov w9, #-1431655766
123; CHECK-NEXT:    movk w8, #43690, lsl #16
124; CHECK-NEXT:    madd w8, w0, w8, w9
125; CHECK-NEXT:    mov w9, #43691
126; CHECK-NEXT:    movk w9, #10922, lsl #16
127; CHECK-NEXT:    ror w8, w8, #1
128; CHECK-NEXT:    cmp w8, w9
129; CHECK-NEXT:    cset w0, lo
130; CHECK-NEXT:    ret
131  %urem = urem i32 %X, 6
132  %cmp = icmp eq i32 %urem, 2
133  ret i1 %cmp
134}
135
136define i1 @t32_6_3(i32 %X) nounwind {
137; CHECK-LABEL: t32_6_3:
138; CHECK:       // %bb.0:
139; CHECK-NEXT:    mov w8, #43691
140; CHECK-NEXT:    mov w9, #43691
141; CHECK-NEXT:    movk w8, #43690, lsl #16
142; CHECK-NEXT:    movk w9, #10922, lsl #16
143; CHECK-NEXT:    mul w8, w0, w8
144; CHECK-NEXT:    sub w8, w8, #1
145; CHECK-NEXT:    ror w8, w8, #1
146; CHECK-NEXT:    cmp w8, w9
147; CHECK-NEXT:    cset w0, lo
148; CHECK-NEXT:    ret
149  %urem = urem i32 %X, 6
150  %cmp = icmp eq i32 %urem, 3
151  ret i1 %cmp
152}
153
154define i1 @t32_6_4(i32 %X) nounwind {
155; CHECK-LABEL: t32_6_4:
156; CHECK:       // %bb.0:
157; CHECK-NEXT:    mov w8, #43691
158; CHECK-NEXT:    sub w9, w0, #4
159; CHECK-NEXT:    movk w8, #43690, lsl #16
160; CHECK-NEXT:    mul w8, w9, w8
161; CHECK-NEXT:    mov w9, #43690
162; CHECK-NEXT:    movk w9, #10922, lsl #16
163; CHECK-NEXT:    ror w8, w8, #1
164; CHECK-NEXT:    cmp w8, w9
165; CHECK-NEXT:    cset w0, lo
166; CHECK-NEXT:    ret
167  %urem = urem i32 %X, 6
168  %cmp = icmp eq i32 %urem, 4
169  ret i1 %cmp
170}
171
172define i1 @t32_6_5(i32 %X) nounwind {
173; CHECK-LABEL: t32_6_5:
174; CHECK:       // %bb.0:
175; CHECK-NEXT:    mov w8, #43691
176; CHECK-NEXT:    sub w9, w0, #5
177; CHECK-NEXT:    movk w8, #43690, lsl #16
178; CHECK-NEXT:    mul w8, w9, w8
179; CHECK-NEXT:    mov w9, #43690
180; CHECK-NEXT:    movk w9, #10922, lsl #16
181; CHECK-NEXT:    ror w8, w8, #1
182; CHECK-NEXT:    cmp w8, w9
183; CHECK-NEXT:    cset w0, lo
184; CHECK-NEXT:    ret
185  %urem = urem i32 %X, 6
186  %cmp = icmp eq i32 %urem, 5
187  ret i1 %cmp
188}
189
190;-------------------------------------------------------------------------------
191; Other widths.
192
193define i1 @t16_3_2(i16 %X) nounwind {
194; CHECK-LABEL: t16_3_2:
195; CHECK:       // %bb.0:
196; CHECK-NEXT:    mov w8, #-21845
197; CHECK-NEXT:    mov w9, #-21846
198; CHECK-NEXT:    madd w8, w0, w8, w9
199; CHECK-NEXT:    mov w9, #21845
200; CHECK-NEXT:    cmp w9, w8, uxth
201; CHECK-NEXT:    cset w0, hi
202; CHECK-NEXT:    ret
203  %urem = urem i16 %X, 3
204  %cmp = icmp eq i16 %urem, 2
205  ret i1 %cmp
206}
207
208define i1 @t8_3_2(i8 %X) nounwind {
209; CHECK-LABEL: t8_3_2:
210; CHECK:       // %bb.0:
211; CHECK-NEXT:    mov w8, #-85
212; CHECK-NEXT:    mul w8, w0, w8
213; CHECK-NEXT:    sub w8, w8, #86
214; CHECK-NEXT:    and w8, w8, #0xff
215; CHECK-NEXT:    cmp w8, #85
216; CHECK-NEXT:    cset w0, lo
217; CHECK-NEXT:    ret
218  %urem = urem i8 %X, 3
219  %cmp = icmp eq i8 %urem, 2
220  ret i1 %cmp
221}
222
223define i1 @t64_3_2(i64 %X) nounwind {
224; CHECK-LABEL: t64_3_2:
225; CHECK:       // %bb.0:
226; CHECK-NEXT:    mov x8, #-6148914691236517206
227; CHECK-NEXT:    mov x9, #-6148914691236517206
228; CHECK-NEXT:    movk x8, #43691
229; CHECK-NEXT:    madd x8, x0, x8, x9
230; CHECK-NEXT:    mov x9, #6148914691236517205
231; CHECK-NEXT:    cmp x8, x9
232; CHECK-NEXT:    cset w0, lo
233; CHECK-NEXT:    ret
234  %urem = urem i64 %X, 3
235  %cmp = icmp eq i64 %urem, 2
236  ret i1 %cmp
237}
238