1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX6 %s
3# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX6 %s
4# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
5# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
6
7---
8name:            add_s32
9legalized:       true
10regBankSelected: true
11
12body: |
13  bb.0:
14    liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
15
16
17    ; GFX6-LABEL: name: add_s32
18    ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
19    ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
20    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
21    ; GFX6: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[COPY1]], implicit-def $scc
22    ; GFX6: %7:vgpr_32, dead %12:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY2]], [[S_ADD_I32_]], 0, implicit $exec
23    ; GFX6: %8:vgpr_32, dead %11:sreg_64_xexec = V_ADD_CO_U32_e64 [[S_ADD_I32_]], %7, 0, implicit $exec
24    ; GFX6: %9:vgpr_32, dead %10:sreg_64_xexec = V_ADD_CO_U32_e64 %8, [[COPY2]], 0, implicit $exec
25    ; GFX6: S_ENDPGM 0, implicit [[S_ADD_I32_]], implicit %7, implicit %8, implicit %9
26    ; GFX9-LABEL: name: add_s32
27    ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
28    ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
29    ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
30    ; GFX9: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[COPY1]], implicit-def $scc
31    ; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY2]], [[S_ADD_I32_]], 0, implicit $exec
32    ; GFX9: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_ADD_I32_]], [[V_ADD_U32_e64_]], 0, implicit $exec
33    ; GFX9: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_1]], [[COPY2]], 0, implicit $exec
34    ; GFX9: S_ENDPGM 0, implicit [[S_ADD_I32_]], implicit [[V_ADD_U32_e64_]], implicit [[V_ADD_U32_e64_1]], implicit [[V_ADD_U32_e64_2]]
35    %0:sgpr(s32) = COPY $sgpr0
36    %1:sgpr(s32) = COPY $sgpr1
37    %2:vgpr(s32) = COPY $vgpr0
38    %3:vgpr(p1) = COPY $vgpr3_vgpr4
39    %4:sgpr(s32) = G_CONSTANT i32 1
40    %5:sgpr(s32) = G_CONSTANT i32 4096
41
42    ; add ss
43    %6:sgpr(s32) = G_ADD %0, %1
44
45    ; add vs
46    %7:vgpr(s32) = G_ADD %2, %6
47
48    ; add sv
49    %8:vgpr(s32) = G_ADD %6, %7
50
51    ; add vv
52    %9:vgpr(s32) = G_ADD %8, %2
53
54    S_ENDPGM 0, implicit %6, implicit %7, implicit %8, implicit %9
55
56...
57
58---
59name:            add_neg_inline_const_64_to_sub_s32_s
60legalized:       true
61regBankSelected: true
62tracksRegLiveness: true
63
64body: |
65  bb.0:
66    liveins: $sgpr0
67
68    ; GFX6-LABEL: name: add_neg_inline_const_64_to_sub_s32_s
69    ; GFX6: liveins: $sgpr0
70    ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
71    ; GFX6: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], 64, implicit-def $scc
72    ; GFX6: S_ENDPGM 0, implicit [[S_SUB_I32_]]
73    ; GFX9-LABEL: name: add_neg_inline_const_64_to_sub_s32_s
74    ; GFX9: liveins: $sgpr0
75    ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
76    ; GFX9: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], 64, implicit-def $scc
77    ; GFX9: S_ENDPGM 0, implicit [[S_SUB_I32_]]
78    %0:sgpr(s32) = COPY $sgpr0
79    %1:sgpr(s32) = G_CONSTANT i32 -64
80    %2:sgpr(s32) = G_ADD %0, %1
81    S_ENDPGM 0, implicit %2
82
83...
84
85---
86name:            add_neg_inline_const_64_to_sub_s32_v
87legalized:       true
88regBankSelected: true
89tracksRegLiveness: true
90
91body: |
92  bb.0:
93    liveins: $vgpr0
94
95    ; GFX6-LABEL: name: add_neg_inline_const_64_to_sub_s32_v
96    ; GFX6: liveins: $vgpr0
97    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
98    ; GFX6: %2:vgpr_32, dead %3:sreg_64 = V_SUB_CO_U32_e64 [[COPY]], 64, 0, implicit $exec
99    ; GFX6: S_ENDPGM 0, implicit %2
100    ; GFX9-LABEL: name: add_neg_inline_const_64_to_sub_s32_v
101    ; GFX9: liveins: $vgpr0
102    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
103    ; GFX9: [[V_SUB_U32_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[COPY]], 64, 0, implicit $exec
104    ; GFX9: S_ENDPGM 0, implicit [[V_SUB_U32_e64_]]
105    %0:vgpr(s32) = COPY $vgpr0
106    %1:vgpr(s32) = G_CONSTANT i32 -64
107    %2:vgpr(s32) = G_ADD %0, %1
108    S_ENDPGM 0, implicit %2
109
110...
111
112---
113name:            add_neg_inline_const_16_to_sub_s32_s
114legalized:       true
115regBankSelected: true
116tracksRegLiveness: true
117
118body: |
119  bb.0:
120    liveins: $sgpr0
121
122    ; GFX6-LABEL: name: add_neg_inline_const_16_to_sub_s32_s
123    ; GFX6: liveins: $sgpr0
124    ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
125    ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
126    ; GFX6: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
127    ; GFX6: S_ENDPGM 0, implicit [[S_ADD_I32_]]
128    ; GFX9-LABEL: name: add_neg_inline_const_16_to_sub_s32_s
129    ; GFX9: liveins: $sgpr0
130    ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
131    ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
132    ; GFX9: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
133    ; GFX9: S_ENDPGM 0, implicit [[S_ADD_I32_]]
134    %0:sgpr(s32) = COPY $sgpr0
135    %1:sgpr(s32) = G_CONSTANT i32 16
136    %2:sgpr(s32) = G_ADD %0, %1
137    S_ENDPGM 0, implicit %2
138
139...
140
141---
142name:            add_neg_inline_const_16_to_sub_s32_v
143legalized:       true
144regBankSelected: true
145tracksRegLiveness: true
146
147body: |
148  bb.0:
149    liveins: $vgpr0
150
151    ; GFX6-LABEL: name: add_neg_inline_const_16_to_sub_s32_v
152    ; GFX6: liveins: $vgpr0
153    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
154    ; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 16, implicit $exec
155    ; GFX6: %2:vgpr_32, dead %3:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
156    ; GFX6: S_ENDPGM 0, implicit %2
157    ; GFX9-LABEL: name: add_neg_inline_const_16_to_sub_s32_v
158    ; GFX9: liveins: $vgpr0
159    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
160    ; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 16, implicit $exec
161    ; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
162    ; GFX9: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]]
163    %0:vgpr(s32) = COPY $vgpr0
164    %1:vgpr(s32) = G_CONSTANT i32 16
165    %2:vgpr(s32) = G_ADD %0, %1
166    S_ENDPGM 0, implicit %2
167
168...
169