1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s 3 4--- 5name: bitreverse_i32_ss 6legalized: true 7regBankSelected: true 8 9body: | 10 bb.0: 11 liveins: $sgpr0 12 ; CHECK-LABEL: name: bitreverse_i32_ss 13 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 14 ; CHECK: [[S_BREV_B32_:%[0-9]+]]:sreg_32 = S_BREV_B32 [[COPY]] 15 ; CHECK: S_ENDPGM 0, implicit [[S_BREV_B32_]] 16 %0:sgpr(s32) = COPY $sgpr0 17 %1:sgpr(s32) = G_BITREVERSE %0 18 S_ENDPGM 0, implicit %1 19... 20 21--- 22name: bitreverse_i32_vv 23legalized: true 24regBankSelected: true 25 26body: | 27 bb.0: 28 liveins: $vgpr0 29 ; CHECK-LABEL: name: bitreverse_i32_vv 30 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 31 ; CHECK: [[V_BFREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY]], implicit $exec 32 ; CHECK: S_ENDPGM 0, implicit [[V_BFREV_B32_e64_]] 33 %0:vgpr(s32) = COPY $vgpr0 34 %1:vgpr(s32) = G_BITREVERSE %0 35 S_ENDPGM 0, implicit %1 36... 37 38--- 39name: bitreverse_i32_vs 40legalized: true 41regBankSelected: true 42 43body: | 44 bb.0: 45 liveins: $sgpr0 46 ; CHECK-LABEL: name: bitreverse_i32_vs 47 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 48 ; CHECK: [[V_BFREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY]], implicit $exec 49 ; CHECK: S_ENDPGM 0, implicit [[V_BFREV_B32_e64_]] 50 %0:sgpr(s32) = COPY $sgpr0 51 %1:vgpr(s32) = G_BITREVERSE %0 52 S_ENDPGM 0, implicit %1 53... 54 55--- 56name: bitreverse_i64_ss 57legalized: true 58regBankSelected: true 59 60body: | 61 bb.0: 62 liveins: $sgpr0_sgpr1 63 ; CHECK-LABEL: name: bitreverse_i64_ss 64 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 65 ; CHECK: [[S_BREV_B64_:%[0-9]+]]:sreg_64 = S_BREV_B64 [[COPY]] 66 ; CHECK: S_ENDPGM 0, implicit [[S_BREV_B64_]] 67 %0:sgpr(s64) = COPY $sgpr0_sgpr1 68 %1:sgpr(s64) = G_BITREVERSE %0 69 S_ENDPGM 0, implicit %1 70... 71 72--- 73name: bitreverse_i64_vv 74legalized: true 75regBankSelected: true 76 77body: | 78 bb.0: 79 liveins: $vgpr0_vgpr1 80 ; CHECK-LABEL: name: bitreverse_i64_vv 81 ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 82 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 83 ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 84 ; CHECK: [[V_BFREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY2]], implicit $exec 85 ; CHECK: [[V_BFREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY1]], implicit $exec 86 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_BFREV_B32_e64_]], %subreg.sub0, [[V_BFREV_B32_e64_1]], %subreg.sub1 87 ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 88 %0:vgpr(s64) = COPY $vgpr0_vgpr1 89 %2:vgpr(s32), %3:vgpr(s32) = G_UNMERGE_VALUES %0(s64) 90 %4:vgpr(s32) = G_BITREVERSE %3 91 %5:vgpr(s32) = G_BITREVERSE %2 92 %1:vgpr(s64) = G_MERGE_VALUES %4(s32), %5(s32) 93 S_ENDPGM 0, implicit %1 94... 95 96--- 97name: bitreverse_i64_vs 98legalized: true 99regBankSelected: true 100 101body: | 102 bb.0: 103 liveins: $sgpr0_sgpr1 104 ; CHECK-LABEL: name: bitreverse_i64_vs 105 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 106 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0 107 ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1 108 ; CHECK: [[V_BFREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY2]], implicit $exec 109 ; CHECK: [[V_BFREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY1]], implicit $exec 110 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_BFREV_B32_e64_]], %subreg.sub0, [[V_BFREV_B32_e64_1]], %subreg.sub1 111 ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 112 %0:sgpr(s64) = COPY $sgpr0_sgpr1 113 %2:sgpr(s32), %3:sgpr(s32) = G_UNMERGE_VALUES %0(s64) 114 %4:vgpr(s32) = G_BITREVERSE %3 115 %5:vgpr(s32) = G_BITREVERSE %2 116 %1:vgpr(s64) = G_MERGE_VALUES %4(s32), %5(s32) 117 S_ENDPGM 0, implicit %1 118... 119