1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=MOVREL %s 3# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GPRIDX %s 4# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=MOVREL %s 5 6--- 7name: insert_vector_elt_s_s32_v2s32 8legalized: true 9regBankSelected: true 10 11body: | 12 bb.0: 13 liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3 14 15 ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v2s32 16 ; MOVREL: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 17 ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 18 ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 19 ; MOVREL: $m0 = COPY [[COPY2]] 20 ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V2_:%[0-9]+]]:sreg_64 = S_INDIRECT_REG_WRITE_MOVREL_B32_V2 [[COPY]], [[COPY1]], 3, implicit $m0 21 ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V2_]] 22 ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v2s32 23 ; GPRIDX: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 24 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 25 ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 26 ; GPRIDX: $m0 = COPY [[COPY2]] 27 ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V2_:%[0-9]+]]:sreg_64 = S_INDIRECT_REG_WRITE_MOVREL_B32_V2 [[COPY]], [[COPY1]], 3, implicit $m0 28 ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V2_]] 29 %0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1 30 %1:sgpr(s32) = COPY $sgpr2 31 %2:sgpr(s32) = COPY $sgpr3 32 %3:sgpr(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2 33 S_ENDPGM 0, implicit %3 34... 35 36--- 37name: insert_vector_elt_s_s32_v3s32 38legalized: true 39regBankSelected: true 40 41body: | 42 bb.0: 43 liveins: $sgpr0_sgpr1_sgpr2, $sgpr3, $sgpr4 44 45 ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v3s32 46 ; MOVREL: [[COPY:%[0-9]+]]:sgpr_96 = COPY $sgpr0_sgpr1_sgpr2 47 ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 48 ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 49 ; MOVREL: $m0 = COPY [[COPY2]] 50 ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V3_:%[0-9]+]]:sgpr_96 = S_INDIRECT_REG_WRITE_MOVREL_B32_V3 [[COPY]], [[COPY1]], 3, implicit $m0 51 ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V3_]] 52 ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v3s32 53 ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_96 = COPY $sgpr0_sgpr1_sgpr2 54 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 55 ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 56 ; GPRIDX: $m0 = COPY [[COPY2]] 57 ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V3_:%[0-9]+]]:sgpr_96 = S_INDIRECT_REG_WRITE_MOVREL_B32_V3 [[COPY]], [[COPY1]], 3, implicit $m0 58 ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V3_]] 59 %0:sgpr(<3 x s32>) = COPY $sgpr0_sgpr1_sgpr2 60 %1:sgpr(s32) = COPY $sgpr3 61 %2:sgpr(s32) = COPY $sgpr4 62 %3:sgpr(<3 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2 63 S_ENDPGM 0, implicit %3 64... 65 66--- 67name: insert_vector_elt_s_s32_v4s32 68legalized: true 69regBankSelected: true 70 71body: | 72 bb.0: 73 liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, $sgpr5 74 75 ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v4s32 76 ; MOVREL: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 77 ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 78 ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 79 ; MOVREL: $m0 = COPY [[COPY2]] 80 ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_MOVREL_B32_V4 [[COPY]], [[COPY1]], 3, implicit $m0 81 ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_]] 82 ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v4s32 83 ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 84 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 85 ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 86 ; GPRIDX: $m0 = COPY [[COPY2]] 87 ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_MOVREL_B32_V4 [[COPY]], [[COPY1]], 3, implicit $m0 88 ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_]] 89 %0:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 90 %1:sgpr(s32) = COPY $sgpr3 91 %2:sgpr(s32) = COPY $sgpr4 92 %3:sgpr(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2 93 S_ENDPGM 0, implicit %3 94... 95 96--- 97name: insert_vector_elt_s_s32_v5s32 98legalized: true 99regBankSelected: true 100 101body: | 102 bb.0: 103 liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4, $sgpr5, $sgpr6 104 105 ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v5s32 106 ; MOVREL: [[COPY:%[0-9]+]]:sgpr_160 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4 107 ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5 108 ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6 109 ; MOVREL: $m0 = COPY [[COPY2]] 110 ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V5_:%[0-9]+]]:sgpr_160 = S_INDIRECT_REG_WRITE_MOVREL_B32_V5 [[COPY]], [[COPY1]], 3, implicit $m0 111 ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V5_]] 112 ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v5s32 113 ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_160 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4 114 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5 115 ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6 116 ; GPRIDX: $m0 = COPY [[COPY2]] 117 ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V5_:%[0-9]+]]:sgpr_160 = S_INDIRECT_REG_WRITE_MOVREL_B32_V5 [[COPY]], [[COPY1]], 3, implicit $m0 118 ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V5_]] 119 %0:sgpr(<5 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4 120 %1:sgpr(s32) = COPY $sgpr5 121 %2:sgpr(s32) = COPY $sgpr6 122 %3:sgpr(<5 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2 123 S_ENDPGM 0, implicit %3 124... 125 126--- 127name: insert_vector_elt_s_s32_v8s32 128legalized: true 129regBankSelected: true 130 131body: | 132 bb.0: 133 liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8, $sgpr9 134 135 ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v8s32 136 ; MOVREL: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 137 ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 138 ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9 139 ; MOVREL: $m0 = COPY [[COPY2]] 140 ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 3, implicit $m0 141 ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_]] 142 ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v8s32 143 ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 144 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 145 ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9 146 ; GPRIDX: $m0 = COPY [[COPY2]] 147 ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 3, implicit $m0 148 ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_]] 149 %0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 150 %1:sgpr(s32) = COPY $sgpr8 151 %2:sgpr(s32) = COPY $sgpr9 152 %3:sgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2 153 S_ENDPGM 0, implicit %3 154... 155 156--- 157name: insert_vector_elt_s_s32_v16s32 158legalized: true 159regBankSelected: true 160 161body: | 162 bb.0: 163 liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15, $sgpr16, $sgpr17 164 165 ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v16s32 166 ; MOVREL: [[COPY:%[0-9]+]]:sgpr_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 167 ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr16 168 ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr17 169 ; MOVREL: $m0 = COPY [[COPY2]] 170 ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V16_:%[0-9]+]]:sgpr_512 = S_INDIRECT_REG_WRITE_MOVREL_B32_V16 [[COPY]], [[COPY1]], 3, implicit $m0 171 ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V16_]] 172 ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v16s32 173 ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 174 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr16 175 ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr17 176 ; GPRIDX: $m0 = COPY [[COPY2]] 177 ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V16_:%[0-9]+]]:sgpr_512 = S_INDIRECT_REG_WRITE_MOVREL_B32_V16 [[COPY]], [[COPY1]], 3, implicit $m0 178 ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V16_]] 179 %0:sgpr(<16 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 180 %1:sgpr(s32) = COPY $sgpr16 181 %2:sgpr(s32) = COPY $sgpr17 182 %3:sgpr(<16 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2 183 S_ENDPGM 0, implicit %3 184... 185 186--- 187name: extract_vector_elt_s_s32_v32s32 188legalized: true 189regBankSelected: true 190 191body: | 192 bb.0: 193 liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, $sgpr40, $sgpr41 194 195 ; MOVREL-LABEL: name: extract_vector_elt_s_s32_v32s32 196 ; MOVREL: [[COPY:%[0-9]+]]:sgpr_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31 197 ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr40 198 ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr41 199 ; MOVREL: $m0 = COPY [[COPY2]] 200 ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V32_:%[0-9]+]]:sgpr_1024 = S_INDIRECT_REG_WRITE_MOVREL_B32_V32 [[COPY]], [[COPY1]], 3, implicit $m0 201 ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V32_]] 202 ; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v32s32 203 ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31 204 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr40 205 ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr41 206 ; GPRIDX: $m0 = COPY [[COPY2]] 207 ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V32_:%[0-9]+]]:sgpr_1024 = S_INDIRECT_REG_WRITE_MOVREL_B32_V32 [[COPY]], [[COPY1]], 3, implicit $m0 208 ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V32_]] 209 %0:sgpr(<32 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31 210 %1:sgpr(s32) = COPY $sgpr40 211 %2:sgpr(s32) = COPY $sgpr41 212 %3:sgpr(<32 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2 213 S_ENDPGM 0, implicit %3 214... 215 216--- 217name: insert_vector_elt_s_s64_v2s64 218legalized: true 219regBankSelected: true 220 221body: | 222 bb.0: 223 liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5, $sgpr6 224 225 ; MOVREL-LABEL: name: insert_vector_elt_s_s64_v2s64 226 ; MOVREL: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 227 ; MOVREL: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5 228 ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6 229 ; MOVREL: $m0 = COPY [[COPY2]] 230 ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V2_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_MOVREL_B64_V2 [[COPY]], [[COPY1]], 4, implicit $m0 231 ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V2_]] 232 ; GPRIDX-LABEL: name: insert_vector_elt_s_s64_v2s64 233 ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 234 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5 235 ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6 236 ; GPRIDX: $m0 = COPY [[COPY2]] 237 ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V2_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_MOVREL_B64_V2 [[COPY]], [[COPY1]], 4, implicit $m0 238 ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V2_]] 239 %0:sgpr(<2 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 240 %1:sgpr(s64) = COPY $sgpr4_sgpr5 241 %2:sgpr(s32) = COPY $sgpr6 242 %3:sgpr(<2 x s64>) = G_INSERT_VECTOR_ELT %0, %1, %2 243 S_ENDPGM 0, implicit %3 244... 245 246--- 247name: insert_vector_elt_s_s64_v4s64 248legalized: true 249regBankSelected: true 250 251body: | 252 bb.0: 253 liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10 254 255 ; MOVREL-LABEL: name: insert_vector_elt_s_s64_v4s64 256 ; MOVREL: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 257 ; MOVREL: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr8_sgpr9 258 ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr10 259 ; MOVREL: $m0 = COPY [[COPY2]] 260 ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V4_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B64_V4 [[COPY]], [[COPY1]], 4, implicit $m0 261 ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V4_]] 262 ; GPRIDX-LABEL: name: insert_vector_elt_s_s64_v4s64 263 ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 264 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr8_sgpr9 265 ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr10 266 ; GPRIDX: $m0 = COPY [[COPY2]] 267 ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V4_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B64_V4 [[COPY]], [[COPY1]], 4, implicit $m0 268 ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V4_]] 269 %0:sgpr(<4 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 270 %1:sgpr(s64) = COPY $sgpr8_sgpr9 271 %2:sgpr(s32) = COPY $sgpr10 272 %3:sgpr(<4 x s64>) = G_INSERT_VECTOR_ELT %0, %1, %2 273 S_ENDPGM 0, implicit %3 274... 275 276--- 277name: insert_vector_elt_s_s64_v8s64 278legalized: true 279regBankSelected: true 280 281body: | 282 bb.0: 283 liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18 284 285 ; MOVREL-LABEL: name: insert_vector_elt_s_s64_v8s64 286 ; MOVREL: [[COPY:%[0-9]+]]:sgpr_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 287 ; MOVREL: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr16_sgpr17 288 ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr18 289 ; MOVREL: $m0 = COPY [[COPY2]] 290 ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V8_:%[0-9]+]]:sgpr_512 = S_INDIRECT_REG_WRITE_MOVREL_B64_V8 [[COPY]], [[COPY1]], 4, implicit $m0 291 ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V8_]] 292 ; GPRIDX-LABEL: name: insert_vector_elt_s_s64_v8s64 293 ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 294 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr16_sgpr17 295 ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr18 296 ; GPRIDX: $m0 = COPY [[COPY2]] 297 ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V8_:%[0-9]+]]:sgpr_512 = S_INDIRECT_REG_WRITE_MOVREL_B64_V8 [[COPY]], [[COPY1]], 4, implicit $m0 298 ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V8_]] 299 %0:sgpr(<8 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 300 %1:sgpr(s64) = COPY $sgpr16_sgpr17 301 %2:sgpr(s32) = COPY $sgpr18 302 %3:sgpr(<8 x s64>) = G_INSERT_VECTOR_ELT %0, %1, %2 303 S_ENDPGM 0, implicit %3 304... 305 306--- 307name: extract_vector_elt_s_s64_v16s64 308legalized: true 309regBankSelected: true 310 311body: | 312 bb.0: 313 liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, $sgpr40_sgpr41, $sgpr42 314 315 ; MOVREL-LABEL: name: extract_vector_elt_s_s64_v16s64 316 ; MOVREL: [[COPY:%[0-9]+]]:sgpr_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31 317 ; MOVREL: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr40_sgpr41 318 ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr42 319 ; MOVREL: $m0 = COPY [[COPY2]] 320 ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V16_:%[0-9]+]]:sgpr_1024 = S_INDIRECT_REG_WRITE_MOVREL_B64_V16 [[COPY]], [[COPY1]], 4, implicit $m0 321 ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V16_]] 322 ; GPRIDX-LABEL: name: extract_vector_elt_s_s64_v16s64 323 ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31 324 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr40_sgpr41 325 ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr42 326 ; GPRIDX: $m0 = COPY [[COPY2]] 327 ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V16_:%[0-9]+]]:sgpr_1024 = S_INDIRECT_REG_WRITE_MOVREL_B64_V16 [[COPY]], [[COPY1]], 4, implicit $m0 328 ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V16_]] 329 %0:sgpr(<16 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31 330 %1:sgpr(s64) = COPY $sgpr40_sgpr41 331 %2:sgpr(s32) = COPY $sgpr42 332 %3:sgpr(<16 x s64>) = G_INSERT_VECTOR_ELT %0, %1, %2 333 S_ENDPGM 0, implicit %3 334... 335 336--- 337name: insert_vector_elt_vvs_s32_v2s32 338legalized: true 339regBankSelected: true 340 341body: | 342 bb.0: 343 liveins: $vgpr0_vgpr1, $vgpr2, $sgpr3 344 345 ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v2s32 346 ; MOVREL: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 347 ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2 348 ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 349 ; MOVREL: $m0 = COPY [[COPY2]] 350 ; MOVREL: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V2_:%[0-9]+]]:vreg_64 = V_INDIRECT_REG_WRITE_MOVREL_B32_V2 [[COPY]], [[COPY1]], 3, implicit $m0, implicit $exec 351 ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V2_]] 352 ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v2s32 353 ; GPRIDX: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 354 ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2 355 ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 356 ; GPRIDX: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V2_:%[0-9]+]]:vreg_64 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V2 [[COPY]], [[COPY1]], [[COPY2]], 3, implicit-def $m0, implicit $m0, implicit $exec 357 ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V2_]] 358 %0:vgpr(<2 x s32>) = COPY $vgpr0_vgpr1 359 %1:vgpr(s32) = COPY $vgpr2 360 %2:sgpr(s32) = COPY $sgpr3 361 %3:vgpr(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2 362 S_ENDPGM 0, implicit %3 363... 364 365--- 366name: insert_vector_elt_vvs_s32_v3s32 367legalized: true 368regBankSelected: true 369 370body: | 371 bb.0: 372 liveins: $vgpr0_vgpr1_vgpr2, $vgpr3, $sgpr4 373 374 ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v3s32 375 ; MOVREL: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2 376 ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3 377 ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 378 ; MOVREL: $m0 = COPY [[COPY2]] 379 ; MOVREL: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V3_:%[0-9]+]]:vreg_96 = V_INDIRECT_REG_WRITE_MOVREL_B32_V3 [[COPY]], [[COPY1]], 3, implicit $m0, implicit $exec 380 ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V3_]] 381 ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v3s32 382 ; GPRIDX: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2 383 ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3 384 ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 385 ; GPRIDX: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V3_:%[0-9]+]]:vreg_96 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V3 [[COPY]], [[COPY1]], [[COPY2]], 3, implicit-def $m0, implicit $m0, implicit $exec 386 ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V3_]] 387 %0:vgpr(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 388 %1:vgpr(s32) = COPY $vgpr3 389 %2:sgpr(s32) = COPY $sgpr4 390 %3:vgpr(<3 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2 391 S_ENDPGM 0, implicit %3 392... 393 394--- 395name: insert_vector_elt_vvs_s32_v4s32 396legalized: true 397regBankSelected: true 398 399body: | 400 bb.0: 401 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4, $vgpr5 402 403 ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v4s32 404 ; MOVREL: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3 405 ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3 406 ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 407 ; MOVREL: $m0 = COPY [[COPY2]] 408 ; MOVREL: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V4_:%[0-9]+]]:vreg_128 = V_INDIRECT_REG_WRITE_MOVREL_B32_V4 [[COPY]], [[COPY1]], 3, implicit $m0, implicit $exec 409 ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V4_]] 410 ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v4s32 411 ; GPRIDX: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3 412 ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3 413 ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 414 ; GPRIDX: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4_:%[0-9]+]]:vreg_128 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4 [[COPY]], [[COPY1]], [[COPY2]], 3, implicit-def $m0, implicit $m0, implicit $exec 415 ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4_]] 416 %0:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 417 %1:vgpr(s32) = COPY $vgpr3 418 %2:sgpr(s32) = COPY $sgpr4 419 %3:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2 420 S_ENDPGM 0, implicit %3 421... 422 423--- 424name: insert_vector_elt_vvs_s32_v5s32 425legalized: true 426regBankSelected: true 427 428body: | 429 bb.0: 430 liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5, $sgpr6 431 432 ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v5s32 433 ; MOVREL: [[COPY:%[0-9]+]]:vreg_160 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 434 ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr5 435 ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6 436 ; MOVREL: $m0 = COPY [[COPY2]] 437 ; MOVREL: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V5_:%[0-9]+]]:vreg_160 = V_INDIRECT_REG_WRITE_MOVREL_B32_V5 [[COPY]], [[COPY1]], 3, implicit $m0, implicit $exec 438 ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V5_]] 439 ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v5s32 440 ; GPRIDX: [[COPY:%[0-9]+]]:vreg_160 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 441 ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr5 442 ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6 443 ; GPRIDX: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V5_:%[0-9]+]]:vreg_160 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V5 [[COPY]], [[COPY1]], [[COPY2]], 3, implicit-def $m0, implicit $m0, implicit $exec 444 ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V5_]] 445 %0:vgpr(<5 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 446 %1:vgpr(s32) = COPY $vgpr5 447 %2:sgpr(s32) = COPY $sgpr6 448 %3:vgpr(<5 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2 449 S_ENDPGM 0, implicit %3 450... 451 452--- 453name: insert_vector_elt_vvs_s32_v8s32 454legalized: true 455regBankSelected: true 456 457body: | 458 bb.0: 459 liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8, $sgpr9 460 461 ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v8s32 462 ; MOVREL: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 463 ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8 464 ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9 465 ; MOVREL: $m0 = COPY [[COPY2]] 466 ; MOVREL: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 3, implicit $m0, implicit $exec 467 ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V8_]] 468 ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v8s32 469 ; GPRIDX: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 470 ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8 471 ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9 472 ; GPRIDX: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8 [[COPY]], [[COPY1]], [[COPY2]], 3, implicit-def $m0, implicit $m0, implicit $exec 473 ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8_]] 474 %0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 475 %1:vgpr(s32) = COPY $vgpr8 476 %2:sgpr(s32) = COPY $sgpr9 477 %3:vgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2 478 S_ENDPGM 0, implicit %3 479... 480 481--- 482name: insert_vector_elt_vvs_s32_v8s32_add_1 483legalized: true 484regBankSelected: true 485 486body: | 487 bb.0: 488 liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8, $sgpr9 489 490 ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v8s32_add_1 491 ; MOVREL: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 492 ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8 493 ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9 494 ; MOVREL: $m0 = COPY [[COPY2]] 495 ; MOVREL: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 11, implicit $m0, implicit $exec 496 ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V8_]] 497 ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v8s32_add_1 498 ; GPRIDX: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 499 ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8 500 ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9 501 ; GPRIDX: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8 [[COPY]], [[COPY1]], [[COPY2]], 11, implicit-def $m0, implicit $m0, implicit $exec 502 ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8_]] 503 %0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 504 %1:vgpr(s32) = COPY $vgpr8 505 %2:sgpr(s32) = COPY $sgpr9 506 %3:sgpr(s32) = G_CONSTANT i32 1 507 %4:sgpr(s32) = G_ADD %2, %3 508 %5:vgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4 509 S_ENDPGM 0, implicit %5 510... 511 512--- 513name: insert_vector_elt_vvs_s32_v8s32_add_8 514legalized: true 515regBankSelected: true 516 517body: | 518 bb.0: 519 liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8, $sgpr9 520 521 ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v8s32_add_8 522 ; MOVREL: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 523 ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8 524 ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9 525 ; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8 526 ; MOVREL: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc 527 ; MOVREL: $m0 = COPY [[S_ADD_I32_]] 528 ; MOVREL: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 3, implicit $m0, implicit $exec 529 ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V8_]] 530 ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v8s32_add_8 531 ; GPRIDX: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 532 ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8 533 ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9 534 ; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8 535 ; GPRIDX: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc 536 ; GPRIDX: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8 [[COPY]], [[COPY1]], [[S_ADD_I32_]], 3, implicit-def $m0, implicit $m0, implicit $exec 537 ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8_]] 538 %0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 539 %1:vgpr(s32) = COPY $vgpr8 540 %2:sgpr(s32) = COPY $sgpr9 541 %3:sgpr(s32) = G_CONSTANT i32 8 542 %4:sgpr(s32) = G_ADD %2, %3 543 %5:vgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4 544 S_ENDPGM 0, implicit %5 545... 546 547--- 548name: insert_vector_elt_s_s32_v8s32_add_1 549legalized: true 550regBankSelected: true 551 552body: | 553 bb.0: 554 liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8, $sgpr9 555 556 ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v8s32_add_1 557 ; MOVREL: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 558 ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 559 ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9 560 ; MOVREL: $m0 = COPY [[COPY2]] 561 ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 11, implicit $m0 562 ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_]] 563 ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v8s32_add_1 564 ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 565 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 566 ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9 567 ; GPRIDX: $m0 = COPY [[COPY2]] 568 ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 11, implicit $m0 569 ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_]] 570 %0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 571 %1:sgpr(s32) = COPY $sgpr8 572 %2:sgpr(s32) = COPY $sgpr9 573 %3:sgpr(s32) = G_CONSTANT i32 1 574 %4:sgpr(s32) = G_ADD %2, %3 575 %5:sgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4 576 S_ENDPGM 0, implicit %5 577... 578 579--- 580name: insert_vector_elt_s_s32_v8s32_add_8 581legalized: true 582regBankSelected: true 583 584body: | 585 bb.0: 586 liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8, $sgpr9 587 588 ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v8s32_add_8 589 ; MOVREL: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 590 ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 591 ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9 592 ; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8 593 ; MOVREL: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc 594 ; MOVREL: $m0 = COPY [[S_ADD_I32_]] 595 ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 3, implicit $m0 596 ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_]] 597 ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v8s32_add_8 598 ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 599 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 600 ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9 601 ; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8 602 ; GPRIDX: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc 603 ; GPRIDX: $m0 = COPY [[S_ADD_I32_]] 604 ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 3, implicit $m0 605 ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_]] 606 %0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 607 %1:sgpr(s32) = COPY $sgpr8 608 %2:sgpr(s32) = COPY $sgpr9 609 %3:sgpr(s32) = G_CONSTANT i32 8 610 %4:sgpr(s32) = G_ADD %2, %3 611 %5:sgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4 612 S_ENDPGM 0, implicit %5 613... 614 615# This should have been folded out in the legalizer, but make sure it 616# doesn't crash. 617--- 618name: insert_vector_elt_s_s32_v4s32_const_idx 619legalized: true 620regBankSelected: true 621 622body: | 623 bb.0: 624 liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4 625 626 ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v4s32_const_idx 627 ; MOVREL: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 628 ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4 629 ; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 630 ; MOVREL: $m0 = COPY [[S_MOV_B32_]] 631 ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_MOVREL_B32_V4 [[COPY]], [[COPY1]], 3, implicit $m0 632 ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_]] 633 ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v4s32_const_idx 634 ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 635 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4 636 ; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 637 ; GPRIDX: $m0 = COPY [[S_MOV_B32_]] 638 ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_MOVREL_B32_V4 [[COPY]], [[COPY1]], 3, implicit $m0 639 ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_]] 640 %0:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 641 %1:sgpr(s32) = COPY $sgpr4 642 %2:sgpr(s32) = G_CONSTANT i32 0 643 %3:sgpr(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2 644 S_ENDPGM 0, implicit %3 645... 646 647--- 648name: insert_vector_elt_v_s32_v4s32_const_idx 649legalized: true 650regBankSelected: true 651 652body: | 653 bb.0: 654 liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4 655 656 ; MOVREL-LABEL: name: insert_vector_elt_v_s32_v4s32_const_idx 657 ; MOVREL: [[COPY:%[0-9]+]]:vreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 658 ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4 659 ; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 660 ; MOVREL: $m0 = COPY [[S_MOV_B32_]] 661 ; MOVREL: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V4_:%[0-9]+]]:vreg_128 = V_INDIRECT_REG_WRITE_MOVREL_B32_V4 [[COPY]], [[COPY1]], 3, implicit $m0, implicit $exec 662 ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V4_]] 663 ; GPRIDX-LABEL: name: insert_vector_elt_v_s32_v4s32_const_idx 664 ; GPRIDX: [[COPY:%[0-9]+]]:vreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 665 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4 666 ; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 667 ; GPRIDX: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4_:%[0-9]+]]:vreg_128 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4 [[COPY]], [[COPY1]], [[S_MOV_B32_]], 3, implicit-def $m0, implicit $m0, implicit $exec 668 ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4_]] 669 %0:vgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 670 %1:sgpr(s32) = COPY $sgpr4 671 %2:sgpr(s32) = G_CONSTANT i32 0 672 %3:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2 673 S_ENDPGM 0, implicit %3 674... 675