1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
3
4# The only instruction selection cases for G_SBFX/G_UBFX are the 64-bit
5# vector versions. All other versions, scalar and 32-bit vector, are
6# expanded during register bank selection.
7
8---
9name:            sbfx_s32_vii
10legalized:       true
11regBankSelected: true
12tracksRegLiveness: true
13body:             |
14  bb.0:
15    liveins: $vgpr0
16    ; CHECK-LABEL: name: sbfx_s32_vii
17    ; CHECK: liveins: $vgpr0
18    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
19    ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
20    ; CHECK: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 10, implicit $exec
21    ; CHECK: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[COPY]], [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], implicit $exec
22    ; CHECK: S_ENDPGM 0, implicit [[V_BFE_I32_e64_]]
23    %0:vgpr(s32) = COPY $vgpr0
24    %1:vgpr(s32) = G_CONSTANT i32 2
25    %2:vgpr(s32) = G_CONSTANT i32 10
26    %3:vgpr(s32) = G_SBFX %0, %1(s32), %2
27    S_ENDPGM 0, implicit %3
28...
29
30---
31name:            sbfx_s32_vvv
32legalized:       true
33regBankSelected: true
34tracksRegLiveness: true
35body:             |
36  bb.0:
37    liveins: $vgpr0, $vgpr1, $vgpr2
38    ; CHECK-LABEL: name: sbfx_s32_vvv
39    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
40    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
41    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
42    ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
43    ; CHECK: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
44    ; CHECK: S_ENDPGM 0, implicit [[V_BFE_I32_e64_]]
45    %0:vgpr(s32) = COPY $vgpr0
46    %1:vgpr(s32) = COPY $vgpr1
47    %2:vgpr(s32) = COPY $vgpr2
48    %3:vgpr(s32) = G_SBFX %0, %1(s32), %2
49    S_ENDPGM 0, implicit %3
50...
51