1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s  | FileCheck -check-prefix=WAVE64 %s
3# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s  | FileCheck -check-prefix=WAVE64 %s
4# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr="+wavefrontsize32" -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s  | FileCheck -check-prefix=WAVE32 %s
5
6---
7
8name:            xor_s1_vcc_vcc_vcc
9legalized:       true
10regBankSelected: true
11tracksRegLiveness: true
12
13body: |
14  bb.0:
15    liveins: $vgpr0, $vgpr1
16    ; WAVE64-LABEL: name: xor_s1_vcc_vcc_vcc
17    ; WAVE64: liveins: $vgpr0, $vgpr1
18    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
19    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
20    ; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
21    ; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
22    ; WAVE64: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
23    ; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc
24    ; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B64_]]
25    ; WAVE32-LABEL: name: xor_s1_vcc_vcc_vcc
26    ; WAVE32: liveins: $vgpr0, $vgpr1
27    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
28    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
29    ; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
30    ; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
31    ; WAVE32: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
32    ; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc
33    ; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]
34    %0:vgpr(s32) = COPY $vgpr0
35    %1:vgpr(s32) = COPY $vgpr1
36    %2:vgpr(s32) = G_CONSTANT i32 0
37    %3:vcc(s1) = G_ICMP intpred(eq), %0, %2
38    %4:vcc(s1) = G_ICMP intpred(eq), %1, %2
39    %5:vcc(s1) = G_XOR %3, %4
40    S_ENDPGM 0, implicit %5
41...
42
43# Should fail to select
44
45---
46
47name:            xor_s1_sgpr_sgpr_sgpr
48legalized:       true
49regBankSelected: true
50tracksRegLiveness: true
51
52body: |
53  bb.0:
54    liveins: $sgpr0, $sgpr1
55    ; WAVE64-LABEL: name: xor_s1_sgpr_sgpr_sgpr
56    ; WAVE64: liveins: $sgpr0, $sgpr1
57    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
58    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
59    ; WAVE64: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
60    ; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B32_]]
61    ; WAVE32-LABEL: name: xor_s1_sgpr_sgpr_sgpr
62    ; WAVE32: liveins: $sgpr0, $sgpr1
63    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
64    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
65    ; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
66    ; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]
67    %0:sgpr(s32) = COPY $sgpr0
68    %1:sgpr(s32) = COPY $sgpr1
69    %2:sgpr(s1) = G_TRUNC %0
70    %3:sgpr(s1) = G_TRUNC %1
71    %4:sgpr(s1) = G_XOR %2, %3
72    S_ENDPGM 0, implicit %4
73...
74
75---
76
77name:            xor_s16_sgpr_sgpr_sgpr
78legalized:       true
79regBankSelected: true
80tracksRegLiveness: true
81
82body: |
83  bb.0:
84    liveins: $sgpr0, $sgpr1
85    ; WAVE64-LABEL: name: xor_s16_sgpr_sgpr_sgpr
86    ; WAVE64: liveins: $sgpr0, $sgpr1
87    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
88    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
89    ; WAVE64: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
90    ; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B32_]]
91    ; WAVE32-LABEL: name: xor_s16_sgpr_sgpr_sgpr
92    ; WAVE32: liveins: $sgpr0, $sgpr1
93    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
94    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
95    ; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
96    ; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]
97    %0:sgpr(s32) = COPY $sgpr0
98    %1:sgpr(s32) = COPY $sgpr1
99    %2:sgpr(s16) = G_TRUNC %0
100    %3:sgpr(s16) = G_TRUNC %1
101    %4:sgpr(s16) = G_XOR %2, %3
102    S_ENDPGM 0, implicit %4
103...
104
105---
106
107name:            xor_s16_vgpr_vgpr_vgpr
108legalized:       true
109regBankSelected: true
110tracksRegLiveness: true
111
112body: |
113  bb.0:
114    liveins: $vgpr0, $vgpr1
115    ; WAVE64-LABEL: name: xor_s16_vgpr_vgpr_vgpr
116    ; WAVE64: liveins: $vgpr0, $vgpr1
117    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
118    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
119    ; WAVE64: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
120    ; WAVE64: S_ENDPGM 0, implicit [[V_XOR_B32_e64_]]
121    ; WAVE32-LABEL: name: xor_s16_vgpr_vgpr_vgpr
122    ; WAVE32: liveins: $vgpr0, $vgpr1
123    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
124    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
125    ; WAVE32: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
126    ; WAVE32: S_ENDPGM 0, implicit [[V_XOR_B32_e64_]]
127    %0:vgpr(s32) = COPY $vgpr0
128    %1:vgpr(s32) = COPY $vgpr1
129    %2:vgpr(s16) = G_TRUNC %0
130    %3:vgpr(s16) = G_TRUNC %1
131    %4:vgpr(s16) = G_XOR %2, %3
132    S_ENDPGM 0, implicit %4
133...
134
135---
136
137name:            xor_s32_sgpr_sgpr_sgpr
138legalized:       true
139regBankSelected: true
140tracksRegLiveness: true
141
142body: |
143  bb.0:
144    liveins: $sgpr0, $sgpr1
145    ; WAVE64-LABEL: name: xor_s32_sgpr_sgpr_sgpr
146    ; WAVE64: liveins: $sgpr0, $sgpr1
147    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
148    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
149    ; WAVE64: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[COPY1]], implicit-def $scc
150    ; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B32_]]
151    ; WAVE32-LABEL: name: xor_s32_sgpr_sgpr_sgpr
152    ; WAVE32: liveins: $sgpr0, $sgpr1
153    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
154    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
155    ; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[COPY1]], implicit-def $scc
156    ; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]
157    %0:sgpr(s32) = COPY $sgpr0
158    %1:sgpr(s32) = COPY $sgpr1
159    %2:sgpr(s32) = G_XOR %0, %1
160    S_ENDPGM 0, implicit %2
161...
162
163---
164
165name:            xor_s64_sgpr_sgpr_sgpr
166legalized:       true
167regBankSelected: true
168tracksRegLiveness: true
169
170body: |
171  bb.0:
172    liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
173    ; WAVE64-LABEL: name: xor_s64_sgpr_sgpr_sgpr
174    ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
175    ; WAVE64: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
176    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
177    ; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[COPY]], [[COPY1]], implicit-def $scc
178    ; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B64_]]
179    ; WAVE32-LABEL: name: xor_s64_sgpr_sgpr_sgpr
180    ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
181    ; WAVE32: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
182    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
183    ; WAVE32: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[COPY]], [[COPY1]], implicit-def $scc
184    ; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B64_]]
185    %0:sgpr(s64) = COPY $sgpr0_sgpr1
186    %1:sgpr(s64) = COPY $sgpr2_sgpr3
187    %2:sgpr(s64) = G_XOR %0, %1
188    S_ENDPGM 0, implicit %2
189...
190
191---
192
193name:            xor_v2s16_sgpr_sgpr_sgpr
194legalized:       true
195regBankSelected: true
196tracksRegLiveness: true
197
198body: |
199  bb.0:
200    liveins: $sgpr0, $sgpr1
201    ; WAVE64-LABEL: name: xor_v2s16_sgpr_sgpr_sgpr
202    ; WAVE64: liveins: $sgpr0, $sgpr1
203    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
204    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
205    ; WAVE64: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
206    ; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B32_]]
207    ; WAVE32-LABEL: name: xor_v2s16_sgpr_sgpr_sgpr
208    ; WAVE32: liveins: $sgpr0, $sgpr1
209    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
210    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
211    ; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
212    ; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]
213    %0:sgpr(<2 x s16>) = COPY $sgpr0
214    %1:sgpr(<2 x s16>) = COPY $sgpr1
215    %2:sgpr(<2 x s16>) = G_XOR %0, %1
216    S_ENDPGM 0, implicit %2
217...
218
219---
220
221name:            xor_v2s32_sgpr_sgpr_sgpr
222legalized:       true
223regBankSelected: true
224tracksRegLiveness: true
225
226body: |
227  bb.0:
228    liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
229    ; WAVE64-LABEL: name: xor_v2s32_sgpr_sgpr_sgpr
230    ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
231    ; WAVE64: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
232    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
233    ; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
234    ; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B64_]]
235    ; WAVE32-LABEL: name: xor_v2s32_sgpr_sgpr_sgpr
236    ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
237    ; WAVE32: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
238    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
239    ; WAVE32: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
240    ; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B64_]]
241    %0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
242    %1:sgpr(<2 x s32>) = COPY $sgpr2_sgpr3
243    %2:sgpr(<2 x s32>) = G_XOR %0, %1
244    S_ENDPGM 0, implicit %2
245...
246
247---
248
249name:            xor_v4s16_sgpr_sgpr_sgpr
250legalized:       true
251regBankSelected: true
252tracksRegLiveness: true
253
254body: |
255  bb.0:
256    liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
257    ; WAVE64-LABEL: name: xor_v4s16_sgpr_sgpr_sgpr
258    ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
259    ; WAVE64: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
260    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
261    ; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
262    ; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B64_]]
263    ; WAVE32-LABEL: name: xor_v4s16_sgpr_sgpr_sgpr
264    ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
265    ; WAVE32: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
266    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
267    ; WAVE32: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
268    ; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B64_]]
269    %0:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1
270    %1:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3
271    %2:sgpr(<4 x s16>) = G_XOR %0, %1
272    S_ENDPGM 0, implicit %2
273...
274
275---
276
277name:            xor_s32_vgpr_vgpr_vgpr
278legalized:       true
279regBankSelected: true
280tracksRegLiveness: true
281
282body: |
283  bb.0:
284    liveins: $vgpr0, $vgpr1
285    ; WAVE64-LABEL: name: xor_s32_vgpr_vgpr_vgpr
286    ; WAVE64: liveins: $vgpr0, $vgpr1
287    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
288    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
289    ; WAVE64: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
290    ; WAVE64: S_ENDPGM 0, implicit [[V_XOR_B32_e64_]]
291    ; WAVE32-LABEL: name: xor_s32_vgpr_vgpr_vgpr
292    ; WAVE32: liveins: $vgpr0, $vgpr1
293    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
294    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
295    ; WAVE32: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
296    ; WAVE32: S_ENDPGM 0, implicit [[V_XOR_B32_e64_]]
297    %0:vgpr(s32) = COPY $vgpr0
298    %1:vgpr(s32) = COPY $vgpr1
299    %2:vgpr(s32) = G_XOR %0, %1
300    S_ENDPGM 0, implicit %2
301...
302
303---
304
305name:            xor_v2s16_vgpr_vgpr_vgpr
306legalized:       true
307regBankSelected: true
308tracksRegLiveness: true
309
310body: |
311  bb.0:
312    liveins: $vgpr0, $vgpr1
313    ; WAVE64-LABEL: name: xor_v2s16_vgpr_vgpr_vgpr
314    ; WAVE64: liveins: $vgpr0, $vgpr1
315    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
316    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
317    ; WAVE64: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
318    ; WAVE64: S_ENDPGM 0, implicit [[V_XOR_B32_e64_]]
319    ; WAVE32-LABEL: name: xor_v2s16_vgpr_vgpr_vgpr
320    ; WAVE32: liveins: $vgpr0, $vgpr1
321    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
322    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
323    ; WAVE32: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
324    ; WAVE32: S_ENDPGM 0, implicit [[V_XOR_B32_e64_]]
325    %0:vgpr(<2 x s16>) = COPY $vgpr0
326    %1:vgpr(<2 x s16>) = COPY $vgpr1
327    %2:vgpr(<2 x s16>) = G_XOR %0, %1
328    S_ENDPGM 0, implicit %2
329...
330
331
332# This should fail to select
333---
334
335name:            xor_s64_vgpr_vgpr_vgpr
336legalized:       true
337regBankSelected: true
338tracksRegLiveness: true
339
340body: |
341  bb.0:
342    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
343    ; WAVE64-LABEL: name: xor_s64_vgpr_vgpr_vgpr
344    ; WAVE64: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
345    ; WAVE64: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
346    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
347    ; WAVE64: [[XOR:%[0-9]+]]:vgpr(s64) = G_XOR [[COPY]], [[COPY1]]
348    ; WAVE64: S_ENDPGM 0, implicit [[XOR]](s64)
349    ; WAVE32-LABEL: name: xor_s64_vgpr_vgpr_vgpr
350    ; WAVE32: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
351    ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
352    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
353    ; WAVE32: [[XOR:%[0-9]+]]:vgpr(s64) = G_XOR [[COPY]], [[COPY1]]
354    ; WAVE32: S_ENDPGM 0, implicit [[XOR]](s64)
355    %0:vgpr(s64) = COPY $vgpr0_vgpr1
356    %1:vgpr(s64) = COPY $vgpr2_vgpr3
357    %2:vgpr(s64) = G_XOR %0, %1
358    S_ENDPGM 0, implicit %2
359...
360
361---
362
363name:            xor_s1_vcc_copy_to_vcc
364legalized:       true
365regBankSelected: true
366tracksRegLiveness: true
367
368body: |
369  bb.0:
370    liveins: $vgpr0, $vgpr1
371    ; WAVE64-LABEL: name: xor_s1_vcc_copy_to_vcc
372    ; WAVE64: liveins: $vgpr0, $vgpr1
373    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
374    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
375    ; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
376    ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
377    ; WAVE64: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec
378    ; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec
379    ; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
380    ; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B64_]]
381    ; WAVE32-LABEL: name: xor_s1_vcc_copy_to_vcc
382    ; WAVE32: liveins: $vgpr0, $vgpr1
383    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
384    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
385    ; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
386    ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
387    ; WAVE32: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec
388    ; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec
389    ; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
390    ; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]
391    %0:vgpr(s32) = COPY $vgpr0
392    %1:vgpr(s32) = COPY $vgpr1
393    %2:vgpr(s1) = G_TRUNC %0
394    %3:vgpr(s1) = G_TRUNC %1
395    %4:vcc(s1) = COPY %2
396    %5:vcc(s1) = COPY %3
397    %6:vcc(s1) = G_XOR %4, %5
398    S_ENDPGM 0, implicit %6
399...
400
401# The selector for the copy of the xor result may constrain the result
402# register of the xor, losing that it is a VCCRegBank context.
403
404# Works for wave32, should fail for wave64
405---
406name:            copy_select_constrain_vcc_result_reg_wave32
407legalized:       true
408regBankSelected: true
409tracksRegLiveness: true
410body:             |
411  bb.0:
412    liveins: $vgpr0, $sgpr0
413
414    ; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
415    ; WAVE64: liveins: $vgpr0, $sgpr0
416    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
417    ; WAVE64: %sgpr0:sreg_32 = COPY $sgpr0
418    ; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
419    ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
420    ; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc
421    ; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
422    ; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
423    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_XOR_B64_]]
424    ; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
425    ; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
426    ; WAVE32: liveins: $vgpr0, $sgpr0
427    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
428    ; WAVE32: %sgpr0:sreg_32 = COPY $sgpr0
429    ; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
430    ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
431    ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc
432    ; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
433    ; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
434    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_XOR_B32_]]
435    ; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
436    %1:vgpr(s32) = COPY $vgpr0
437    %0:vgpr(s1) = G_TRUNC %1(s32)
438    %sgpr0:sgpr(s32) = COPY $sgpr0
439    %2:sgpr(s1) = G_TRUNC %sgpr0
440    %6:sgpr(s32) = G_CONSTANT i32 0
441    %7:sgpr(p1) = G_IMPLICIT_DEF
442    %9:vcc(s1) = COPY %0(s1)
443    %10:vcc(s1) = COPY %2(s1)
444    %8:vcc(s1) = G_XOR %9, %10
445    %3:sreg_32_xm0(s1) = COPY %8(s1)
446    S_ENDPGM 0, implicit %3
447
448...
449
450# Works for wave64, should fail for wave32
451---
452name:            copy_select_constrain_vcc_result_reg_wave64
453legalized:       true
454regBankSelected: true
455tracksRegLiveness: true
456body:             |
457  bb.0:
458    liveins: $vgpr0, $sgpr0
459
460    ; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
461    ; WAVE64: liveins: $vgpr0, $sgpr0
462    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
463    ; WAVE64: %sgpr0:sreg_32 = COPY $sgpr0
464    ; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
465    ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
466    ; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc
467    ; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
468    ; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
469    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_XOR_B64_]]
470    ; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
471    ; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
472    ; WAVE32: liveins: $vgpr0, $sgpr0
473    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
474    ; WAVE32: %sgpr0:sreg_32 = COPY $sgpr0
475    ; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
476    ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
477    ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc
478    ; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
479    ; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_XOR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
480    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_XOR_B32_]]
481    ; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
482    %1:vgpr(s32) = COPY $vgpr0
483    %0:vgpr(s1) = G_TRUNC %1(s32)
484    %sgpr0:sgpr(s32) = COPY $sgpr0
485    %2:sgpr(s1) = G_TRUNC %sgpr0
486    %6:sgpr(s32) = G_CONSTANT i32 0
487    %7:sgpr(p1) = G_IMPLICIT_DEF
488    %9:vcc(s1) = COPY %0(s1)
489    %10:vcc(s1) = COPY %2(s1)
490    %8:vcc(s1) = G_XOR %9, %10
491    %3:sreg_64_xexec(s1) = COPY %8(s1)
492    S_ENDPGM 0, implicit %3
493
494...
495