1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -stop-after=irtranslator -o - %s | FileCheck %s
3
4@var = global i32 undef
5
6define i32 @test() {
7  ; CHECK-LABEL: name: test
8  ; CHECK: bb.1 (%ir-block.0):
9  ; CHECK:   liveins: $sgpr30_sgpr31
10  ; CHECK:   [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
11  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
12  ; CHECK:   [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[C]](s32)
13  ; CHECK:   [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var
14  ; CHECK:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[INTTOPTR]](p0), [[GV]]
15  ; CHECK:   [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
16  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY [[ZEXT]](s32)
17  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
18  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
19  ; CHECK:   [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
20  ; CHECK:   $vgpr0 = COPY [[COPY4]](s32)
21  ; CHECK:   [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
22  ; CHECK:   S_SETPC_B64_return [[COPY5]], implicit $vgpr0
23  ret i32 bitcast (<1 x i32> <i32 extractelement (<1 x i32> bitcast (i32 zext (i1 icmp eq (i32* @var, i32* inttoptr (i32 -1 to i32*)) to i32) to <1 x i32>), i64 0)> to i32)
24}
25
26@gint = external addrspace(1) global i8, align 4
27
28; Technically we should be able to fold away the compare to true, but
29; currently constexpr doesn't understand null in non-0 address spaces.
30define amdgpu_kernel void @constantexpr_select_0() {
31  ; CHECK-LABEL: name: constantexpr_select_0
32  ; CHECK: bb.1 (%ir-block.0):
33  ; CHECK:   [[GV:%[0-9]+]]:_(p1) = G_GLOBAL_VALUE @gint
34  ; CHECK:   [[C:%[0-9]+]]:_(p1) = G_CONSTANT i64 0
35  ; CHECK:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[GV]](p1), [[C]]
36  ; CHECK:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
37  ; CHECK:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
38  ; CHECK:   [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]
39  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
40  ; CHECK:   G_STORE [[SELECT]](s32), [[DEF]](p1) :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
41  ; CHECK:   S_ENDPGM 0
42  store i32 select (i1 icmp eq (i8 addrspace(1)* @gint, i8 addrspace(1)* null), i32 1, i32 0), i32 addrspace(1)* undef, align 4
43  ret void
44}
45
46define amdgpu_kernel void @constantexpr_select_1() {
47  ; CHECK-LABEL: name: constantexpr_select_1
48  ; CHECK: bb.1 (%ir-block.0):
49  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1024
50  ; CHECK:   [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[C]](s64)
51  ; CHECK:   [[GV:%[0-9]+]]:_(p1) = G_GLOBAL_VALUE @gint
52  ; CHECK:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[INTTOPTR]](p1), [[GV]]
53  ; CHECK:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
54  ; CHECK:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
55  ; CHECK:   [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]
56  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
57  ; CHECK:   G_STORE [[SELECT]](s32), [[DEF]](p1) :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
58  ; CHECK:   S_ENDPGM 0
59  store i32 select (i1 icmp eq (i8 addrspace(1)* @gint, i8 addrspace(1)* inttoptr (i64 1024 to i8 addrspace(1)*)), i32 1, i32 0), i32 addrspace(1)* undef, align 4
60  ret void
61}
62