1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s 3 4--- 5name: ctlz_s32_s32 6 7body: | 8 bb.0: 9 liveins: $vgpr0 10 ; CHECK-LABEL: name: ctlz_s32_s32 11 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 12 ; CHECK: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[COPY]](s32) 13 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 14 ; CHECK: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C]] 15 ; CHECK: $vgpr0 = COPY [[UMIN]](s32) 16 %0:_(s32) = COPY $vgpr0 17 %1:_(s32) = G_CTLZ %0 18 $vgpr0 = COPY %1 19... 20 21--- 22name: ctlz_s32_s64 23 24body: | 25 bb.0: 26 liveins: $vgpr0_vgpr1 27 ; CHECK-LABEL: name: ctlz_s32_s64 28 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 29 ; CHECK: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[COPY]](s64) 30 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 31 ; CHECK: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C]] 32 ; CHECK: $vgpr0 = COPY [[UMIN]](s32) 33 %0:_(s64) = COPY $vgpr0_vgpr1 34 %1:_(s32) = G_CTLZ %0 35 $vgpr0 = COPY %1 36... 37 38--- 39name: ctlz_s64_s64 40 41body: | 42 bb.0: 43 liveins: $vgpr0_vgpr1 44 ; CHECK-LABEL: name: ctlz_s64_s64 45 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 46 ; CHECK: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[COPY]](s64) 47 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 48 ; CHECK: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C]] 49 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[UMIN]](s32) 50 ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 51 %0:_(s64) = COPY $vgpr0_vgpr1 52 %1:_(s64) = G_CTLZ %0 53 $vgpr0_vgpr1 = COPY %1 54... 55 56--- 57name: ctlz_s16_s32 58 59body: | 60 bb.0: 61 liveins: $vgpr0 62 ; CHECK-LABEL: name: ctlz_s16_s32 63 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 64 ; CHECK: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[COPY]](s32) 65 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 66 ; CHECK: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C]] 67 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 68 ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UMIN]], [[C1]] 69 ; CHECK: $vgpr0 = COPY [[AND]](s32) 70 %0:_(s32) = COPY $vgpr0 71 %1:_(s16) = G_CTLZ %0 72 %2:_(s32) = G_ZEXT %1 73 $vgpr0 = COPY %2 74... 75 76--- 77name: ctlz_s16_s16 78 79body: | 80 bb.0: 81 liveins: $vgpr0 82 ; CHECK-LABEL: name: ctlz_s16_s16 83 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 84 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 85 ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] 86 ; CHECK: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[AND]](s32) 87 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 88 ; CHECK: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C1]] 89 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 90 ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMIN]], [[C2]] 91 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) 92 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] 93 ; CHECK: $vgpr0 = COPY [[AND1]](s32) 94 %0:_(s32) = COPY $vgpr0 95 %1:_(s16) = G_TRUNC %0 96 %2:_(s16) = G_CTLZ %1 97 %3:_(s32) = G_ZEXT %2 98 $vgpr0 = COPY %3 99... 100 101--- 102name: ctlz_v2s32_v2s32 103 104body: | 105 bb.0: 106 liveins: $vgpr0_vgpr1 107 ; CHECK-LABEL: name: ctlz_v2s32_v2s32 108 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 109 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) 110 ; CHECK: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[UV]](s32) 111 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 112 ; CHECK: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C]] 113 ; CHECK: [[AMDGPU_FFBH_U32_1:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[UV1]](s32) 114 ; CHECK: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_1]], [[C]] 115 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UMIN]](s32), [[UMIN1]](s32) 116 ; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) 117 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1 118 %1:_(<2 x s32>) = G_CTLZ %0 119 $vgpr0_vgpr1 = COPY %1 120... 121 122--- 123name: ctlz_v2s32_v2s64 124 125body: | 126 bb.0: 127 liveins: $vgpr0_vgpr1_vgpr2_vgpr3 128 ; CHECK-LABEL: name: ctlz_v2s32_v2s64 129 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 130 ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>) 131 ; CHECK: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[UV]](s64) 132 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 133 ; CHECK: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C]] 134 ; CHECK: [[AMDGPU_FFBH_U32_1:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[UV1]](s64) 135 ; CHECK: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_1]], [[C]] 136 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UMIN]](s32), [[UMIN1]](s32) 137 ; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) 138 %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 139 %1:_(<2 x s32>) = G_CTLZ %0 140 $vgpr0_vgpr1 = COPY %1 141... 142 143--- 144name: ctlz_v2s16_v2s16 145 146body: | 147 bb.0: 148 liveins: $vgpr0 149 ; CHECK-LABEL: name: ctlz_v2s16_v2s16 150 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 151 ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) 152 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 153 ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) 154 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 155 ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]] 156 ; CHECK: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[AND]](s32) 157 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 158 ; CHECK: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C2]] 159 ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMIN]], [[C]] 160 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) 161 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]] 162 ; CHECK: [[AMDGPU_FFBH_U32_1:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[AND1]](s32) 163 ; CHECK: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_1]], [[C2]] 164 ; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UMIN1]], [[C]] 165 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32) 166 ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] 167 ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]] 168 ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32) 169 ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL]] 170 ; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) 171 ; CHECK: $vgpr0 = COPY [[BITCAST1]](<2 x s16>) 172 %0:_(<2 x s16>) = COPY $vgpr0 173 %1:_(<2 x s16>) = G_CTLZ %0 174 $vgpr0 = COPY %1 175... 176 177--- 178name: ctlz_s7_s7 179 180body: | 181 bb.0: 182 liveins: $vgpr0 183 184 ; CHECK-LABEL: name: ctlz_s7_s7 185 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 186 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 187 ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] 188 ; CHECK: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[AND]](s32) 189 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 190 ; CHECK: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C1]] 191 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 25 192 ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMIN]], [[C2]] 193 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) 194 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] 195 ; CHECK: $vgpr0 = COPY [[AND1]](s32) 196 %0:_(s32) = COPY $vgpr0 197 %1:_(s7) = G_TRUNC %0 198 %2:_(s7) = G_CTLZ %1 199 %3:_(s32) = G_ZEXT %2 200 $vgpr0 = COPY %3 201... 202 203--- 204name: ctlz_s33_s33 205 206body: | 207 bb.0: 208 liveins: $vgpr0_vgpr1 209 210 ; CHECK-LABEL: name: ctlz_s33_s33 211 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 212 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591 213 ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] 214 ; CHECK: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[AND]](s64) 215 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 216 ; CHECK: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C1]] 217 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[UMIN]](s32) 218 ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 31 219 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ZEXT]](s64) 220 ; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C2]](s64) 221 ; CHECK: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[UV2]] 222 ; CHECK: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[USUBO]](s32) 223 ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT1]](s64) 224 %0:_(s64) = COPY $vgpr0_vgpr1 225 %1:_(s33) = G_TRUNC %0 226 %2:_(s33) = G_CTLZ %1 227 %3:_(s64) = G_ANYEXT %2 228 $vgpr0_vgpr1 = COPY %3 229... 230 231# --- 232# name: ctlz_v2s7_v2s7 233 234# body: | 235# bb.0: 236# liveins: $vgpr0 237# %0:_(<2 x s32>) = COPY $vgpr0_vgpr1 238# %1:_(<2 x s7>) = G_TRUNC %0 239# %2:_(<2 x s7>) = G_CTLZ %1 240# %3:_(<2 x s32>) = G_ANYEXT %2 241# $vgpr0_vgpr1 = COPY %3 242# ... 243