1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s | FileCheck -check-prefix=SI %s
3# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -run-pass=legalizer -o - %s | FileCheck -check-prefix=CI %s
4# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck -check-prefix=VI %s
5# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s
6# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s
7
8---
9name: test_fceil_s16
10body: |
11  bb.0:
12    liveins: $vgpr0
13
14    ; SI-LABEL: name: test_fceil_s16
15    ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
16    ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
17    ; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
18    ; SI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT]]
19    ; SI: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL]](s32)
20    ; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
21    ; SI: $vgpr0 = COPY [[ANYEXT]](s32)
22    ; CI-LABEL: name: test_fceil_s16
23    ; CI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
24    ; CI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
25    ; CI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
26    ; CI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT]]
27    ; CI: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL]](s32)
28    ; CI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
29    ; CI: $vgpr0 = COPY [[ANYEXT]](s32)
30    ; VI-LABEL: name: test_fceil_s16
31    ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
32    ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
33    ; VI: [[FCEIL:%[0-9]+]]:_(s16) = G_FCEIL [[TRUNC]]
34    ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCEIL]](s16)
35    ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
36    ; GFX9-LABEL: name: test_fceil_s16
37    ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
38    ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
39    ; GFX9: [[FCEIL:%[0-9]+]]:_(s16) = G_FCEIL [[TRUNC]]
40    ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCEIL]](s16)
41    ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
42    %0:_(s32) = COPY $vgpr0
43    %1:_(s16) = G_TRUNC %0
44    %2:_(s16) = G_FCEIL %1
45    %3:_(s32) = G_ANYEXT %2
46    $vgpr0 = COPY %3
47...
48
49---
50name: test_fceil_s32
51body: |
52  bb.0:
53    liveins: $vgpr0
54
55    ; SI-LABEL: name: test_fceil_s32
56    ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
57    ; SI: $vgpr0 = COPY [[COPY]](s32)
58    ; CI-LABEL: name: test_fceil_s32
59    ; CI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
60    ; CI: $vgpr0 = COPY [[COPY]](s32)
61    ; VI-LABEL: name: test_fceil_s32
62    ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
63    ; VI: $vgpr0 = COPY [[COPY]](s32)
64    ; GFX9-LABEL: name: test_fceil_s32
65    ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
66    ; GFX9: $vgpr0 = COPY [[COPY]](s32)
67    %0:_(s32) = COPY $vgpr0
68    %1:_(s32) = G_FCEIL %0
69    $vgpr0 = COPY %0
70...
71
72---
73name: test_fceil_s64
74body: |
75  bb.0:
76    liveins: $vgpr0_vgpr1
77
78    ; SI-LABEL: name: test_fceil_s64
79    ; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
80    ; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
81    ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
82    ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
83    ; SI: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[UV1]](s32), [[C]](s32), [[C1]](s32)
84    ; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1023
85    ; SI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[INT]], [[C2]]
86    ; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
87    ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
88    ; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4503599627370495
89    ; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
90    ; SI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C5]](s32), [[AND]](s32)
91    ; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[C4]], [[SUB]](s32)
92    ; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
93    ; SI: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[C6]]
94    ; SI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[XOR]]
95    ; SI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 51
96    ; SI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB]](s32), [[C5]]
97    ; SI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](s32), [[C7]]
98    ; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[MV]], [[AND1]]
99    ; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[COPY]], [[SELECT]]
100    ; SI: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
101    ; SI: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
102    ; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](s64), [[C8]]
103    ; SI: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[COPY]](s64), [[SELECT1]]
104    ; SI: [[AND2:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
105    ; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[AND2]](s1), [[C9]], [[C8]]
106    ; SI: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[SELECT1]], [[SELECT2]]
107    ; SI: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[COPY]]
108    ; SI: $vgpr0_vgpr1 = COPY [[FCEIL]](s64)
109    ; CI-LABEL: name: test_fceil_s64
110    ; CI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
111    ; CI: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[COPY]]
112    ; CI: $vgpr0_vgpr1 = COPY [[FCEIL]](s64)
113    ; VI-LABEL: name: test_fceil_s64
114    ; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
115    ; VI: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[COPY]]
116    ; VI: $vgpr0_vgpr1 = COPY [[FCEIL]](s64)
117    ; GFX9-LABEL: name: test_fceil_s64
118    ; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
119    ; GFX9: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[COPY]]
120    ; GFX9: $vgpr0_vgpr1 = COPY [[FCEIL]](s64)
121    %0:_(s64) = COPY $vgpr0_vgpr1
122    %1:_(s64) = G_FCEIL %0
123    $vgpr0_vgpr1 = COPY %1
124...
125
126---
127name: test_fceil_v2s16
128body: |
129  bb.0:
130    liveins: $vgpr0
131
132    ; SI-LABEL: name: test_fceil_v2s16
133    ; SI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
134    ; SI: $vgpr0 = COPY [[COPY]](<2 x s16>)
135    ; CI-LABEL: name: test_fceil_v2s16
136    ; CI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
137    ; CI: $vgpr0 = COPY [[COPY]](<2 x s16>)
138    ; VI-LABEL: name: test_fceil_v2s16
139    ; VI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
140    ; VI: $vgpr0 = COPY [[COPY]](<2 x s16>)
141    ; GFX9-LABEL: name: test_fceil_v2s16
142    ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
143    ; GFX9: $vgpr0 = COPY [[COPY]](<2 x s16>)
144    %0:_(<2 x s16>) = COPY $vgpr0
145    %1:_(<2 x s16>) = G_FCEIL %0
146    $vgpr0 = COPY %0
147...
148
149---
150name: test_fceil_v2s32
151body: |
152  bb.0:
153    liveins: $vgpr0_vgpr1
154
155    ; SI-LABEL: name: test_fceil_v2s32
156    ; SI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
157    ; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
158    ; SI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[UV]]
159    ; SI: [[FCEIL1:%[0-9]+]]:_(s32) = G_FCEIL [[UV1]]
160    ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FCEIL]](s32), [[FCEIL1]](s32)
161    ; SI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
162    ; CI-LABEL: name: test_fceil_v2s32
163    ; CI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
164    ; CI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
165    ; CI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[UV]]
166    ; CI: [[FCEIL1:%[0-9]+]]:_(s32) = G_FCEIL [[UV1]]
167    ; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FCEIL]](s32), [[FCEIL1]](s32)
168    ; CI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
169    ; VI-LABEL: name: test_fceil_v2s32
170    ; VI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
171    ; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
172    ; VI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[UV]]
173    ; VI: [[FCEIL1:%[0-9]+]]:_(s32) = G_FCEIL [[UV1]]
174    ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FCEIL]](s32), [[FCEIL1]](s32)
175    ; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
176    ; GFX9-LABEL: name: test_fceil_v2s32
177    ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
178    ; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
179    ; GFX9: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[UV]]
180    ; GFX9: [[FCEIL1:%[0-9]+]]:_(s32) = G_FCEIL [[UV1]]
181    ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FCEIL]](s32), [[FCEIL1]](s32)
182    ; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
183    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
184    %1:_(<2 x s32>) = G_FCEIL %0
185    $vgpr0_vgpr1 = COPY %1
186...
187
188---
189name: test_fceil_v2s64
190body: |
191  bb.0:
192    liveins: $vgpr0_vgpr1_vgpr2_vgpr3
193
194    ; SI-LABEL: name: test_fceil_v2s64
195    ; SI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
196    ; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
197    ; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64)
198    ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
199    ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
200    ; SI: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[UV3]](s32), [[C]](s32), [[C1]](s32)
201    ; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1023
202    ; SI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[INT]], [[C2]]
203    ; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
204    ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C3]]
205    ; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4503599627370495
206    ; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
207    ; SI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C5]](s32), [[AND]](s32)
208    ; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[C4]], [[SUB]](s32)
209    ; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
210    ; SI: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[C6]]
211    ; SI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV]], [[XOR]]
212    ; SI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 51
213    ; SI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB]](s32), [[C5]]
214    ; SI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](s32), [[C7]]
215    ; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[MV]], [[AND1]]
216    ; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV]], [[SELECT]]
217    ; SI: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
218    ; SI: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
219    ; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV]](s64), [[C8]]
220    ; SI: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[UV]](s64), [[SELECT1]]
221    ; SI: [[AND2:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
222    ; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[AND2]](s1), [[C9]], [[C8]]
223    ; SI: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[SELECT1]], [[SELECT2]]
224    ; SI: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[UV]]
225    ; SI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
226    ; SI: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[UV5]](s32), [[C]](s32), [[C1]](s32)
227    ; SI: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[INT1]], [[C2]]
228    ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C3]]
229    ; SI: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C5]](s32), [[AND3]](s32)
230    ; SI: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[C4]], [[SUB1]](s32)
231    ; SI: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[ASHR1]], [[C6]]
232    ; SI: [[AND4:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[XOR1]]
233    ; SI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB1]](s32), [[C5]]
234    ; SI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB1]](s32), [[C7]]
235    ; SI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[MV1]], [[AND4]]
236    ; SI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV1]], [[SELECT3]]
237    ; SI: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV1]](s64), [[C8]]
238    ; SI: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[UV1]](s64), [[SELECT4]]
239    ; SI: [[AND5:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
240    ; SI: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[AND5]](s1), [[C9]], [[C8]]
241    ; SI: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[SELECT4]], [[SELECT5]]
242    ; SI: [[FCEIL1:%[0-9]+]]:_(s64) = G_FCEIL [[UV1]]
243    ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FCEIL]](s64), [[FCEIL1]](s64)
244    ; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
245    ; CI-LABEL: name: test_fceil_v2s64
246    ; CI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
247    ; CI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
248    ; CI: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[UV]]
249    ; CI: [[FCEIL1:%[0-9]+]]:_(s64) = G_FCEIL [[UV1]]
250    ; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FCEIL]](s64), [[FCEIL1]](s64)
251    ; CI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
252    ; VI-LABEL: name: test_fceil_v2s64
253    ; VI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
254    ; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
255    ; VI: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[UV]]
256    ; VI: [[FCEIL1:%[0-9]+]]:_(s64) = G_FCEIL [[UV1]]
257    ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FCEIL]](s64), [[FCEIL1]](s64)
258    ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
259    ; GFX9-LABEL: name: test_fceil_v2s64
260    ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
261    ; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
262    ; GFX9: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[UV]]
263    ; GFX9: [[FCEIL1:%[0-9]+]]:_(s64) = G_FCEIL [[UV1]]
264    ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FCEIL]](s64), [[FCEIL1]](s64)
265    ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
266    %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
267    %1:_(<2 x s64>) = G_FCEIL %0
268    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
269...
270