1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX6 %s 3# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s 4# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s 5 6--- 7name: test_fpowi_s16_s32_flags 8body: | 9 bb.0: 10 liveins: $vgpr0, $vgpr1 11 12 ; GFX6-LABEL: name: test_fpowi_s16_s32_flags 13 ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 14 ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 15 ; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 16 ; GFX6: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16) 17 ; GFX6: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY1]](s32) 18 ; GFX6: [[FLOG2_:%[0-9]+]]:_(s32) = nnan G_FLOG2 [[FPEXT]] 19 ; GFX6: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[SITOFP]](s32) 20 ; GFX6: [[FEXP2_:%[0-9]+]]:_(s32) = nnan G_FEXP2 [[INT]] 21 ; GFX6: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FEXP2_]](s32) 22 ; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16) 23 ; GFX6: $vgpr0 = COPY [[ANYEXT]](s32) 24 ; GFX9-LABEL: name: test_fpowi_s16_s32_flags 25 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 26 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 27 ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 28 ; GFX9: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[COPY1]](s32) 29 ; GFX9: [[FLOG2_:%[0-9]+]]:_(s16) = nnan G_FLOG2 [[TRUNC]] 30 ; GFX9: [[FPEXT:%[0-9]+]]:_(s32) = nnan G_FPEXT [[FLOG2_]](s16) 31 ; GFX9: [[FPEXT1:%[0-9]+]]:_(s32) = nnan G_FPEXT [[SITOFP]](s16) 32 ; GFX9: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FPEXT]](s32), [[FPEXT1]](s32) 33 ; GFX9: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT]](s32) 34 ; GFX9: [[FEXP2_:%[0-9]+]]:_(s16) = nnan G_FEXP2 [[FPTRUNC]] 35 ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FEXP2_]](s16) 36 ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) 37 %0:_(s32) = COPY $vgpr0 38 %1:_(s32) = COPY $vgpr1 39 %2:_(s16) = G_TRUNC %0 40 %3:_(s16) = nnan G_FPOWI %2, %1 41 %4:_(s32) = G_ANYEXT %3 42 $vgpr0 = COPY %4 43... 44 45--- 46name: test_fpowi_s32_s32_flags 47body: | 48 bb.0: 49 liveins: $vgpr0, $vgpr1 50 51 ; GFX6-LABEL: name: test_fpowi_s32_s32_flags 52 ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 53 ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 54 ; GFX6: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY1]](s32) 55 ; GFX6: [[FLOG2_:%[0-9]+]]:_(s32) = nnan G_FLOG2 [[COPY]] 56 ; GFX6: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[SITOFP]](s32) 57 ; GFX6: [[FEXP2_:%[0-9]+]]:_(s32) = nnan G_FEXP2 [[INT]] 58 ; GFX6: $vgpr0 = COPY [[FEXP2_]](s32) 59 ; GFX9-LABEL: name: test_fpowi_s32_s32_flags 60 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 61 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 62 ; GFX9: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY1]](s32) 63 ; GFX9: [[FLOG2_:%[0-9]+]]:_(s32) = nnan G_FLOG2 [[COPY]] 64 ; GFX9: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[SITOFP]](s32) 65 ; GFX9: [[FEXP2_:%[0-9]+]]:_(s32) = nnan G_FEXP2 [[INT]] 66 ; GFX9: $vgpr0 = COPY [[FEXP2_]](s32) 67 %0:_(s32) = COPY $vgpr0 68 %1:_(s32) = COPY $vgpr1 69 %2:_(s32) = nnan G_FPOWI %0, %1 70 $vgpr0 = COPY %2 71... 72