1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN 3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN 4 5define i32 @global_atomic_csub(i32 addrspace(1)* %ptr, i32 %data) { 6; GCN-LABEL: global_atomic_csub: 7; GCN: ; %bb.0: 8; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 9; GCN-NEXT: s_waitcnt_vscnt null, 0x0 10; GCN-NEXT: global_atomic_csub v0, v[0:1], v2, off glc 11; GCN-NEXT: s_waitcnt vmcnt(0) 12; GCN-NEXT: s_setpc_b64 s[30:31] 13 %ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %ptr, i32 %data) 14 ret i32 %ret 15} 16 17define i32 @global_atomic_csub_offset(i32 addrspace(1)* %ptr, i32 %data) { 18; GCN-LABEL: global_atomic_csub_offset: 19; GCN: ; %bb.0: 20; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 21; GCN-NEXT: s_waitcnt_vscnt null, 0x0 22; GCN-NEXT: s_mov_b64 s[4:5], 0x1000 23; GCN-NEXT: v_mov_b32_e32 v3, s4 24; GCN-NEXT: v_mov_b32_e32 v4, s5 25; GCN-NEXT: v_add_co_u32 v0, vcc_lo, v0, v3 26; GCN-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v4, vcc_lo 27; GCN-NEXT: global_atomic_csub v0, v[0:1], v2, off glc 28; GCN-NEXT: s_waitcnt vmcnt(0) 29; GCN-NEXT: s_setpc_b64 s[30:31] 30 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 1024 31 %ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %gep, i32 %data) 32 ret i32 %ret 33} 34 35define void @global_atomic_csub_nortn(i32 addrspace(1)* %ptr, i32 %data) { 36; GCN-LABEL: global_atomic_csub_nortn: 37; GCN: ; %bb.0: 38; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 39; GCN-NEXT: s_waitcnt_vscnt null, 0x0 40; GCN-NEXT: global_atomic_csub v0, v[0:1], v2, off glc 41; GCN-NEXT: s_waitcnt vmcnt(0) 42; GCN-NEXT: s_setpc_b64 s[30:31] 43 %ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %ptr, i32 %data) 44 ret void 45} 46 47define void @global_atomic_csub_offset_nortn(i32 addrspace(1)* %ptr, i32 %data) { 48; GCN-LABEL: global_atomic_csub_offset_nortn: 49; GCN: ; %bb.0: 50; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 51; GCN-NEXT: s_waitcnt_vscnt null, 0x0 52; GCN-NEXT: s_mov_b64 s[4:5], 0x1000 53; GCN-NEXT: v_mov_b32_e32 v3, s4 54; GCN-NEXT: v_mov_b32_e32 v4, s5 55; GCN-NEXT: v_add_co_u32 v0, vcc_lo, v0, v3 56; GCN-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v4, vcc_lo 57; GCN-NEXT: global_atomic_csub v0, v[0:1], v2, off glc 58; GCN-NEXT: s_waitcnt vmcnt(0) 59; GCN-NEXT: s_setpc_b64 s[30:31] 60 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 1024 61 %ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %gep, i32 %data) 62 ret void 63} 64 65define amdgpu_kernel void @global_atomic_csub_sgpr_base_offset(i32 addrspace(1)* %ptr, i32 %data) { 66; GCN-LABEL: global_atomic_csub_sgpr_base_offset: 67; GCN: ; %bb.0: 68; GCN-NEXT: s_clause 0x1 69; GCN-NEXT: s_load_dword s2, s[4:5], 0x8 70; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 71; GCN-NEXT: v_mov_b32_e32 v1, 0x1000 72; GCN-NEXT: s_waitcnt lgkmcnt(0) 73; GCN-NEXT: v_mov_b32_e32 v0, s2 74; GCN-NEXT: global_atomic_csub v0, v1, v0, s[0:1] glc 75; GCN-NEXT: s_waitcnt vmcnt(0) 76; GCN-NEXT: global_store_dword v[0:1], v0, off 77; GCN-NEXT: s_endpgm 78 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 1024 79 %ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %gep, i32 %data) 80 store i32 %ret, i32 addrspace(1)* undef 81 ret void 82} 83 84define amdgpu_kernel void @global_atomic_csub_sgpr_base_offset_nortn(i32 addrspace(1)* %ptr, i32 %data) { 85; GCN-LABEL: global_atomic_csub_sgpr_base_offset_nortn: 86; GCN: ; %bb.0: 87; GCN-NEXT: s_clause 0x1 88; GCN-NEXT: s_load_dword s2, s[4:5], 0x8 89; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 90; GCN-NEXT: v_mov_b32_e32 v1, 0x1000 91; GCN-NEXT: s_waitcnt lgkmcnt(0) 92; GCN-NEXT: v_mov_b32_e32 v0, s2 93; GCN-NEXT: global_atomic_csub v0, v1, v0, s[0:1] glc 94; GCN-NEXT: s_endpgm 95 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 1024 96 %ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %gep, i32 %data) 97 ret void 98} 99 100declare i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* nocapture, i32) #1 101 102attributes #0 = { nounwind willreturn } 103attributes #1 = { argmemonly nounwind } 104