1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -stop-after=instruction-select -o - %s | FileCheck %s
3
4define amdgpu_ps void @struct_buffer_store_format_f32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
5  ; CHECK-LABEL: name: struct_buffer_store_format_f32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
6  ; CHECK: bb.1 (%ir-block.0):
7  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
8  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
9  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
10  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
11  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
12  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
13  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
14  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
15  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
16  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
17  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
18  ; CHECK:   BUFFER_STORE_FORMAT_X_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s32), align 1, addrspace 4)
19  ; CHECK:   S_ENDPGM 0
20  call void @llvm.amdgcn.struct.buffer.store.format.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
21  ret void
22}
23
24define amdgpu_ps void @struct_buffer_store_format_v2f32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<2 x float> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
25  ; CHECK-LABEL: name: struct_buffer_store_format_v2f32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
26  ; CHECK: bb.1 (%ir-block.0):
27  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3
28  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
29  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
30  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
31  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
32  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
33  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4
34  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5
35  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3
36  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
37  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
38  ; CHECK:   [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6
39  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
40  ; CHECK:   BUFFER_STORE_FORMAT_XY_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 0, 0, 0, implicit $exec :: (dereferenceable store (<2 x s32>), align 1, addrspace 4)
41  ; CHECK:   S_ENDPGM 0
42  call void @llvm.amdgcn.struct.buffer.store.format.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
43  ret void
44}
45
46define amdgpu_ps void @struct_buffer_store_format_v3f32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<3 x float> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
47  ; CHECK-LABEL: name: struct_buffer_store_format_v3f32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
48  ; CHECK: bb.1 (%ir-block.0):
49  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
50  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
51  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
52  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
53  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2
54  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2
55  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3
56  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4
57  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr5
58  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[COPY6]], %subreg.sub3
59  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
60  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4
61  ; CHECK:   [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6
62  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY7]], %subreg.sub0, [[COPY8]], %subreg.sub1
63  ; CHECK:   BUFFER_STORE_FORMAT_XYZ_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY9]], 0, 0, 0, 0, implicit $exec :: (dereferenceable store (<3 x s32>), align 1, addrspace 4)
64  ; CHECK:   S_ENDPGM 0
65  call void @llvm.amdgcn.struct.buffer.store.format.v3f32(<3 x float> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
66  ret void
67}
68
69define amdgpu_ps void @struct_buffer_store_format_v4f32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x float> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
70  ; CHECK-LABEL: name: struct_buffer_store_format_v4f32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
71  ; CHECK: bb.1 (%ir-block.0):
72  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
73  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
74  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
75  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
76  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
77  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
78  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
79  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3
80  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4
81  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5
82  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3
83  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4
84  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY $vgpr5
85  ; CHECK:   [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr6
86  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1
87  ; CHECK:   BUFFER_STORE_FORMAT_XYZW_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY10]], 0, 0, 0, 0, implicit $exec :: (dereferenceable store (<4 x s32>), align 1, addrspace 4)
88  ; CHECK:   S_ENDPGM 0
89  call void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
90  ret void
91}
92
93define amdgpu_ps void @struct_buffer_store_format_f32__sgpr_val__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset(float inreg %val, <4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {
94  ; CHECK-LABEL: name: struct_buffer_store_format_f32__sgpr_val__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset
95  ; CHECK: bb.1 (%ir-block.0):
96  ; CHECK:   successors: %bb.2(0x80000000)
97  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
98  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
99  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
100  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
101  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2
102  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3
103  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
104  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3
105  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4
106  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4
107  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
108  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
109  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
110  ; CHECK:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
111  ; CHECK:   [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
112  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
113  ; CHECK: bb.2:
114  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
115  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]].sub0, implicit $exec
116  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]].sub1, implicit $exec
117  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
118  ; CHECK:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY11]], implicit $exec
119  ; CHECK:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]].sub0, implicit $exec
120  ; CHECK:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]].sub1, implicit $exec
121  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
122  ; CHECK:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY12]], implicit $exec
123  ; CHECK:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
124  ; CHECK:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
125  ; CHECK:   [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
126  ; CHECK:   [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY7]], implicit $exec
127  ; CHECK:   [[S_AND_B64_1:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U32_e64_]], [[S_AND_B64_]], implicit-def $scc
128  ; CHECK:   [[REG_SEQUENCE4:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1
129  ; CHECK:   BUFFER_STORE_FORMAT_X_BOTHEN_exact [[COPY8]], [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[V_READFIRSTLANE_B32_4]], 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s32), align 1, addrspace 4)
130  ; CHECK:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_1]], implicit-def $exec, implicit-def $scc, implicit $exec
131  ; CHECK:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
132  ; CHECK:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
133  ; CHECK: bb.3:
134  ; CHECK:   successors: %bb.4(0x80000000)
135  ; CHECK:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
136  ; CHECK: bb.4:
137  ; CHECK:   S_ENDPGM 0
138  call void @llvm.amdgcn.struct.buffer.store.format.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
139  ret void
140}
141
142define amdgpu_ps void @struct_buffer_store_format_i32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(i32 %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
143  ; CHECK-LABEL: name: struct_buffer_store_format_i32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
144  ; CHECK: bb.1 (%ir-block.0):
145  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
146  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
147  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
148  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
149  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
150  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
151  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
152  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
153  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
154  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
155  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
156  ; CHECK:   BUFFER_STORE_FORMAT_X_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s32), align 1, addrspace 4)
157  ; CHECK:   S_ENDPGM 0
158  call void @llvm.amdgcn.struct.buffer.store.format.i32(i32 %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
159  ret void
160}
161
162declare void @llvm.amdgcn.struct.buffer.store.format.f32(float, <4 x i32>, i32, i32, i32, i32 immarg)
163declare void @llvm.amdgcn.struct.buffer.store.format.v2f32(<2 x float>, <4 x i32>, i32, i32, i32, i32 immarg)
164declare void @llvm.amdgcn.struct.buffer.store.format.v3f32(<3 x float>, <4 x i32>, i32, i32, i32, i32 immarg)
165declare void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float>, <4 x i32>, i32, i32, i32, i32 immarg)
166declare void @llvm.amdgcn.struct.buffer.store.format.i32(i32, <4 x i32>, i32, i32, i32, i32 immarg)
167