1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck --check-prefix=GCN %s
3# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck --check-prefix=GCN %s
4
5---
6name:            bfe_and_lshr_s32
7legalized:       true
8tracksRegLiveness: true
9
10body: |
11  bb.0.entry:
12  liveins: $vgpr0
13
14    ; GCN-LABEL: name: bfe_and_lshr_s32
15    ; GCN: liveins: $vgpr0
16    ; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
17    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
18    ; GCN: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
19    ; GCN: [[UBFX:%[0-9]+]]:_(s32) = G_UBFX [[COPY]], [[C1]](s32), [[C]]
20    ; GCN: $vgpr0 = COPY [[UBFX]](s32)
21    %0:_(s32) = COPY $vgpr0
22    %1:_(s32) = G_CONSTANT i32 8
23    %2:_(s32) = G_LSHR %0, %1(s32)
24    %3:_(s32) = G_CONSTANT i32 31
25    %4:_(s32) = G_AND %2, %3
26    $vgpr0 = COPY %4(s32)
27
28...
29
30---
31name:            bfe_and_lshr_s64
32legalized:       true
33tracksRegLiveness: true
34
35body: |
36  bb.0.entry:
37  liveins: $vgpr0_vgpr1
38
39    ; GCN-LABEL: name: bfe_and_lshr_s64
40    ; GCN: liveins: $vgpr0_vgpr1
41    ; GCN: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
42    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
43    ; GCN: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
44    ; GCN: [[UBFX:%[0-9]+]]:_(s64) = G_UBFX [[COPY]], [[C1]](s32), [[C]]
45    ; GCN: $vgpr0_vgpr1 = COPY [[UBFX]](s64)
46    %0:_(s64) = COPY $vgpr0_vgpr1
47    %1:_(s32) = G_CONSTANT i32 8
48    %2:_(s64) = G_LSHR %0, %1(s32)
49    %3:_(s64) = G_CONSTANT i64 1023
50    %4:_(s64) = G_AND %2, %3
51    $vgpr0_vgpr1 = COPY %4(s64)
52
53...
54
55---
56name:            toobig_and_lshr_s32
57legalized:       true
58tracksRegLiveness: true
59
60body: |
61  bb.0.entry:
62  liveins: $vgpr0
63
64    ; GCN-LABEL: name: toobig_and_lshr_s32
65    ; GCN: liveins: $vgpr0
66    ; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
67    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
68    ; GCN: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
69    ; GCN: $vgpr0 = COPY [[LSHR]](s32)
70    %0:_(s32) = COPY $vgpr0
71    %1:_(s32) = G_CONSTANT i32 28
72    %2:_(s32) = G_LSHR %0, %1(s32)
73    %3:_(s32) = G_CONSTANT i32 511
74    %4:_(s32) = G_AND %2, %3
75    $vgpr0 = COPY %4(s32)
76
77...
78
79---
80name:            bfe_and_ashr_s32
81legalized:       true
82tracksRegLiveness: true
83
84body: |
85  bb.0.entry:
86  liveins: $vgpr0
87
88    ; GCN-LABEL: name: bfe_and_ashr_s32
89    ; GCN: liveins: $vgpr0
90    ; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
91    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
92    ; GCN: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
93    ; GCN: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
94    ; GCN: [[AND:%[0-9]+]]:_(s32) = G_AND [[ASHR]], [[C1]]
95    ; GCN: $vgpr0 = COPY [[AND]](s32)
96    %0:_(s32) = COPY $vgpr0
97    %1:_(s32) = G_CONSTANT i32 8
98    %2:_(s32) = G_ASHR %0, %1(s32)
99    %3:_(s32) = G_CONSTANT i32 31
100    %4:_(s32) = G_AND %2, %3
101    $vgpr0 = COPY %4(s32)
102
103...
104