1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s
3
4---
5name: test_min_max_ValK0_K1_i32
6legalized: true
7regBankSelected: true
8tracksRegLiveness: true
9body: |
10  bb.1:
11    liveins: $vgpr0, $sgpr30_sgpr31
12
13    ; CHECK-LABEL: name: test_min_max_ValK0_K1_i32
14    ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
15    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
16    ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
17    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12
18    ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
19    ; CHECK: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[C]], [[C1]]
20    ; CHECK: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)
21    ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
22    ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
23    %0:vgpr(s32) = COPY $vgpr0
24    %1:sgpr_64 = COPY $sgpr30_sgpr31
25    %2:sgpr(s32) = G_CONSTANT i32 -12
26    %7:vgpr(s32) = COPY %2(s32)
27    %3:vgpr(s32) = G_SMAX %0, %7
28    %4:sgpr(s32) = G_CONSTANT i32 17
29    %8:vgpr(s32) = COPY %4(s32)
30    %5:vgpr(s32) = G_SMIN %3, %8
31    $vgpr0 = COPY %5(s32)
32    %6:ccr_sgpr_64 = COPY %1
33    S_SETPC_B64_return %6, implicit $vgpr0
34...
35
36---
37name: min_max_ValK0_K1_i32
38legalized: true
39regBankSelected: true
40tracksRegLiveness: true
41body: |
42  bb.1:
43    liveins: $vgpr0, $sgpr30_sgpr31
44
45    ; CHECK-LABEL: name: min_max_ValK0_K1_i32
46    ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
47    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
48    ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
49    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12
50    ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
51    ; CHECK: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[C]], [[C1]]
52    ; CHECK: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)
53    ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
54    ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
55    %0:vgpr(s32) = COPY $vgpr0
56    %1:sgpr_64 = COPY $sgpr30_sgpr31
57    %2:sgpr(s32) = G_CONSTANT i32 -12
58    %7:vgpr(s32) = COPY %2(s32)
59    %3:vgpr(s32) = G_SMAX %7, %0
60    %4:sgpr(s32) = G_CONSTANT i32 17
61    %8:vgpr(s32) = COPY %4(s32)
62    %5:vgpr(s32) = G_SMIN %3, %8
63    $vgpr0 = COPY %5(s32)
64    %6:ccr_sgpr_64 = COPY %1
65    S_SETPC_B64_return %6, implicit $vgpr0
66...
67
68---
69name: test_min_K1max_ValK0__i32
70legalized: true
71regBankSelected: true
72tracksRegLiveness: true
73body: |
74  bb.1:
75    liveins: $vgpr0, $sgpr30_sgpr31
76
77    ; CHECK-LABEL: name: test_min_K1max_ValK0__i32
78    ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
79    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
80    ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
81    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12
82    ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
83    ; CHECK: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[C]], [[C1]]
84    ; CHECK: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)
85    ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
86    ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
87    %0:vgpr(s32) = COPY $vgpr0
88    %1:sgpr_64 = COPY $sgpr30_sgpr31
89    %2:sgpr(s32) = G_CONSTANT i32 -12
90    %7:vgpr(s32) = COPY %2(s32)
91    %3:vgpr(s32) = G_SMAX %0, %7
92    %4:sgpr(s32) = G_CONSTANT i32 17
93    %8:vgpr(s32) = COPY %4(s32)
94    %5:vgpr(s32) = G_SMIN %8, %3
95    $vgpr0 = COPY %5(s32)
96    %6:ccr_sgpr_64 = COPY %1
97    S_SETPC_B64_return %6, implicit $vgpr0
98...
99
100---
101name: test_min_K1max_K0Val__i32
102legalized: true
103regBankSelected: true
104tracksRegLiveness: true
105body: |
106  bb.1:
107    liveins: $vgpr0, $sgpr30_sgpr31
108
109    ; CHECK-LABEL: name: test_min_K1max_K0Val__i32
110    ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
111    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
112    ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
113    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12
114    ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
115    ; CHECK: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[C]], [[C1]]
116    ; CHECK: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)
117    ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
118    ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
119    %0:vgpr(s32) = COPY $vgpr0
120    %1:sgpr_64 = COPY $sgpr30_sgpr31
121    %2:sgpr(s32) = G_CONSTANT i32 -12
122    %7:vgpr(s32) = COPY %2(s32)
123    %3:vgpr(s32) = G_SMAX %7, %0
124    %4:sgpr(s32) = G_CONSTANT i32 17
125    %8:vgpr(s32) = COPY %4(s32)
126    %5:vgpr(s32) = G_SMIN %8, %3
127    $vgpr0 = COPY %5(s32)
128    %6:ccr_sgpr_64 = COPY %1
129    S_SETPC_B64_return %6, implicit $vgpr0
130...
131
132---
133name: test_max_min_ValK1_K0_i32
134legalized: true
135regBankSelected: true
136tracksRegLiveness: true
137body: |
138  bb.1:
139    liveins: $vgpr0, $sgpr30_sgpr31
140
141    ; CHECK-LABEL: name: test_max_min_ValK1_K0_i32
142    ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
143    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
144    ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
145    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
146    ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12
147    ; CHECK: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[C1]], [[C]]
148    ; CHECK: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)
149    ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
150    ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
151    %0:vgpr(s32) = COPY $vgpr0
152    %1:sgpr_64 = COPY $sgpr30_sgpr31
153    %2:sgpr(s32) = G_CONSTANT i32 17
154    %7:vgpr(s32) = COPY %2(s32)
155    %3:vgpr(s32) = G_SMIN %0, %7
156    %4:sgpr(s32) = G_CONSTANT i32 -12
157    %8:vgpr(s32) = COPY %4(s32)
158    %5:vgpr(s32) = G_SMAX %3, %8
159    $vgpr0 = COPY %5(s32)
160    %6:ccr_sgpr_64 = COPY %1
161    S_SETPC_B64_return %6, implicit $vgpr0
162...
163
164---
165name: test_max_min_K1Val_K0_i32
166legalized: true
167regBankSelected: true
168tracksRegLiveness: true
169body: |
170  bb.1:
171    liveins: $vgpr0, $sgpr30_sgpr31
172
173    ; CHECK-LABEL: name: test_max_min_K1Val_K0_i32
174    ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
175    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
176    ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
177    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
178    ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12
179    ; CHECK: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[C1]], [[C]]
180    ; CHECK: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)
181    ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
182    ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
183    %0:vgpr(s32) = COPY $vgpr0
184    %1:sgpr_64 = COPY $sgpr30_sgpr31
185    %2:sgpr(s32) = G_CONSTANT i32 17
186    %7:vgpr(s32) = COPY %2(s32)
187    %3:vgpr(s32) = G_SMIN %7, %0
188    %4:sgpr(s32) = G_CONSTANT i32 -12
189    %8:vgpr(s32) = COPY %4(s32)
190    %5:vgpr(s32) = G_SMAX %3, %8
191    $vgpr0 = COPY %5(s32)
192    %6:ccr_sgpr_64 = COPY %1
193    S_SETPC_B64_return %6, implicit $vgpr0
194...
195
196---
197name: test_max_K0min_ValK1__i32
198legalized: true
199regBankSelected: true
200tracksRegLiveness: true
201body: |
202  bb.1:
203    liveins: $vgpr0, $sgpr30_sgpr31
204
205    ; CHECK-LABEL: name: test_max_K0min_ValK1__i32
206    ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
207    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
208    ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
209    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
210    ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12
211    ; CHECK: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[C1]], [[C]]
212    ; CHECK: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)
213    ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
214    ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
215    %0:vgpr(s32) = COPY $vgpr0
216    %1:sgpr_64 = COPY $sgpr30_sgpr31
217    %2:sgpr(s32) = G_CONSTANT i32 17
218    %7:vgpr(s32) = COPY %2(s32)
219    %3:vgpr(s32) = G_SMIN %0, %7
220    %4:sgpr(s32) = G_CONSTANT i32 -12
221    %8:vgpr(s32) = COPY %4(s32)
222    %5:vgpr(s32) = G_SMAX %8, %3
223    $vgpr0 = COPY %5(s32)
224    %6:ccr_sgpr_64 = COPY %1
225    S_SETPC_B64_return %6, implicit $vgpr0
226...
227
228---
229name: test_max_K0min_K1Val__i32
230legalized: true
231regBankSelected: true
232tracksRegLiveness: true
233body: |
234  bb.1:
235    liveins: $vgpr0, $sgpr30_sgpr31
236
237    ; CHECK-LABEL: name: test_max_K0min_K1Val__i32
238    ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
239    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
240    ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
241    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
242    ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12
243    ; CHECK: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[C1]], [[C]]
244    ; CHECK: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)
245    ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
246    ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
247    %0:vgpr(s32) = COPY $vgpr0
248    %1:sgpr_64 = COPY $sgpr30_sgpr31
249    %2:sgpr(s32) = G_CONSTANT i32 17
250    %7:vgpr(s32) = COPY %2(s32)
251    %3:vgpr(s32) = G_SMIN %7, %0
252    %4:sgpr(s32) = G_CONSTANT i32 -12
253    %8:vgpr(s32) = COPY %4(s32)
254    %5:vgpr(s32) = G_SMAX %8, %3
255    $vgpr0 = COPY %5(s32)
256    %6:ccr_sgpr_64 = COPY %1
257    S_SETPC_B64_return %6, implicit $vgpr0
258...
259
260---
261name: test_max_K0min_K1Val__v2i16
262legalized: true
263regBankSelected: true
264tracksRegLiveness: true
265body: |
266  bb.1:
267    liveins: $vgpr0, $sgpr30_sgpr31
268
269    ; CHECK-LABEL: name: test_max_K0min_K1Val__v2i16
270    ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
271    ; CHECK: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
272    ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
273    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
274    ; CHECK: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C]](s32), [[C]](s32)
275    ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12
276    ; CHECK: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32)
277    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
278    ; CHECK: [[SMIN:%[0-9]+]]:vgpr(<2 x s16>) = G_SMIN [[COPY2]], [[COPY]]
279    ; CHECK: [[COPY3:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
280    ; CHECK: [[SMAX:%[0-9]+]]:vgpr(<2 x s16>) = G_SMAX [[COPY3]], [[SMIN]]
281    ; CHECK: $vgpr0 = COPY [[SMAX]](<2 x s16>)
282    ; CHECK: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
283    ; CHECK: S_SETPC_B64_return [[COPY4]], implicit $vgpr0
284    %0:vgpr(<2 x s16>) = COPY $vgpr0
285    %1:sgpr_64 = COPY $sgpr30_sgpr31
286    %9:sgpr(s32) = G_CONSTANT i32 17
287    %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %9(s32), %9(s32)
288    %10:sgpr(s32) = G_CONSTANT i32 -12
289    %5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %10(s32), %10(s32)
290    %11:vgpr(<2 x s16>) = COPY %2(<2 x s16>)
291    %4:vgpr(<2 x s16>) = G_SMIN %11, %0
292    %12:vgpr(<2 x s16>) = COPY %5(<2 x s16>)
293    %7:vgpr(<2 x s16>) = G_SMAX %12, %4
294    $vgpr0 = COPY %7(<2 x s16>)
295    %8:ccr_sgpr_64 = COPY %1
296    S_SETPC_B64_return %8, implicit $vgpr0
297...
298
299---
300name: test_uniform_min_max
301legalized: true
302regBankSelected: true
303tracksRegLiveness: true
304body: |
305  bb.1:
306    liveins: $sgpr2
307
308    ; CHECK-LABEL: name: test_uniform_min_max
309    ; CHECK: liveins: $sgpr2
310    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
311    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12
312    ; CHECK: [[SMAX:%[0-9]+]]:sgpr(s32) = G_SMAX [[COPY]], [[C]]
313    ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
314    ; CHECK: [[SMIN:%[0-9]+]]:sgpr(s32) = G_SMIN [[SMAX]], [[C1]]
315    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[SMIN]](s32)
316    ; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
317    ; CHECK: $sgpr0 = COPY [[INT]](s32)
318    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
319    %0:sgpr(s32) = COPY $sgpr2
320    %3:sgpr(s32) = G_CONSTANT i32 -12
321    %4:sgpr(s32) = G_SMAX %0, %3
322    %5:sgpr(s32) = G_CONSTANT i32 17
323    %6:sgpr(s32) = G_SMIN %4, %5
324    %8:vgpr(s32) = COPY %6(s32)
325    %7:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), %8(s32)
326    $sgpr0 = COPY %7(s32)
327    SI_RETURN_TO_EPILOG implicit $sgpr0
328...
329