1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
3# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
4
5---
6name: interp_mov_ss
7legalized: true
8tracksRegLiveness: true
9
10body: |
11  bb.0:
12    liveins: $sgpr0, $sgpr1
13    ; CHECK-LABEL: name: interp_mov_ss
14    ; CHECK: liveins: $sgpr0, $sgpr1
15    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
16    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
17    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
18    ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.mov), [[COPY2]](s32), 1, 1, [[COPY1]](s32)
19    %0:_(s32) = COPY $sgpr0
20    %1:_(s32) = COPY $sgpr1
21    %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.mov), %0, 1, 1, %1
22...
23
24---
25name: interp_mov_sv
26legalized: true
27tracksRegLiveness: true
28
29body: |
30  bb.0:
31    liveins: $sgpr0, $vgpr0
32    ; CHECK-LABEL: name: interp_mov_sv
33    ; CHECK: liveins: $sgpr0, $vgpr0
34    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
35    ; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY]](s32), implicit $exec
36    ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.mov), 0, 1, 1, [[V_READFIRSTLANE_B32_]](s32)
37    %0:_(s32) = COPY $vgpr0
38    %1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.mov), 0, 1, 1, %0
39...
40