1; FIXME: Need to add support for mubuf stores to enable this on SI. 2; XUN: llc < %s -march=amdgcn -mcpu=tahiti -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefixes=SI,GCN %s 3; RUN: llc < %s -march=amdgcn -mcpu=bonaire -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefixes=CI,GCN,SICIVI %s 4; RUN: llc < %s -march=amdgcn -mcpu=tonga -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefixes=VI,GCN,SICIVI %s 5; RUN: llc -march=amdgcn -mcpu=gfx900 -show-mc-encoding -verify-machineinstrs -global-isel < %s | FileCheck --check-prefixes=GFX9_10,GCN,VIGFX9_10,SIVIGFX9_10 %s 6; RUN: llc -march=amdgcn -mcpu=gfx1010 -show-mc-encoding -verify-machineinstrs -global-isel < %s | FileCheck --check-prefixes=GFX9_10,GCN,VIGFX9_10,SIVIGFX9_10 %s 7 8; SMRD load with an immediate offset. 9; GCN-LABEL: {{^}}smrd0: 10; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x1 ; encoding: [0x01 11; VIGFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4 12define amdgpu_kernel void @smrd0(i32 addrspace(4)* %ptr) { 13entry: 14 %0 = getelementptr i32, i32 addrspace(4)* %ptr, i64 1 15 %1 = load i32, i32 addrspace(4)* %0 16 store i32 %1, i32 addrspace(1)* undef 17 ret void 18} 19 20; SMRD load with the largest possible immediate offset. 21; GCN-LABEL: {{^}}smrd1: 22; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff,0x{{[0-9]+[137]}} 23; VIGFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc 24define amdgpu_kernel void @smrd1(i32 addrspace(4)* %ptr) { 25entry: 26 %0 = getelementptr i32, i32 addrspace(4)* %ptr, i64 255 27 %1 = load i32, i32 addrspace(4)* %0 28 store i32 %1, i32 addrspace(1)* undef 29 ret void 30} 31 32; SMRD load with an offset greater than the largest possible immediate. 33; GCN-LABEL: {{^}}smrd2: 34; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400 35; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]] 36; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100 37; VIGFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400 38; GCN: s_endpgm 39define amdgpu_kernel void @smrd2(i32 addrspace(4)* %ptr) { 40entry: 41 %0 = getelementptr i32, i32 addrspace(4)* %ptr, i64 256 42 %1 = load i32, i32 addrspace(4)* %0 43 store i32 %1, i32 addrspace(1)* undef 44 ret void 45} 46 47; SMRD load with a 64-bit offset 48; GCN-LABEL: {{^}}smrd3: 49; FIXME: There are too many copies here because we don't fold immediates 50; through REG_SEQUENCE 51; XSI: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[{{[0-9]:[0-9]}}], 0xb ; encoding: [0x0b 52; TODO: Add VI checks 53; XGCN: s_endpgm 54define amdgpu_kernel void @smrd3(i32 addrspace(4)* %ptr) { 55entry: 56 %0 = getelementptr i32, i32 addrspace(4)* %ptr, i64 4294967296 ; 2 ^ 32 57 %1 = load i32, i32 addrspace(4)* %0 58 store i32 %1, i32 addrspace(1)* undef 59 ret void 60} 61 62; SMRD load with the largest possible immediate offset on VI 63; GCN-LABEL: {{^}}smrd4: 64; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc 65; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]] 66; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff 67; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc 68; GFX9_10: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc 69; GFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]] 70define amdgpu_kernel void @smrd4(i32 addrspace(4)* %ptr) { 71entry: 72 %0 = getelementptr i32, i32 addrspace(4)* %ptr, i64 262143 73 %1 = load i32, i32 addrspace(4)* %0 74 store i32 %1, i32 addrspace(1)* undef 75 ret void 76} 77 78; SMRD load with an offset greater than the largest possible immediate on VI 79; GCN-LABEL: {{^}}smrd5: 80; SIVIGFX9_10: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000 81; SIVIGFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]] 82; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000 83; GCN: s_endpgm 84define amdgpu_kernel void @smrd5(i32 addrspace(4)* %ptr) { 85entry: 86 %0 = getelementptr i32, i32 addrspace(4)* %ptr, i64 262144 87 %1 = load i32, i32 addrspace(4)* %0 88 store i32 %1, i32 addrspace(1)* undef 89 ret void 90} 91 92; GFX9_10 can use a signed immediate byte offset 93; GCN-LABEL: {{^}}smrd6: 94; SICIVI: s_add_u32 s{{[0-9]}}, s{{[0-9]}}, -4 95; SICIVI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x0 96; GFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], -0x4 97define amdgpu_kernel void @smrd6(i32 addrspace(1)* %out, i32 addrspace(4)* %ptr) #0 { 98entry: 99 %tmp = getelementptr i32, i32 addrspace(4)* %ptr, i64 -1 100 %tmp1 = load i32, i32 addrspace(4)* %tmp 101 store i32 %tmp1, i32 addrspace(1)* %out 102 ret void 103} 104 105; Don't use a negative SGPR offset 106; GCN-LABEL: {{^}}smrd7: 107; GCN: s_add_u32 s{{[0-9]}}, s{{[0-9]}}, 0xffe00000 108; SICIVI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x0 109; GFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x0 110define amdgpu_kernel void @smrd7(i32 addrspace(1)* %out, i32 addrspace(4)* %ptr) #0 { 111entry: 112 %tmp = getelementptr i32, i32 addrspace(4)* %ptr, i64 -524288 113 %tmp1 = load i32, i32 addrspace(4)* %tmp 114 store i32 %tmp1, i32 addrspace(1)* %out 115 ret void 116} 117