1; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -amdgpu-s-branch-bits=4 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10 %s 2; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -amdgpu-s-branch-bits=4 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s 3 4; Make sure the code size estimate for inline asm is 12-bytes per 5; instruction, rather than 8 in previous generations. 6 7; GCN-LABEL: {{^}}long_forward_branch_gfx10only: 8; GFX9: s_cmp_eq_u32 9; GFX9: s_load_dwordx2 10; GFX9-NEXT: s_cbranch_scc1 11 12; GFX10: s_cmp_eq_u32 13; GFX10-NEXT: s_cbranch_scc0 14; GFX10: s_getpc_b64 15; GFX10: s_add_u32 16; GFX10: s_addc_u32 17; GFX10: s_setpc_b64 18define amdgpu_kernel void @long_forward_branch_gfx10only(i32 addrspace(1)* %arg, i32 %cnd) #0 { 19bb0: 20 %cmp = icmp eq i32 %cnd, 0 21 br i1 %cmp, label %bb3, label %bb2 ; +9 dword branch 22 23bb2: 24 ; Estimated as 40-bytes on gfx10 (requiring a long branch), but 25 ; 16-bytes on gfx9 (allowing a short branch) 26 call void asm sideeffect 27 "v_nop_e64 28 v_nop_e64", ""() #0 29 br label %bb3 30 31bb3: 32 store volatile i32 %cnd, i32 addrspace(1)* %arg 33 ret void 34} 35