1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=SI-SAFE,GCN %s 2; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GCN %s 3 4; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI-SAFE,GCN %s 5; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GCN %s 6 7; GCN-LABEL: {{^}}min_fneg_select_regression_0: 8; GCN-NOT: v_mul 9 10; SI-SAFE: v_max_legacy_f32_e64 [[MIN:v[0-9]+]], -1.0, -v0 11 12; VI-SAFE: v_cmp_nle_f32_e32 vcc, 1.0, v0 13; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc 14; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 15 16; GCN-NONAN: v_max_f32_e64 v0, -v0, -1.0 17define amdgpu_ps float @min_fneg_select_regression_0(float %a, float %b) #0 { 18 %fneg.a = fsub float -0.0, %a 19 %cmp.a = fcmp ult float %a, 1.0 20 %min.a = select i1 %cmp.a, float %fneg.a, float -1.0 21 ret float %min.a 22} 23 24; GCN-LABEL: {{^}}min_fneg_select_regression_posk_0: 25; GCN-NOT: v_mul 26 27; SI-SAFE: v_max_legacy_f32_e64 [[MIN:v[0-9]+]], 1.0, -v0 28 29; VI-SAFE: v_cmp_nle_f32_e32 vcc, -1.0, v0 30; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, -1.0, v0, vcc 31; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 32 33; GCN-NONAN: v_max_f32_e64 v{{[0-9]+}}, -v0, 1.0 34define amdgpu_ps float @min_fneg_select_regression_posk_0(float %a, float %b) #0 { 35 %fneg.a = fsub float -0.0, %a 36 %cmp.a = fcmp ult float %a, -1.0 37 %min.a = select i1 %cmp.a, float %fneg.a, float 1.0 38 ret float %min.a 39} 40 41; GCN-LABEL: {{^}}max_fneg_select_regression_0: 42; GCN-NOT: v_mul 43 44; SI-SAFE: v_min_legacy_f32_e64 [[MIN:v[0-9]+]], -1.0, -v0 45 46; VI-SAFE: v_cmp_nge_f32_e32 vcc, 1.0, v0 47; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc 48; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 49 50; GCN-NONAN: v_min_f32_e64 [[MIN:v[0-9]+]], -v0, -1.0 51define amdgpu_ps float @max_fneg_select_regression_0(float %a) #0 { 52 %fneg.a = fsub float -0.0, %a 53 %cmp.a = fcmp ugt float %a, 1.0 54 %min.a = select i1 %cmp.a, float %fneg.a, float -1.0 55 ret float %min.a 56} 57 58; GCN-LABEL: {{^}}max_fneg_select_regression_posk_0: 59; GCN-NOT: v_mul 60 61; SI-SAFE: v_min_legacy_f32_e64 [[MIN:v[0-9]+]], 1.0, -v0 62 63; VI-SAFE: v_cmp_nge_f32_e32 vcc, -1.0, v0 64; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, -1.0, v0, vcc 65; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 66 67; GCN-NONAN: v_min_f32_e64 [[MIN:v[0-9]+]], -v0, 1.0 68define amdgpu_ps float @max_fneg_select_regression_posk_0(float %a) #0 { 69 %fneg.a = fsub float -0.0, %a 70 %cmp.a = fcmp ugt float %a, -1.0 71 %min.a = select i1 %cmp.a, float %fneg.a, float 1.0 72 ret float %min.a 73} 74 75attributes #0 = { nounwind } 76attributes #1 = { nounwind readnone } 77