1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s 3 4; Test a selectcc with i32 LHS/RHS and float True/False 5 6define amdgpu_kernel void @test(float addrspace(1)* %out, i32 addrspace(1)* %in) { 7; CHECK-LABEL: test: 8; CHECK: ; %bb.0: ; %entry 9; CHECK-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] 10; CHECK-NEXT: TEX 0 @6 11; CHECK-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[] 12; CHECK-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 13; CHECK-NEXT: CF_END 14; CHECK-NEXT: PAD 15; CHECK-NEXT: Fetch clause starting at 6: 16; CHECK-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 17; CHECK-NEXT: ALU clause starting at 8: 18; CHECK-NEXT: MOV * T0.X, KC0[2].Z, 19; CHECK-NEXT: ALU clause starting at 9: 20; CHECK-NEXT: SETGT_INT * T0.W, 0.0, T0.X, 21; CHECK-NEXT: CNDE_INT T0.X, PV.W, literal.x, 0.0, 22; CHECK-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, 23; CHECK-NEXT: 1065353216(1.000000e+00), 2(2.802597e-45) 24entry: 25 %0 = load i32, i32 addrspace(1)* %in 26 %1 = icmp sge i32 %0, 0 27 %2 = select i1 %1, float 1.0, float 0.0 28 store float %2, float addrspace(1)* %out 29 ret void 30} 31