1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600 3--- | 4 5 define void @fabs_v4f32(<4 x float>* %a, <4 x float>* %c) { entry: ret void } 6 define void @fabs_v2f64(<2 x double>* %a, <2 x double>* %c) { entry: ret void } 7 8... 9--- 10name: fabs_v4f32 11alignment: 4 12legalized: true 13regBankSelected: true 14tracksRegLiveness: true 15body: | 16 bb.1.entry: 17 liveins: $a0, $a1 18 19 ; P5600-LABEL: name: fabs_v4f32 20 ; P5600: liveins: $a0, $a1 21 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 22 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 23 ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a) 24 ; P5600: [[FABS_W:%[0-9]+]]:msa128w = FABS_W [[LD_W]] 25 ; P5600: ST_W [[FABS_W]], [[COPY1]], 0 :: (store (<4 x s32>) into %ir.c) 26 ; P5600: RetRA 27 %0:gprb(p0) = COPY $a0 28 %1:gprb(p0) = COPY $a1 29 %2:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a) 30 %3:fprb(<4 x s32>) = G_FABS %2 31 G_STORE %3(<4 x s32>), %1(p0) :: (store (<4 x s32>) into %ir.c) 32 RetRA 33 34... 35--- 36name: fabs_v2f64 37alignment: 4 38legalized: true 39regBankSelected: true 40tracksRegLiveness: true 41body: | 42 bb.1.entry: 43 liveins: $a0, $a1 44 45 ; P5600-LABEL: name: fabs_v2f64 46 ; P5600: liveins: $a0, $a1 47 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 48 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 49 ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a) 50 ; P5600: [[FABS_D:%[0-9]+]]:msa128d = FABS_D [[LD_D]] 51 ; P5600: ST_D [[FABS_D]], [[COPY1]], 0 :: (store (<2 x s64>) into %ir.c) 52 ; P5600: RetRA 53 %0:gprb(p0) = COPY $a0 54 %1:gprb(p0) = COPY $a1 55 %2:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a) 56 %3:fprb(<2 x s64>) = G_FABS %2 57 G_STORE %3(<2 x s64>), %1(p0) :: (store (<2 x s64>) into %ir.c) 58 RetRA 59 60... 61