1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -O0 -mattr=+mve %s -o - | FileCheck %s
3
4declare void @external_function()
5
6define arm_aapcs_vfpcc void @spill_vector_i32(<4 x i32> %v, <4 x i32>* %p) {
7; CHECK-LABEL: spill_vector_i32:
8; CHECK:       @ %bb.0: @ %entry
9; CHECK-NEXT:    .save {r7, lr}
10; CHECK-NEXT:    push {r7, lr}
11; CHECK-NEXT:    .pad #40
12; CHECK-NEXT:    sub sp, #40
13; CHECK-NEXT:    str r0, [sp, #12] @ 4-byte Spill
14; CHECK-NEXT:    vstrw.32 q0, [sp, #16] @ 16-byte Spill
15; CHECK-NEXT:    bl external_function
16; CHECK-NEXT:    ldr r0, [sp, #12] @ 4-byte Reload
17; CHECK-NEXT:    vldrw.u32 q0, [sp, #16] @ 16-byte Reload
18; CHECK-NEXT:    vstrw.32 q0, [r0]
19; CHECK-NEXT:    add sp, #40
20; CHECK-NEXT:    pop {r7, pc}
21entry:
22  call void @external_function()
23  store <4 x i32> %v, <4 x i32>* %p, align 4
24  ret void
25}
26
27define arm_aapcs_vfpcc void @spill_vector_i16(<8 x i16> %v, <8 x i16>* %p) {
28; CHECK-LABEL: spill_vector_i16:
29; CHECK:       @ %bb.0: @ %entry
30; CHECK-NEXT:    .save {r7, lr}
31; CHECK-NEXT:    push {r7, lr}
32; CHECK-NEXT:    .pad #40
33; CHECK-NEXT:    sub sp, #40
34; CHECK-NEXT:    str r0, [sp, #12] @ 4-byte Spill
35; CHECK-NEXT:    vstrw.32 q0, [sp, #16] @ 16-byte Spill
36; CHECK-NEXT:    bl external_function
37; CHECK-NEXT:    ldr r0, [sp, #12] @ 4-byte Reload
38; CHECK-NEXT:    vldrw.u32 q0, [sp, #16] @ 16-byte Reload
39; CHECK-NEXT:    vstrh.16 q0, [r0]
40; CHECK-NEXT:    add sp, #40
41; CHECK-NEXT:    pop {r7, pc}
42entry:
43  call void @external_function()
44  store <8 x i16> %v, <8 x i16>* %p, align 2
45  ret void
46}
47
48define arm_aapcs_vfpcc void @spill_vector_i8(<16 x i8> %v, <16 x i8>* %p) {
49; CHECK-LABEL: spill_vector_i8:
50; CHECK:       @ %bb.0: @ %entry
51; CHECK-NEXT:    .save {r7, lr}
52; CHECK-NEXT:    push {r7, lr}
53; CHECK-NEXT:    .pad #40
54; CHECK-NEXT:    sub sp, #40
55; CHECK-NEXT:    str r0, [sp, #12] @ 4-byte Spill
56; CHECK-NEXT:    vstrw.32 q0, [sp, #16] @ 16-byte Spill
57; CHECK-NEXT:    bl external_function
58; CHECK-NEXT:    ldr r0, [sp, #12] @ 4-byte Reload
59; CHECK-NEXT:    vldrw.u32 q0, [sp, #16] @ 16-byte Reload
60; CHECK-NEXT:    vstrb.8 q0, [r0]
61; CHECK-NEXT:    add sp, #40
62; CHECK-NEXT:    pop {r7, pc}
63entry:
64  call void @external_function()
65  store <16 x i8> %v, <16 x i8>* %p, align 1
66  ret void
67}
68
69define arm_aapcs_vfpcc void @spill_vector_i64(<2 x i64> %v, <2 x i64>* %p) {
70; CHECK-LABEL: spill_vector_i64:
71; CHECK:       @ %bb.0: @ %entry
72; CHECK-NEXT:    .save {r7, lr}
73; CHECK-NEXT:    push {r7, lr}
74; CHECK-NEXT:    .pad #40
75; CHECK-NEXT:    sub sp, #40
76; CHECK-NEXT:    str r0, [sp, #12] @ 4-byte Spill
77; CHECK-NEXT:    vstrw.32 q0, [sp, #16] @ 16-byte Spill
78; CHECK-NEXT:    bl external_function
79; CHECK-NEXT:    ldr r0, [sp, #12] @ 4-byte Reload
80; CHECK-NEXT:    vldrw.u32 q0, [sp, #16] @ 16-byte Reload
81; CHECK-NEXT:    vstrw.32 q0, [r0]
82; CHECK-NEXT:    add sp, #40
83; CHECK-NEXT:    pop {r7, pc}
84entry:
85  call void @external_function()
86  store <2 x i64> %v, <2 x i64>* %p, align 8
87  ret void
88}
89
90define arm_aapcs_vfpcc void @spill_vector_f32(<4 x float> %v, <4 x float>* %p) {
91; CHECK-LABEL: spill_vector_f32:
92; CHECK:       @ %bb.0: @ %entry
93; CHECK-NEXT:    .save {r7, lr}
94; CHECK-NEXT:    push {r7, lr}
95; CHECK-NEXT:    .pad #40
96; CHECK-NEXT:    sub sp, #40
97; CHECK-NEXT:    str r0, [sp, #12] @ 4-byte Spill
98; CHECK-NEXT:    vstrw.32 q0, [sp, #16] @ 16-byte Spill
99; CHECK-NEXT:    bl external_function
100; CHECK-NEXT:    ldr r0, [sp, #12] @ 4-byte Reload
101; CHECK-NEXT:    vldrw.u32 q0, [sp, #16] @ 16-byte Reload
102; CHECK-NEXT:    vstrw.32 q0, [r0]
103; CHECK-NEXT:    add sp, #40
104; CHECK-NEXT:    pop {r7, pc}
105entry:
106  call void @external_function()
107  store <4 x float> %v, <4 x float>* %p, align 8
108  ret void
109}
110
111define arm_aapcs_vfpcc void @spill_vector_f16(<8 x half> %v, <8 x half>* %p) {
112; CHECK-LABEL: spill_vector_f16:
113; CHECK:       @ %bb.0: @ %entry
114; CHECK-NEXT:    .save {r7, lr}
115; CHECK-NEXT:    push {r7, lr}
116; CHECK-NEXT:    .pad #40
117; CHECK-NEXT:    sub sp, #40
118; CHECK-NEXT:    str r0, [sp, #12] @ 4-byte Spill
119; CHECK-NEXT:    vstrw.32 q0, [sp, #16] @ 16-byte Spill
120; CHECK-NEXT:    bl external_function
121; CHECK-NEXT:    ldr r0, [sp, #12] @ 4-byte Reload
122; CHECK-NEXT:    vldrw.u32 q0, [sp, #16] @ 16-byte Reload
123; CHECK-NEXT:    vstrw.32 q0, [r0]
124; CHECK-NEXT:    add sp, #40
125; CHECK-NEXT:    pop {r7, pc}
126entry:
127  call void @external_function()
128  store <8 x half> %v, <8 x half>* %p, align 8
129  ret void
130}
131
132define arm_aapcs_vfpcc void @spill_vector_f64(<2 x double> %v, <2 x double>* %p) {
133; CHECK-LABEL: spill_vector_f64:
134; CHECK:       @ %bb.0: @ %entry
135; CHECK-NEXT:    .save {r7, lr}
136; CHECK-NEXT:    push {r7, lr}
137; CHECK-NEXT:    .pad #40
138; CHECK-NEXT:    sub sp, #40
139; CHECK-NEXT:    str r0, [sp, #12] @ 4-byte Spill
140; CHECK-NEXT:    vstrw.32 q0, [sp, #16] @ 16-byte Spill
141; CHECK-NEXT:    bl external_function
142; CHECK-NEXT:    ldr r0, [sp, #12] @ 4-byte Reload
143; CHECK-NEXT:    vldrw.u32 q0, [sp, #16] @ 16-byte Reload
144; CHECK-NEXT:    vstrw.32 q0, [r0]
145; CHECK-NEXT:    add sp, #40
146; CHECK-NEXT:    pop {r7, pc}
147entry:
148  call void @external_function()
149  store <2 x double> %v, <2 x double>* %p, align 8
150  ret void
151}
152