1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
2
3// --------------------------------------------------------------------------//
4// Source and Destination Registers must match
5
6suqadd z0.b, p0/m, z1.b, z2.b
7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
8// CHECK-NEXT: suqadd z0.b, p0/m, z1.b, z2.b
9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10
11
12// --------------------------------------------------------------------------//
13// Element sizes must match
14
15suqadd z0.b, p0/m, z0.d, z1.d
16// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
17// CHECK-NEXT: suqadd z0.b, p0/m, z0.d, z1.d
18// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
19
20suqadd z0.b, p0/m, z0.b, z1.h
21// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
22// CHECK-NEXT: suqadd z0.b, p0/m, z0.b, z1.h
23// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
24
25
26// --------------------------------------------------------------------------//
27// Invalid predicate
28
29suqadd z0.b, p0/z, z0.b, z1.b
30// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
31// CHECK-NEXT: suqadd z0.b, p0/z, z0.b, z1.b
32// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
33
34suqadd z0.b, p8/m, z0.b, z1.b
35// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
36// CHECK-NEXT: suqadd z0.b, p8/m, z0.b, z1.b
37// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
38