1//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12//===----------------------------------------------------------------------===//
13// Target-independent interfaces which we are implementing.
14//===----------------------------------------------------------------------===//
15
16include "llvm/Target/Target.td"
17
18//===----------------------------------------------------------------------===//
19// AArch64 Subtarget features.
20//
21
22def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
23                                       "Enable ARMv8 FP">;
24
25def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
26  "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
27
28def FeatureSM4 : SubtargetFeature<
29    "sm4", "HasSM4", "true",
30    "Enable SM3 and SM4 support", [FeatureNEON]>;
31
32def FeatureSHA2 : SubtargetFeature<
33    "sha2", "HasSHA2", "true",
34    "Enable SHA1 and SHA256 support", [FeatureNEON]>;
35
36def FeatureSHA3 : SubtargetFeature<
37    "sha3", "HasSHA3", "true",
38    "Enable SHA512 and SHA3 support", [FeatureNEON, FeatureSHA2]>;
39
40def FeatureAES : SubtargetFeature<
41    "aes", "HasAES", "true",
42    "Enable AES support", [FeatureNEON]>;
43
44// Crypto has been split up and any combination is now valid (see the
45// crypto definitions above). Also, crypto is now context sensitive:
46// it has a different meaning for e.g. Armv8.4 than it has for Armv8.2.
47// Therefore, we rely on Clang, the user interacing tool, to pass on the
48// appropriate crypto options. But here in the backend, crypto has very little
49// meaning anymore. We kept the Crypto definition here for backward
50// compatibility, and now imply features SHA2 and AES, which was the
51// "traditional" meaning of Crypto.
52def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
53  "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>;
54
55def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
56  "Enable ARMv8 CRC-32 checksum instructions">;
57
58def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
59  "Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
60
61def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
62  "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">;
63
64def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true",
65  "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">;
66
67def FeaturePAN : SubtargetFeature<
68    "pan", "HasPAN", "true",
69    "Enables ARM v8.1 Privileged Access-Never extension">;
70
71def FeatureLOR : SubtargetFeature<
72    "lor", "HasLOR", "true",
73    "Enables ARM v8.1 Limited Ordering Regions extension">;
74
75def FeatureVH : SubtargetFeature<
76    "vh", "HasVH", "true",
77    "Enables ARM v8.1 Virtual Host extension">;
78
79def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
80  "Enable ARMv8 PMUv3 Performance Monitors extension">;
81
82def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
83  "Full FP16", [FeatureFPARMv8]>;
84
85def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true",
86  "Enable FP16 FML instructions", [FeatureFullFP16]>;
87
88def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
89  "Enable Statistical Profiling extension">;
90
91def FeaturePAN_RWV : SubtargetFeature<
92    "pan-rwv", "HasPAN_RWV", "true",
93    "Enable v8.2 PAN s1e1R and s1e1W Variants",
94    [FeaturePAN]>;
95
96// UAO PState
97def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true",
98    "Enable v8.2 UAO PState">;
99
100def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP",
101    "true", "Enable v8.2 data Cache Clean to Point of Persistence" >;
102
103def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true",
104  "Enable Scalable Vector Extension (SVE) instructions", [FeatureFullFP16]>;
105
106// This flag is currently still labeled as Experimental, but when fully
107// implemented this should tell the compiler to use the zeroing pseudos to
108// benefit from the reverse instructions (e.g. SUB vs SUBR) if the inactive
109// lanes are known to be zero. The pseudos will then be expanded using the
110// MOVPRFX instruction to zero the inactive lanes. This feature should only be
111// enabled if MOVPRFX instructions are known to merge with the destructive
112// operations they prefix.
113//
114// This feature could similarly be extended to support cheap merging of _any_
115// value into the inactive lanes using the MOVPRFX instruction that uses
116// merging-predication.
117def FeatureExperimentalZeroingPseudos
118    : SubtargetFeature<"use-experimental-zeroing-pseudos",
119                       "UseExperimentalZeroingPseudos", "true",
120                       "Hint to the compiler that the MOVPRFX instruction is "
121                       "merged with destructive operations",
122                       []>;
123
124def FeatureSVE2 : SubtargetFeature<"sve2", "HasSVE2", "true",
125  "Enable Scalable Vector Extension 2 (SVE2) instructions", [FeatureSVE]>;
126
127def FeatureSVE2AES : SubtargetFeature<"sve2-aes", "HasSVE2AES", "true",
128  "Enable AES SVE2 instructions", [FeatureSVE2, FeatureAES]>;
129
130def FeatureSVE2SM4 : SubtargetFeature<"sve2-sm4", "HasSVE2SM4", "true",
131  "Enable SM4 SVE2 instructions", [FeatureSVE2, FeatureSM4]>;
132
133def FeatureSVE2SHA3 : SubtargetFeature<"sve2-sha3", "HasSVE2SHA3", "true",
134  "Enable SHA3 SVE2 instructions", [FeatureSVE2, FeatureSHA3]>;
135
136def FeatureSVE2BitPerm : SubtargetFeature<"sve2-bitperm", "HasSVE2BitPerm", "true",
137  "Enable bit permutation SVE2 instructions", [FeatureSVE2]>;
138
139def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
140                                        "Has zero-cycle register moves">;
141
142def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true",
143                                        "Has zero-cycle zeroing instructions for generic registers">;
144
145def FeatureZCZeroingFP : SubtargetFeature<"zcz-fp", "HasZeroCycleZeroingFP", "true",
146                                        "Has zero-cycle zeroing instructions for FP registers">;
147
148def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
149                                        "Has zero-cycle zeroing instructions",
150                                        [FeatureZCZeroingGP, FeatureZCZeroingFP]>;
151
152/// ... but the floating-point version doesn't quite work in rare cases on older
153/// CPUs.
154def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround",
155    "HasZeroCycleZeroingFPWorkaround", "true",
156    "The zero-cycle floating-point zeroing instruction has a bug">;
157
158def FeatureStrictAlign : SubtargetFeature<"strict-align",
159                                          "StrictAlign", "true",
160                                          "Disallow all unaligned memory "
161                                          "access">;
162
163foreach i = {1-7,9-15,18,20-28,30} in
164    def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true",
165                                             "Reserve X"#i#", making it unavailable "
166                                             "as a GPR">;
167
168foreach i = {8-15,18} in
169    def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i,
170         "CustomCallSavedXRegs["#i#"]", "true", "Make X"#i#" callee saved.">;
171
172def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
173                                    "Use alias analysis during codegen">;
174
175def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
176    "true",
177    "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
178
179def FeaturePredictableSelectIsExpensive : SubtargetFeature<
180    "predictable-select-expensive", "PredictableSelectIsExpensive", "true",
181    "Prefer likely predicted branches over selects">;
182
183def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move",
184    "CustomAsCheapAsMove", "true",
185    "Use custom handling of cheap instructions">;
186
187def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move",
188    "ExynosAsCheapAsMove", "true",
189    "Use Exynos specific handling of cheap instructions",
190    [FeatureCustomCheapAsMoveHandling]>;
191
192def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
193    "UsePostRAScheduler", "true", "Schedule again after register allocation">;
194
195def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
196    "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">;
197
198def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128",
199    "Paired128IsSlow", "true", "Paired 128 bit loads and stores are slow">;
200
201def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "STRQroIsSlow",
202    "true", "STR of Q register with register offset is slow">;
203
204def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
205    "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
206    "true", "Use alternative pattern for sextload convert to f32">;
207
208def FeatureArithmeticBccFusion : SubtargetFeature<
209    "arith-bcc-fusion", "HasArithmeticBccFusion", "true",
210    "CPU fuses arithmetic+bcc operations">;
211
212def FeatureArithmeticCbzFusion : SubtargetFeature<
213    "arith-cbz-fusion", "HasArithmeticCbzFusion", "true",
214    "CPU fuses arithmetic + cbz/cbnz operations">;
215
216def FeatureFuseAddress : SubtargetFeature<
217    "fuse-address", "HasFuseAddress", "true",
218    "CPU fuses address generation and memory operations">;
219
220def FeatureFuseAES : SubtargetFeature<
221    "fuse-aes", "HasFuseAES", "true",
222    "CPU fuses AES crypto operations">;
223
224def FeatureFuseArithmeticLogic : SubtargetFeature<
225    "fuse-arith-logic", "HasFuseArithmeticLogic", "true",
226    "CPU fuses arithmetic and logic operations">;
227
228def FeatureFuseCCSelect : SubtargetFeature<
229    "fuse-csel", "HasFuseCCSelect", "true",
230    "CPU fuses conditional select operations">;
231
232def FeatureFuseCryptoEOR : SubtargetFeature<
233    "fuse-crypto-eor", "HasFuseCryptoEOR", "true",
234    "CPU fuses AES/PMULL and EOR operations">;
235
236def FeatureFuseLiterals : SubtargetFeature<
237    "fuse-literals", "HasFuseLiterals", "true",
238    "CPU fuses literal generation operations">;
239
240def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
241    "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
242    "Disable latency scheduling heuristic">;
243
244def FeatureForce32BitJumpTables
245   : SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true",
246                      "Force jump table entries to be 32-bits wide except at MinSize">;
247
248def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true",
249                                   "Enable support for RCPC extension">;
250
251def FeatureUseRSqrt : SubtargetFeature<
252    "use-reciprocal-square-root", "UseRSqrt", "true",
253    "Use the reciprocal square root approximation">;
254
255def FeatureDotProd : SubtargetFeature<
256    "dotprod", "HasDotProd", "true",
257    "Enable dot product support">;
258
259def FeaturePA : SubtargetFeature<
260    "pa", "HasPA", "true",
261    "Enable v8.3-A Pointer Authentication extension">;
262
263def FeatureJS : SubtargetFeature<
264    "jsconv", "HasJS", "true",
265    "Enable v8.3-A JavaScript FP conversion instructions",
266    [FeatureFPARMv8]>;
267
268def FeatureCCIDX : SubtargetFeature<
269    "ccidx", "HasCCIDX", "true",
270    "Enable v8.3-A Extend of the CCSIDR number of sets">;
271
272def FeatureComplxNum : SubtargetFeature<
273    "complxnum", "HasComplxNum", "true",
274    "Enable v8.3-A Floating-point complex number support",
275    [FeatureNEON]>;
276
277def FeatureNV : SubtargetFeature<
278    "nv", "HasNV", "true",
279    "Enable v8.4-A Nested Virtualization Enchancement">;
280
281def FeatureRASv8_4 : SubtargetFeature<
282    "rasv8_4", "HasRASv8_4", "true",
283    "Enable v8.4-A Reliability, Availability and Serviceability extension",
284    [FeatureRAS]>;
285
286def FeatureMPAM : SubtargetFeature<
287    "mpam", "HasMPAM", "true",
288    "Enable v8.4-A Memory system Partitioning and Monitoring extension">;
289
290def FeatureDIT : SubtargetFeature<
291    "dit", "HasDIT", "true",
292    "Enable v8.4-A Data Independent Timing instructions">;
293
294def FeatureTRACEV8_4 : SubtargetFeature<
295    "tracev8.4", "HasTRACEV8_4", "true",
296    "Enable v8.4-A Trace extension">;
297
298def FeatureAM : SubtargetFeature<
299    "am", "HasAM", "true",
300    "Enable v8.4-A Activity Monitors extension">;
301
302def FeatureAMVS : SubtargetFeature<
303    "amvs", "HasAMVS", "true",
304    "Enable v8.6-A Activity Monitors Virtualization support",
305    [FeatureAM]>;
306
307def FeatureSEL2 : SubtargetFeature<
308    "sel2", "HasSEL2", "true",
309    "Enable v8.4-A Secure Exception Level 2 extension">;
310
311def FeaturePMU : SubtargetFeature<
312    "pmu", "HasPMU", "true",
313    "Enable v8.4-A PMU extension">;
314
315def FeatureTLB_RMI : SubtargetFeature<
316    "tlb-rmi", "HasTLB_RMI", "true",
317    "Enable v8.4-A TLB Range and Maintenance Instructions">;
318
319def FeatureFMI : SubtargetFeature<
320    "fmi", "HasFMI", "true",
321    "Enable v8.4-A Flag Manipulation Instructions">;
322
323// 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset
324def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true",
325    "Enable v8.4-A RCPC instructions with Immediate Offsets",
326    [FeatureRCPC]>;
327
328def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
329                                        "NegativeImmediates", "false",
330                                        "Convert immediates and instructions "
331                                        "to their negated or complemented "
332                                        "equivalent when the immediate does "
333                                        "not fit in the encoding.">;
334
335def FeatureLSLFast : SubtargetFeature<
336    "lsl-fast", "HasLSLFast", "true",
337    "CPU has a fastpath logical shift of up to 3 places">;
338
339def FeatureAggressiveFMA :
340  SubtargetFeature<"aggressive-fma",
341                   "HasAggressiveFMA",
342                   "true",
343                   "Enable Aggressive FMA for floating-point.">;
344
345def FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true",
346  "Enable alternative NZCV format for floating point comparisons">;
347
348def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true",
349  "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to "
350  "an integer (in FP format) forcing it to fit into a 32- or 64-bit int" >;
351
352def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict",
353  "true", "Enable architectural speculation restriction" >;
354
355def FeatureSB : SubtargetFeature<"sb", "HasSB",
356  "true", "Enable v8.5 Speculation Barrier" >;
357
358def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS",
359  "true", "Enable Speculative Store Bypass Safe bit" >;
360
361def FeaturePredRes : SubtargetFeature<"predres", "HasPredRes", "true",
362  "Enable v8.5a execution and data prediction invalidation instructions" >;
363
364def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP",
365    "true", "Enable v8.5 Cache Clean to Point of Deep Persistence" >;
366
367def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI",
368    "true", "Enable Branch Target Identification" >;
369
370def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen",
371    "true", "Enable Random Number generation instructions" >;
372
373def FeatureMTE : SubtargetFeature<"mte", "HasMTE",
374    "true", "Enable Memory Tagging Extension" >;
375
376def FeatureTRBE : SubtargetFeature<"trbe", "HasTRBE",
377    "true", "Enable Trace Buffer Extension">;
378
379def FeatureETE : SubtargetFeature<"ete", "HasETE",
380    "true", "Enable Embedded Trace Extension",
381    [FeatureTRBE]>;
382
383def FeatureTME : SubtargetFeature<"tme", "HasTME",
384    "true", "Enable Transactional Memory Extension" >;
385
386def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
387    "AllowTaggedGlobals",
388    "true", "Use an instruction sequence for taking the address of a global "
389    "that allows a memory tag in the upper address bits">;
390
391def FeatureBF16 : SubtargetFeature<"bf16", "HasBF16",
392    "true", "Enable BFloat16 Extension" >;
393
394def FeatureMatMulInt8 : SubtargetFeature<"i8mm", "HasMatMulInt8",
395    "true", "Enable Matrix Multiply Int8 Extension">;
396
397def FeatureMatMulFP32 : SubtargetFeature<"f32mm", "HasMatMulFP32",
398    "true", "Enable Matrix Multiply FP32 Extension", [FeatureSVE]>;
399
400def FeatureMatMulFP64 : SubtargetFeature<"f64mm", "HasMatMulFP64",
401    "true", "Enable Matrix Multiply FP64 Extension", [FeatureSVE]>;
402
403def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
404    "true", "Enable fine grained virtualization traps extension">;
405
406def FeatureEnhancedCounterVirtualization :
407      SubtargetFeature<"ecv", "HasEnhancedCounterVirtualization",
408      "true", "Enable enhanced counter virtualization extension">;
409
410//===----------------------------------------------------------------------===//
411// Architectures.
412//
413
414def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
415  "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM,
416  FeaturePAN, FeatureLOR, FeatureVH]>;
417
418def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
419  "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO,
420  FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>;
421
422def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
423  "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePA,
424  FeatureJS, FeatureCCIDX, FeatureComplxNum]>;
425
426def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
427  "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd,
428  FeatureNV, FeatureRASv8_4, FeatureMPAM, FeatureDIT,
429  FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeaturePMU, FeatureTLB_RMI,
430  FeatureFMI, FeatureRCPC_IMMO]>;
431
432def HasV8_5aOps : SubtargetFeature<
433  "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
434  [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
435   FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist,
436   FeatureBranchTargetId]>;
437
438def HasV8_6aOps : SubtargetFeature<
439  "v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions",
440
441  [HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps,
442   FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>;
443
444//===----------------------------------------------------------------------===//
445// Register File Description
446//===----------------------------------------------------------------------===//
447
448include "AArch64RegisterInfo.td"
449include "AArch64RegisterBanks.td"
450include "AArch64CallingConvention.td"
451
452//===----------------------------------------------------------------------===//
453// Instruction Descriptions
454//===----------------------------------------------------------------------===//
455
456include "AArch64Schedule.td"
457include "AArch64InstrInfo.td"
458include "AArch64SchedPredicates.td"
459include "AArch64SchedPredExynos.td"
460include "AArch64Combine.td"
461
462def AArch64InstrInfo : InstrInfo;
463
464//===----------------------------------------------------------------------===//
465// Named operands for MRS/MSR/TLBI/...
466//===----------------------------------------------------------------------===//
467
468include "AArch64SystemOperands.td"
469
470//===----------------------------------------------------------------------===//
471// Access to privileged registers
472//===----------------------------------------------------------------------===//
473
474foreach i = 1-3 in
475def FeatureUseEL#i#ForTP : SubtargetFeature<"tpidr-el"#i, "UseEL"#i#"ForTP",
476  "true", "Permit use of TPIDR_EL"#i#" for the TLS base">;
477
478//===----------------------------------------------------------------------===//
479// Control codegen mitigation against Straight Line Speculation vulnerability.
480//===----------------------------------------------------------------------===//
481
482def FeatureHardenSlsRetBr : SubtargetFeature<"harden-sls-retbr",
483  "HardenSlsRetBr", "true",
484  "Harden against straight line speculation across RET and BR instructions">;
485def FeatureHardenSlsBlr : SubtargetFeature<"harden-sls-blr",
486  "HardenSlsBlr", "true",
487  "Harden against straight line speculation across BLR instructions">;
488
489//===----------------------------------------------------------------------===//
490// AArch64 Processors supported.
491//
492
493//===----------------------------------------------------------------------===//
494// Unsupported features to disable for scheduling models
495//===----------------------------------------------------------------------===//
496
497class AArch64Unsupported { list<Predicate> F; }
498
499def SVEUnsupported : AArch64Unsupported {
500  let F = [HasSVE, HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3,
501           HasSVE2BitPerm];
502}
503
504def PAUnsupported : AArch64Unsupported {
505  let F = [HasPA];
506}
507
508include "AArch64SchedA53.td"
509include "AArch64SchedA57.td"
510include "AArch64SchedCyclone.td"
511include "AArch64SchedFalkor.td"
512include "AArch64SchedKryo.td"
513include "AArch64SchedExynosM3.td"
514include "AArch64SchedExynosM4.td"
515include "AArch64SchedExynosM5.td"
516include "AArch64SchedThunderX.td"
517include "AArch64SchedThunderX2T99.td"
518include "AArch64SchedThunderX3T110.td"
519
520def ProcA35     : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
521                                   "Cortex-A35 ARM processors", [
522                                   FeatureCRC,
523                                   FeatureCrypto,
524                                   FeatureFPARMv8,
525                                   FeatureNEON,
526                                   FeaturePerfMon
527                                   ]>;
528
529def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
530                                   "Cortex-A53 ARM processors", [
531                                   FeatureBalanceFPOps,
532                                   FeatureCRC,
533                                   FeatureCrypto,
534                                   FeatureCustomCheapAsMoveHandling,
535                                   FeatureFPARMv8,
536                                   FeatureFuseAES,
537                                   FeatureNEON,
538                                   FeaturePerfMon,
539                                   FeaturePostRAScheduler,
540                                   FeatureUseAA
541                                   ]>;
542
543def ProcA55     : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
544                                   "Cortex-A55 ARM processors", [
545                                   HasV8_2aOps,
546                                   FeatureCrypto,
547                                   FeatureFPARMv8,
548                                   FeatureFuseAES,
549                                   FeatureNEON,
550                                   FeatureFullFP16,
551                                   FeatureDotProd,
552                                   FeatureRCPC,
553                                   FeaturePerfMon
554                                   ]>;
555
556def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
557                                   "Cortex-A57 ARM processors", [
558                                   FeatureBalanceFPOps,
559                                   FeatureCRC,
560                                   FeatureCrypto,
561                                   FeatureCustomCheapAsMoveHandling,
562                                   FeatureFPARMv8,
563                                   FeatureFuseAES,
564                                   FeatureFuseLiterals,
565                                   FeatureNEON,
566                                   FeaturePerfMon,
567                                   FeaturePostRAScheduler,
568                                   FeaturePredictableSelectIsExpensive
569                                   ]>;
570
571def ProcA65     : SubtargetFeature<"a65", "ARMProcFamily", "CortexA65",
572                                   "Cortex-A65 ARM processors", [
573                                   HasV8_2aOps,
574                                   FeatureCrypto,
575                                   FeatureDotProd,
576                                   FeatureFPARMv8,
577                                   FeatureFullFP16,
578                                   FeatureNEON,
579                                   FeatureRAS,
580                                   FeatureRCPC,
581                                   FeatureSSBS,
582                                   ]>;
583
584def ProcA72     : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
585                                   "Cortex-A72 ARM processors", [
586                                   FeatureCRC,
587                                   FeatureCrypto,
588                                   FeatureFPARMv8,
589                                   FeatureFuseAES,
590                                   FeatureNEON,
591                                   FeaturePerfMon
592                                   ]>;
593
594def ProcA73     : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
595                                   "Cortex-A73 ARM processors", [
596                                   FeatureCRC,
597                                   FeatureCrypto,
598                                   FeatureFPARMv8,
599                                   FeatureFuseAES,
600                                   FeatureNEON,
601                                   FeaturePerfMon
602                                   ]>;
603
604def ProcA75     : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
605                                   "Cortex-A75 ARM processors", [
606                                   HasV8_2aOps,
607                                   FeatureCrypto,
608                                   FeatureFPARMv8,
609                                   FeatureFuseAES,
610                                   FeatureNEON,
611                                   FeatureFullFP16,
612                                   FeatureDotProd,
613                                   FeatureRCPC,
614                                   FeaturePerfMon
615                                   ]>;
616
617def ProcA76     : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76",
618                                   "Cortex-A76 ARM processors", [
619                                    HasV8_2aOps,
620                                    FeatureFPARMv8,
621                                    FeatureNEON,
622                                    FeatureRCPC,
623                                    FeatureCrypto,
624                                    FeatureFullFP16,
625                                    FeatureDotProd,
626                                    FeatureSSBS
627                                    ]>;
628
629def ProcA77     : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77",
630                                   "Cortex-A77 ARM processors", [
631                                    HasV8_2aOps,
632                                    FeatureFPARMv8,
633                                    FeatureNEON, FeatureRCPC,
634                                    FeatureCrypto,
635                                    FeatureFullFP16,
636                                    FeatureDotProd
637                                    ]>;
638
639def ProcA78 : SubtargetFeature<"cortex-a78", "ARMProcFamily",
640                               "CortexA78",
641                               "Cortex-A78 ARM processors", [
642                               HasV8_2aOps,
643                               FeatureCrypto,
644                               FeatureFPARMv8,
645                               FeatureFuseAES,
646                               FeatureNEON,
647                               FeatureRCPC,
648                               FeaturePerfMon,
649                               FeaturePostRAScheduler,
650                               FeatureSPE,
651                               FeatureFullFP16,
652                               FeatureSSBS,
653                               FeatureDotProd]>;
654
655def ProcX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1",
656                                  "Cortex-X1 ARM processors", [
657                                  HasV8_2aOps,
658                                  FeatureCrypto,
659                                  FeatureFPARMv8,
660                                  FeatureFuseAES,
661                                  FeatureNEON,
662                                  FeatureRCPC,
663                                  FeaturePerfMon,
664                                  FeaturePostRAScheduler,
665                                  FeatureSPE,
666                                  FeatureFullFP16,
667                                  FeatureDotProd]>;
668
669def ProcA64FX : SubtargetFeature<"a64fx", "ARMProcFamily", "A64FX",
670                                 "Fujitsu A64FX processors", [
671                                  HasV8_2aOps,
672                                  FeatureFPARMv8,
673                                  FeatureNEON,
674                                  FeatureSHA2,
675                                  FeaturePerfMon,
676                                  FeatureFullFP16,
677                                  FeatureSVE,
678                                  FeaturePostRAScheduler,
679                                  FeatureComplxNum
680                                  ]>;
681
682def ProcCarmel : SubtargetFeature<"carmel", "ARMProcFamily", "Carmel",
683                                  "Nvidia Carmel processors", [
684                                   HasV8_2aOps,
685                                   FeatureNEON,
686                                   FeatureCrypto,
687                                   FeatureFullFP16
688                                   ]>;
689
690// Note that cyclone does not fuse AES instructions, but newer apple chips do
691// perform the fusion and cyclone is used by default when targetting apple OSes.
692def ProcAppleA7 : SubtargetFeature<"apple-a7", "ARMProcFamily", "AppleA7",
693                                   "Apple A7 (the CPU formerly known as Cyclone)", [
694                                   FeatureAlternateSExtLoadCVTF32Pattern,
695                                   FeatureArithmeticBccFusion,
696                                   FeatureArithmeticCbzFusion,
697                                   FeatureCrypto,
698                                   FeatureDisableLatencySchedHeuristic,
699                                   FeatureFPARMv8,
700                                   FeatureFuseAES,
701                                   FeatureFuseCryptoEOR,
702                                   FeatureNEON,
703                                   FeaturePerfMon,
704                                   FeatureZCRegMove,
705                                   FeatureZCZeroing,
706                                   FeatureZCZeroingFPWorkaround
707                                   ]>;
708
709def ProcAppleA10 : SubtargetFeature<"apple-a10", "ARMProcFamily", "AppleA10",
710                                    "Apple A10", [
711                                    FeatureAlternateSExtLoadCVTF32Pattern,
712                                    FeatureArithmeticBccFusion,
713                                    FeatureArithmeticCbzFusion,
714                                    FeatureCrypto,
715                                    FeatureDisableLatencySchedHeuristic,
716                                    FeatureFPARMv8,
717                                    FeatureFuseAES,
718                                    FeatureFuseCryptoEOR,
719                                    FeatureNEON,
720                                    FeaturePerfMon,
721                                    FeatureZCRegMove,
722                                    FeatureZCZeroing,
723                                    FeatureCRC,
724                                    FeatureRDM,
725                                    FeaturePAN,
726                                    FeatureLOR,
727                                    FeatureVH,
728                                    ]>;
729
730def ProcAppleA11 : SubtargetFeature<"apple-a11", "ARMProcFamily", "AppleA11",
731                                    "Apple A11", [
732                                    FeatureAlternateSExtLoadCVTF32Pattern,
733                                    FeatureArithmeticBccFusion,
734                                    FeatureArithmeticCbzFusion,
735                                    FeatureCrypto,
736                                    FeatureDisableLatencySchedHeuristic,
737                                    FeatureFPARMv8,
738                                    FeatureFuseAES,
739                                    FeatureFuseCryptoEOR,
740                                    FeatureNEON,
741                                    FeaturePerfMon,
742                                    FeatureZCRegMove,
743                                    FeatureZCZeroing,
744                                    FeatureFullFP16,
745                                    HasV8_2aOps
746                                    ]>;
747
748def ProcAppleA12 : SubtargetFeature<"apple-a12", "ARMProcFamily", "AppleA12",
749                                    "Apple A12", [
750                                    FeatureAlternateSExtLoadCVTF32Pattern,
751                                    FeatureArithmeticBccFusion,
752                                    FeatureArithmeticCbzFusion,
753                                    FeatureCrypto,
754                                    FeatureDisableLatencySchedHeuristic,
755                                    FeatureFPARMv8,
756                                    FeatureFuseAES,
757                                    FeatureFuseCryptoEOR,
758                                    FeatureNEON,
759                                    FeaturePerfMon,
760                                    FeatureZCRegMove,
761                                    FeatureZCZeroing,
762                                    FeatureFullFP16,
763                                    HasV8_3aOps
764                                    ]>;
765
766def ProcAppleA13 : SubtargetFeature<"apple-a13", "ARMProcFamily", "AppleA13",
767                                     "Apple A13", [
768                                     FeatureAlternateSExtLoadCVTF32Pattern,
769                                     FeatureArithmeticBccFusion,
770                                     FeatureArithmeticCbzFusion,
771                                     FeatureCrypto,
772                                     FeatureDisableLatencySchedHeuristic,
773                                     FeatureFPARMv8,
774                                     FeatureFuseAES,
775                                     FeatureFuseCryptoEOR,
776                                     FeatureNEON,
777                                     FeaturePerfMon,
778                                     FeatureZCRegMove,
779                                     FeatureZCZeroing,
780                                     FeatureFullFP16,
781                                     FeatureFP16FML,
782                                     FeatureSHA3,
783                                     HasV8_4aOps
784                                     ]>;
785
786def ProcExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3",
787                                    "Samsung Exynos-M3 processors",
788                                    [FeatureCRC,
789                                     FeatureCrypto,
790                                     FeatureExynosCheapAsMoveHandling,
791                                     FeatureForce32BitJumpTables,
792                                     FeatureFuseAddress,
793                                     FeatureFuseAES,
794                                     FeatureFuseCCSelect,
795                                     FeatureFuseLiterals,
796                                     FeatureLSLFast,
797                                     FeaturePerfMon,
798                                     FeaturePostRAScheduler,
799                                     FeaturePredictableSelectIsExpensive,
800                                     FeatureZCZeroingFP]>;
801
802def ProcExynosM4 : SubtargetFeature<"exynosm4", "ARMProcFamily", "ExynosM3",
803                                    "Samsung Exynos-M4 processors",
804                                    [HasV8_2aOps,
805                                     FeatureArithmeticBccFusion,
806                                     FeatureArithmeticCbzFusion,
807                                     FeatureCrypto,
808                                     FeatureDotProd,
809                                     FeatureExynosCheapAsMoveHandling,
810                                     FeatureForce32BitJumpTables,
811                                     FeatureFullFP16,
812                                     FeatureFuseAddress,
813                                     FeatureFuseAES,
814                                     FeatureFuseArithmeticLogic,
815                                     FeatureFuseCCSelect,
816                                     FeatureFuseLiterals,
817                                     FeatureLSLFast,
818                                     FeaturePerfMon,
819                                     FeaturePostRAScheduler,
820                                     FeatureZCZeroing]>;
821
822def ProcKryo    : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
823                                   "Qualcomm Kryo processors", [
824                                   FeatureCRC,
825                                   FeatureCrypto,
826                                   FeatureCustomCheapAsMoveHandling,
827                                   FeatureFPARMv8,
828                                   FeatureNEON,
829                                   FeaturePerfMon,
830                                   FeaturePostRAScheduler,
831                                   FeaturePredictableSelectIsExpensive,
832                                   FeatureZCZeroing,
833                                   FeatureLSLFast
834                                   ]>;
835
836def ProcFalkor  : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor",
837                                   "Qualcomm Falkor processors", [
838                                   FeatureCRC,
839                                   FeatureCrypto,
840                                   FeatureCustomCheapAsMoveHandling,
841                                   FeatureFPARMv8,
842                                   FeatureNEON,
843                                   FeaturePerfMon,
844                                   FeaturePostRAScheduler,
845                                   FeaturePredictableSelectIsExpensive,
846                                   FeatureRDM,
847                                   FeatureZCZeroing,
848                                   FeatureLSLFast,
849                                   FeatureSlowSTRQro
850                                   ]>;
851
852def ProcNeoverseE1 : SubtargetFeature<"neoversee1", "ARMProcFamily",
853                                      "NeoverseE1",
854                                      "Neoverse E1 ARM processors", [
855                                      HasV8_2aOps,
856                                      FeatureCrypto,
857                                      FeatureDotProd,
858                                      FeatureFPARMv8,
859                                      FeatureFullFP16,
860                                      FeatureNEON,
861                                      FeatureRCPC,
862                                      FeatureSSBS,
863                                      ]>;
864
865def ProcNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily",
866                                      "NeoverseN1",
867                                      "Neoverse N1 ARM processors", [
868                                      HasV8_2aOps,
869                                      FeatureCrypto,
870                                      FeatureDotProd,
871                                      FeatureFPARMv8,
872                                      FeatureFullFP16,
873                                      FeatureNEON,
874                                      FeatureRCPC,
875                                      FeatureSPE,
876                                      FeatureSSBS,
877                                      ]>;
878
879def ProcSaphira  : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira",
880                                   "Qualcomm Saphira processors", [
881                                   FeatureCrypto,
882                                   FeatureCustomCheapAsMoveHandling,
883                                   FeatureFPARMv8,
884                                   FeatureNEON,
885                                   FeatureSPE,
886                                   FeaturePerfMon,
887                                   FeaturePostRAScheduler,
888                                   FeaturePredictableSelectIsExpensive,
889                                   FeatureZCZeroing,
890                                   FeatureLSLFast,
891                                   HasV8_4aOps]>;
892
893def ProcThunderX2T99  : SubtargetFeature<"thunderx2t99", "ARMProcFamily",
894                                         "ThunderX2T99",
895                                         "Cavium ThunderX2 processors", [
896                                          FeatureAggressiveFMA,
897                                          FeatureCRC,
898                                          FeatureCrypto,
899                                          FeatureFPARMv8,
900                                          FeatureArithmeticBccFusion,
901                                          FeatureNEON,
902                                          FeaturePostRAScheduler,
903                                          FeaturePredictableSelectIsExpensive,
904                                          FeatureLSE,
905                                          HasV8_1aOps]>;
906
907def ProcThunderX3T110  : SubtargetFeature<"thunderx3t110", "ARMProcFamily",
908                                         "ThunderX3T110",
909                                         "Marvell ThunderX3 processors", [
910                                          FeatureAggressiveFMA,
911                                          FeatureCRC,
912                                          FeatureCrypto,
913                                          FeatureFPARMv8,
914                                          FeatureArithmeticBccFusion,
915                                          FeatureNEON,
916                                          FeaturePostRAScheduler,
917                                          FeaturePredictableSelectIsExpensive,
918                                          FeatureLSE,
919                                          FeaturePA,
920                                          FeatureUseAA,
921                                          FeatureBalanceFPOps,
922                                          FeaturePerfMon,
923                                          FeatureStrictAlign,
924                                          HasV8_3aOps]>;
925
926def ProcThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX",
927                                    "Cavium ThunderX processors", [
928                                    FeatureCRC,
929                                    FeatureCrypto,
930                                    FeatureFPARMv8,
931                                    FeaturePerfMon,
932                                    FeaturePostRAScheduler,
933                                    FeaturePredictableSelectIsExpensive,
934                                    FeatureNEON]>;
935
936def ProcThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily",
937                                       "ThunderXT88",
938                                       "Cavium ThunderX processors", [
939                                       FeatureCRC,
940                                       FeatureCrypto,
941                                       FeatureFPARMv8,
942                                       FeaturePerfMon,
943                                       FeaturePostRAScheduler,
944                                       FeaturePredictableSelectIsExpensive,
945                                       FeatureNEON]>;
946
947def ProcThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily",
948                                       "ThunderXT81",
949                                       "Cavium ThunderX processors", [
950                                       FeatureCRC,
951                                       FeatureCrypto,
952                                       FeatureFPARMv8,
953                                       FeaturePerfMon,
954                                       FeaturePostRAScheduler,
955                                       FeaturePredictableSelectIsExpensive,
956                                       FeatureNEON]>;
957
958def ProcThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily",
959                                       "ThunderXT83",
960                                       "Cavium ThunderX processors", [
961                                       FeatureCRC,
962                                       FeatureCrypto,
963                                       FeatureFPARMv8,
964                                       FeaturePerfMon,
965                                       FeaturePostRAScheduler,
966                                       FeaturePredictableSelectIsExpensive,
967                                       FeatureNEON]>;
968
969def ProcTSV110 : SubtargetFeature<"tsv110", "ARMProcFamily", "TSV110",
970                                  "HiSilicon TS-V110 processors", [
971                                  HasV8_2aOps,
972                                  FeatureCrypto,
973                                  FeatureCustomCheapAsMoveHandling,
974                                  FeatureFPARMv8,
975                                  FeatureFuseAES,
976                                  FeatureNEON,
977                                  FeaturePerfMon,
978                                  FeaturePostRAScheduler,
979                                  FeatureSPE,
980                                  FeatureFullFP16,
981                                  FeatureFP16FML,
982                                  FeatureDotProd]>;
983
984def : ProcessorModel<"generic", NoSchedModel, [
985                     FeatureFPARMv8,
986                     FeatureFuseAES,
987                     FeatureNEON,
988                     FeaturePerfMon,
989                     FeaturePostRAScheduler,
990// ETE and TRBE are future architecture extensions. We temporarily enable them
991// by default for users targeting generic AArch64, until it is decided in which
992// armv8.x-a architecture revision they will end up. The extensions do not
993// affect code generated by the compiler and can be used only by explicitly
994// mentioning the new system register names in assembly.
995                     FeatureETE
996                     ]>;
997
998def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
999def : ProcessorModel<"cortex-a34", CortexA53Model, [ProcA35]>;
1000def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
1001def : ProcessorModel<"cortex-a55", CortexA53Model, [ProcA55]>;
1002def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
1003def : ProcessorModel<"cortex-a65", CortexA53Model, [ProcA65]>;
1004def : ProcessorModel<"cortex-a65ae", CortexA53Model, [ProcA65]>;
1005def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>;
1006def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>;
1007def : ProcessorModel<"cortex-a75", CortexA57Model, [ProcA75]>;
1008def : ProcessorModel<"cortex-a76", CortexA57Model, [ProcA76]>;
1009def : ProcessorModel<"cortex-a76ae", CortexA57Model, [ProcA76]>;
1010def : ProcessorModel<"cortex-a77", CortexA57Model, [ProcA77]>;
1011def : ProcessorModel<"cortex-a78", CortexA57Model, [ProcA78]>;
1012def : ProcessorModel<"cortex-x1", CortexA57Model, [ProcX1]>;
1013def : ProcessorModel<"neoverse-e1", CortexA53Model, [ProcNeoverseE1]>;
1014def : ProcessorModel<"neoverse-n1", CortexA57Model, [ProcNeoverseN1]>;
1015def : ProcessorModel<"exynos-m3", ExynosM3Model, [ProcExynosM3]>;
1016def : ProcessorModel<"exynos-m4", ExynosM4Model, [ProcExynosM4]>;
1017def : ProcessorModel<"exynos-m5", ExynosM5Model, [ProcExynosM4]>;
1018def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>;
1019def : ProcessorModel<"saphira", FalkorModel, [ProcSaphira]>;
1020def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;
1021// Cavium ThunderX/ThunderX T8X  Processors
1022def : ProcessorModel<"thunderx", ThunderXT8XModel,  [ProcThunderX]>;
1023def : ProcessorModel<"thunderxt88", ThunderXT8XModel,  [ProcThunderXT88]>;
1024def : ProcessorModel<"thunderxt81", ThunderXT8XModel,  [ProcThunderXT81]>;
1025def : ProcessorModel<"thunderxt83", ThunderXT8XModel,  [ProcThunderXT83]>;
1026// Cavium ThunderX2T9X  Processors. Formerly Broadcom Vulcan.
1027def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, [ProcThunderX2T99]>;
1028// Marvell ThunderX3T110 Processors.
1029def : ProcessorModel<"thunderx3t110", ThunderX3T110Model, [ProcThunderX3T110]>;
1030// FIXME: HiSilicon TSV110 is currently modeled as a Cortex-A57.
1031def : ProcessorModel<"tsv110", CortexA57Model, [ProcTSV110]>;
1032
1033// Support cyclone as an alias for apple-a7 so we can still LTO old bitcode.
1034def : ProcessorModel<"cyclone", CycloneModel, [ProcAppleA7]>;
1035
1036// iPhone and iPad CPUs
1037def : ProcessorModel<"apple-a7", CycloneModel, [ProcAppleA7]>;
1038def : ProcessorModel<"apple-a8", CycloneModel, [ProcAppleA7]>;
1039def : ProcessorModel<"apple-a9", CycloneModel, [ProcAppleA7]>;
1040def : ProcessorModel<"apple-a10", CycloneModel, [ProcAppleA10]>;
1041def : ProcessorModel<"apple-a11", CycloneModel, [ProcAppleA11]>;
1042def : ProcessorModel<"apple-a12", CycloneModel, [ProcAppleA12]>;
1043def : ProcessorModel<"apple-a13", CycloneModel, [ProcAppleA13]>;
1044
1045// watch CPUs.
1046def : ProcessorModel<"apple-s4", CycloneModel, [ProcAppleA12]>;
1047def : ProcessorModel<"apple-s5", CycloneModel, [ProcAppleA12]>;
1048
1049// Alias for the latest Apple processor model supported by LLVM.
1050def : ProcessorModel<"apple-latest", CycloneModel, [ProcAppleA13]>;
1051
1052// Fujitsu A64FX
1053// FIXME: Scheduling model is not implemented yet.
1054def : ProcessorModel<"a64fx", NoSchedModel, [ProcA64FX]>;
1055
1056// Nvidia Carmel
1057def : ProcessorModel<"carmel", NoSchedModel, [ProcCarmel]>;
1058
1059//===----------------------------------------------------------------------===//
1060// Assembly parser
1061//===----------------------------------------------------------------------===//
1062
1063def GenericAsmParserVariant : AsmParserVariant {
1064  int Variant = 0;
1065  string Name = "generic";
1066  string BreakCharacters = ".";
1067  string TokenizingCharacters = "[]*!/";
1068}
1069
1070def AppleAsmParserVariant : AsmParserVariant {
1071  int Variant = 1;
1072  string Name = "apple-neon";
1073  string BreakCharacters = ".";
1074  string TokenizingCharacters = "[]*!/";
1075}
1076
1077//===----------------------------------------------------------------------===//
1078// Assembly printer
1079//===----------------------------------------------------------------------===//
1080// AArch64 Uses the MC printer for asm output, so make sure the TableGen
1081// AsmWriter bits get associated with the correct class.
1082def GenericAsmWriter : AsmWriter {
1083  string AsmWriterClassName  = "InstPrinter";
1084  int PassSubtarget = 1;
1085  int Variant = 0;
1086  bit isMCAsmWriter = 1;
1087}
1088
1089def AppleAsmWriter : AsmWriter {
1090  let AsmWriterClassName = "AppleInstPrinter";
1091  int PassSubtarget = 1;
1092  int Variant = 1;
1093  int isMCAsmWriter = 1;
1094}
1095
1096//===----------------------------------------------------------------------===//
1097// Target Declaration
1098//===----------------------------------------------------------------------===//
1099
1100def AArch64 : Target {
1101  let InstructionSet = AArch64InstrInfo;
1102  let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
1103  let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
1104  let AllowRegisterRenaming = 1;
1105}
1106
1107//===----------------------------------------------------------------------===//
1108// Pfm Counters
1109//===----------------------------------------------------------------------===//
1110
1111include "AArch64PfmCounters.td"
1112