1 //=== AArch64CallingConvention.cpp - AArch64 CC impl ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the table-generated and custom routines for the AArch64
10 // Calling Convention.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AArch64CallingConvention.h"
15 #include "AArch64.h"
16 #include "AArch64InstrInfo.h"
17 #include "AArch64Subtarget.h"
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/TargetInstrInfo.h"
20 #include "llvm/IR/CallingConv.h"
21 using namespace llvm;
22 
23 static const MCPhysReg XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
24                                      AArch64::X3, AArch64::X4, AArch64::X5,
25                                      AArch64::X6, AArch64::X7};
26 static const MCPhysReg HRegList[] = {AArch64::H0, AArch64::H1, AArch64::H2,
27                                      AArch64::H3, AArch64::H4, AArch64::H5,
28                                      AArch64::H6, AArch64::H7};
29 static const MCPhysReg SRegList[] = {AArch64::S0, AArch64::S1, AArch64::S2,
30                                      AArch64::S3, AArch64::S4, AArch64::S5,
31                                      AArch64::S6, AArch64::S7};
32 static const MCPhysReg DRegList[] = {AArch64::D0, AArch64::D1, AArch64::D2,
33                                      AArch64::D3, AArch64::D4, AArch64::D5,
34                                      AArch64::D6, AArch64::D7};
35 static const MCPhysReg QRegList[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2,
36                                      AArch64::Q3, AArch64::Q4, AArch64::Q5,
37                                      AArch64::Q6, AArch64::Q7};
38 static const MCPhysReg ZRegList[] = {AArch64::Z0, AArch64::Z1, AArch64::Z2,
39                                      AArch64::Z3, AArch64::Z4, AArch64::Z5,
40                                      AArch64::Z6, AArch64::Z7};
41 
finishStackBlock(SmallVectorImpl<CCValAssign> & PendingMembers,MVT LocVT,ISD::ArgFlagsTy & ArgFlags,CCState & State,Align SlotAlign)42 static bool finishStackBlock(SmallVectorImpl<CCValAssign> &PendingMembers,
43                              MVT LocVT, ISD::ArgFlagsTy &ArgFlags,
44                              CCState &State, Align SlotAlign) {
45   unsigned Size = LocVT.getSizeInBits() / 8;
46   const Align StackAlign =
47       State.getMachineFunction().getDataLayout().getStackAlignment();
48   const Align OrigAlign = ArgFlags.getNonZeroOrigAlign();
49   const Align Alignment = std::min(OrigAlign, StackAlign);
50 
51   for (auto &It : PendingMembers) {
52     It.convertToMem(State.AllocateStack(Size, std::max(Alignment, SlotAlign)));
53     State.addLoc(It);
54     SlotAlign = Align(1);
55   }
56 
57   // All pending members have now been allocated
58   PendingMembers.clear();
59   return true;
60 }
61 
62 /// The Darwin variadic PCS places anonymous arguments in 8-byte stack slots. An
63 /// [N x Ty] type must still be contiguous in memory though.
CC_AArch64_Custom_Stack_Block(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)64 static bool CC_AArch64_Custom_Stack_Block(
65       unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo,
66       ISD::ArgFlagsTy &ArgFlags, CCState &State) {
67   SmallVectorImpl<CCValAssign> &PendingMembers = State.getPendingLocs();
68 
69   // Add the argument to the list to be allocated once we know the size of the
70   // block.
71   PendingMembers.push_back(
72       CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo));
73 
74   if (!ArgFlags.isInConsecutiveRegsLast())
75     return true;
76 
77   return finishStackBlock(PendingMembers, LocVT, ArgFlags, State, Align(8));
78 }
79 
80 /// Given an [N x Ty] block, it should be passed in a consecutive sequence of
81 /// registers. If no such sequence is available, mark the rest of the registers
82 /// of that type as used and place the argument on the stack.
CC_AArch64_Custom_Block(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)83 static bool CC_AArch64_Custom_Block(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
84                                     CCValAssign::LocInfo &LocInfo,
85                                     ISD::ArgFlagsTy &ArgFlags, CCState &State) {
86   const AArch64Subtarget &Subtarget = static_cast<const AArch64Subtarget &>(
87       State.getMachineFunction().getSubtarget());
88   bool IsDarwinILP32 = Subtarget.isTargetILP32() && Subtarget.isTargetMachO();
89 
90   // Try to allocate a contiguous block of registers, each of the correct
91   // size to hold one member.
92   ArrayRef<MCPhysReg> RegList;
93   if (LocVT.SimpleTy == MVT::i64 || (IsDarwinILP32 && LocVT.SimpleTy == MVT::i32))
94     RegList = XRegList;
95   else if (LocVT.SimpleTy == MVT::f16)
96     RegList = HRegList;
97   else if (LocVT.SimpleTy == MVT::f32 || LocVT.is32BitVector())
98     RegList = SRegList;
99   else if (LocVT.SimpleTy == MVT::f64 || LocVT.is64BitVector())
100     RegList = DRegList;
101   else if (LocVT.SimpleTy == MVT::f128 || LocVT.is128BitVector())
102     RegList = QRegList;
103   else if (LocVT.isScalableVector())
104     RegList = ZRegList;
105   else {
106     // Not an array we want to split up after all.
107     return false;
108   }
109 
110   SmallVectorImpl<CCValAssign> &PendingMembers = State.getPendingLocs();
111 
112   // Add the argument to the list to be allocated once we know the size of the
113   // block.
114   PendingMembers.push_back(
115       CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo));
116 
117   if (!ArgFlags.isInConsecutiveRegsLast())
118     return true;
119 
120   // [N x i32] arguments get packed into x-registers on Darwin's arm64_32
121   // because that's how the armv7k Clang front-end emits small structs.
122   unsigned EltsPerReg = (IsDarwinILP32 && LocVT.SimpleTy == MVT::i32) ? 2 : 1;
123   unsigned RegResult = State.AllocateRegBlock(
124       RegList, alignTo(PendingMembers.size(), EltsPerReg) / EltsPerReg);
125   if (RegResult && EltsPerReg == 1) {
126     for (auto &It : PendingMembers) {
127       It.convertToReg(RegResult);
128       State.addLoc(It);
129       ++RegResult;
130     }
131     PendingMembers.clear();
132     return true;
133   } else if (RegResult) {
134     assert(EltsPerReg == 2 && "unexpected ABI");
135     bool UseHigh = false;
136     CCValAssign::LocInfo Info;
137     for (auto &It : PendingMembers) {
138       Info = UseHigh ? CCValAssign::AExtUpper : CCValAssign::ZExt;
139       State.addLoc(CCValAssign::getReg(It.getValNo(), MVT::i32, RegResult,
140                                        MVT::i64, Info));
141       UseHigh = !UseHigh;
142       if (!UseHigh)
143         ++RegResult;
144     }
145     PendingMembers.clear();
146     return true;
147   }
148 
149   if (LocVT.isScalableVector())
150     report_fatal_error(
151         "Passing consecutive scalable vector registers unsupported");
152 
153   // Mark all regs in the class as unavailable
154   for (auto Reg : RegList)
155     State.AllocateReg(Reg);
156 
157   const Align SlotAlign = Subtarget.isTargetDarwin() ? Align(1) : Align(8);
158 
159   return finishStackBlock(PendingMembers, LocVT, ArgFlags, State, SlotAlign);
160 }
161 
162 // TableGen provides definitions of the calling convention analysis entry
163 // points.
164 #include "AArch64GenCallingConv.inc"
165