1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the ARM specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "ARM.h"
14
15 #include "ARMCallLowering.h"
16 #include "ARMLegalizerInfo.h"
17 #include "ARMRegisterBankInfo.h"
18 #include "ARMSubtarget.h"
19 #include "ARMFrameLowering.h"
20 #include "ARMInstrInfo.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "MCTargetDesc/ARMMCTargetDesc.h"
24 #include "Thumb1FrameLowering.h"
25 #include "Thumb1InstrInfo.h"
26 #include "Thumb2InstrInfo.h"
27 #include "llvm/ADT/StringRef.h"
28 #include "llvm/ADT/Triple.h"
29 #include "llvm/ADT/Twine.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/GlobalValue.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCTargetOptions.h"
36 #include "llvm/Support/CodeGen.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/TargetParser.h"
39 #include "llvm/Target/TargetOptions.h"
40
41 using namespace llvm;
42
43 #define DEBUG_TYPE "arm-subtarget"
44
45 #define GET_SUBTARGETINFO_TARGET_DESC
46 #define GET_SUBTARGETINFO_CTOR
47 #include "ARMGenSubtargetInfo.inc"
48
49 static cl::opt<bool>
50 UseFusedMulOps("arm-use-mulops",
51 cl::init(true), cl::Hidden);
52
53 enum ITMode {
54 DefaultIT,
55 RestrictedIT,
56 NoRestrictedIT
57 };
58
59 static cl::opt<ITMode>
60 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
61 cl::ZeroOrMore,
62 cl::values(clEnumValN(DefaultIT, "arm-default-it",
63 "Generate IT block based on arch"),
64 clEnumValN(RestrictedIT, "arm-restrict-it",
65 "Disallow deprecated IT based on ARMv8"),
66 clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
67 "Allow IT blocks based on ARMv7")));
68
69 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not
70 /// currently supported (for testing only).
71 static cl::opt<bool>
72 ForceFastISel("arm-force-fast-isel",
73 cl::init(false), cl::Hidden);
74
75 static cl::opt<bool> EnableSubRegLiveness("arm-enable-subreg-liveness",
76 cl::init(false), cl::Hidden);
77
78 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
79 /// so that we can use initializer lists for subtarget initialization.
initializeSubtargetDependencies(StringRef CPU,StringRef FS)80 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
81 StringRef FS) {
82 initializeEnvironment();
83 initSubtargetFeatures(CPU, FS);
84 return *this;
85 }
86
initializeFrameLowering(StringRef CPU,StringRef FS)87 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
88 StringRef FS) {
89 ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
90 if (STI.isThumb1Only())
91 return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
92
93 return new ARMFrameLowering(STI);
94 }
95
ARMSubtarget(const Triple & TT,const std::string & CPU,const std::string & FS,const ARMBaseTargetMachine & TM,bool IsLittle,bool MinSize)96 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
97 const std::string &FS,
98 const ARMBaseTargetMachine &TM, bool IsLittle,
99 bool MinSize)
100 : ARMGenSubtargetInfo(TT, CPU, FS), UseMulOps(UseFusedMulOps),
101 CPUString(CPU), OptMinSize(MinSize), IsLittle(IsLittle),
102 TargetTriple(TT), Options(TM.Options), TM(TM),
103 FrameLowering(initializeFrameLowering(CPU, FS)),
104 // At this point initializeSubtargetDependencies has been called so
105 // we can query directly.
106 InstrInfo(isThumb1Only()
107 ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
108 : !isThumb()
109 ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
110 : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
111 TLInfo(TM, *this) {
112
113 CallLoweringInfo.reset(new ARMCallLowering(*getTargetLowering()));
114 Legalizer.reset(new ARMLegalizerInfo(*this));
115
116 auto *RBI = new ARMRegisterBankInfo(*getRegisterInfo());
117
118 // FIXME: At this point, we can't rely on Subtarget having RBI.
119 // It's awkward to mix passing RBI and the Subtarget; should we pass
120 // TII/TRI as well?
121 InstSelector.reset(createARMInstructionSelector(
122 *static_cast<const ARMBaseTargetMachine *>(&TM), *this, *RBI));
123
124 RegBankInfo.reset(RBI);
125 }
126
getCallLowering() const127 const CallLowering *ARMSubtarget::getCallLowering() const {
128 return CallLoweringInfo.get();
129 }
130
getInstructionSelector() const131 InstructionSelector *ARMSubtarget::getInstructionSelector() const {
132 return InstSelector.get();
133 }
134
getLegalizerInfo() const135 const LegalizerInfo *ARMSubtarget::getLegalizerInfo() const {
136 return Legalizer.get();
137 }
138
getRegBankInfo() const139 const RegisterBankInfo *ARMSubtarget::getRegBankInfo() const {
140 return RegBankInfo.get();
141 }
142
isXRaySupported() const143 bool ARMSubtarget::isXRaySupported() const {
144 // We don't currently suppport Thumb, but Windows requires Thumb.
145 return hasV6Ops() && hasARMOps() && !isTargetWindows();
146 }
147
initializeEnvironment()148 void ARMSubtarget::initializeEnvironment() {
149 // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
150 // directly from it, but we can try to make sure they're consistent when both
151 // available.
152 UseSjLjEH = (isTargetDarwin() && !isTargetWatchABI() &&
153 Options.ExceptionModel == ExceptionHandling::None) ||
154 Options.ExceptionModel == ExceptionHandling::SjLj;
155 assert((!TM.getMCAsmInfo() ||
156 (TM.getMCAsmInfo()->getExceptionHandlingType() ==
157 ExceptionHandling::SjLj) == UseSjLjEH) &&
158 "inconsistent sjlj choice between CodeGen and MC");
159 }
160
initSubtargetFeatures(StringRef CPU,StringRef FS)161 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
162 if (CPUString.empty()) {
163 CPUString = "generic";
164
165 if (isTargetDarwin()) {
166 StringRef ArchName = TargetTriple.getArchName();
167 ARM::ArchKind AK = ARM::parseArch(ArchName);
168 if (AK == ARM::ArchKind::ARMV7S)
169 // Default to the Swift CPU when targeting armv7s/thumbv7s.
170 CPUString = "swift";
171 else if (AK == ARM::ArchKind::ARMV7K)
172 // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
173 // ARMv7k does not use SjLj exception handling.
174 CPUString = "cortex-a7";
175 }
176 }
177
178 // Insert the architecture feature derived from the target triple into the
179 // feature string. This is important for setting features that are implied
180 // based on the architecture version.
181 std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
182 if (!FS.empty()) {
183 if (!ArchFS.empty())
184 ArchFS = (Twine(ArchFS) + "," + FS).str();
185 else
186 ArchFS = std::string(FS);
187 }
188 ParseSubtargetFeatures(CPUString, ArchFS);
189
190 // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
191 // Assert this for now to make the change obvious.
192 assert(hasV6T2Ops() || !hasThumb2());
193
194 // Execute only support requires movt support
195 if (genExecuteOnly()) {
196 NoMovt = false;
197 assert(hasV8MBaselineOps() && "Cannot generate execute-only code for this target");
198 }
199
200 // Keep a pointer to static instruction cost data for the specified CPU.
201 SchedModel = getSchedModelForCPU(CPUString);
202
203 // Initialize scheduling itinerary for the specified CPU.
204 InstrItins = getInstrItineraryForCPU(CPUString);
205
206 // FIXME: this is invalid for WindowsCE
207 if (isTargetWindows())
208 NoARM = true;
209
210 if (isAAPCS_ABI())
211 stackAlignment = Align(8);
212 if (isTargetNaCl() || isAAPCS16_ABI())
213 stackAlignment = Align(16);
214
215 // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
216 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
217 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
218 // support in the assembler and linker to be used. This would need to be
219 // fixed to fully support tail calls in Thumb1.
220 //
221 // For ARMv8-M, we /do/ implement tail calls. Doing this is tricky for v8-M
222 // baseline, since the LDM/POP instruction on Thumb doesn't take LR. This
223 // means if we need to reload LR, it takes extra instructions, which outweighs
224 // the value of the tail call; but here we don't know yet whether LR is going
225 // to be used. We take the optimistic approach of generating the tail call and
226 // perhaps taking a hit if we need to restore the LR.
227
228 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
229 // but we need to make sure there are enough registers; the only valid
230 // registers are the 4 used for parameters. We don't currently do this
231 // case.
232
233 SupportsTailCall = !isThumb() || hasV8MBaselineOps();
234
235 if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
236 SupportsTailCall = false;
237
238 switch (IT) {
239 case DefaultIT:
240 RestrictIT = hasV8Ops();
241 break;
242 case RestrictedIT:
243 RestrictIT = true;
244 break;
245 case NoRestrictedIT:
246 RestrictIT = false;
247 break;
248 }
249
250 // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
251 const FeatureBitset &Bits = getFeatureBits();
252 if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
253 (Options.UnsafeFPMath || isTargetDarwin()))
254 UseNEONForSinglePrecisionFP = true;
255
256 if (isRWPI())
257 ReserveR9 = true;
258
259 // If MVEVectorCostFactor is still 0 (has not been set to anything else), default it to 2
260 if (MVEVectorCostFactor == 0)
261 MVEVectorCostFactor = 2;
262
263 // FIXME: Teach TableGen to deal with these instead of doing it manually here.
264 switch (ARMProcFamily) {
265 case Others:
266 case CortexA5:
267 break;
268 case CortexA7:
269 LdStMultipleTiming = DoubleIssue;
270 break;
271 case CortexA8:
272 LdStMultipleTiming = DoubleIssue;
273 break;
274 case CortexA9:
275 LdStMultipleTiming = DoubleIssueCheckUnalignedAccess;
276 PreISelOperandLatencyAdjustment = 1;
277 break;
278 case CortexA12:
279 break;
280 case CortexA15:
281 MaxInterleaveFactor = 2;
282 PreISelOperandLatencyAdjustment = 1;
283 PartialUpdateClearance = 12;
284 break;
285 case CortexA17:
286 case CortexA32:
287 case CortexA35:
288 case CortexA53:
289 case CortexA55:
290 case CortexA57:
291 case CortexA72:
292 case CortexA73:
293 case CortexA75:
294 case CortexA76:
295 case CortexA77:
296 case CortexA78:
297 case CortexR4:
298 case CortexR4F:
299 case CortexR5:
300 case CortexR7:
301 case CortexM3:
302 case CortexR52:
303 case CortexX1:
304 break;
305 case Exynos:
306 LdStMultipleTiming = SingleIssuePlusExtras;
307 MaxInterleaveFactor = 4;
308 if (!isThumb())
309 PrefLoopLogAlignment = 3;
310 break;
311 case Kryo:
312 break;
313 case Krait:
314 PreISelOperandLatencyAdjustment = 1;
315 break;
316 case NeoverseN1:
317 break;
318 case Swift:
319 MaxInterleaveFactor = 2;
320 LdStMultipleTiming = SingleIssuePlusExtras;
321 PreISelOperandLatencyAdjustment = 1;
322 PartialUpdateClearance = 12;
323 break;
324 }
325 }
326
isTargetHardFloat() const327 bool ARMSubtarget::isTargetHardFloat() const { return TM.isTargetHardFloat(); }
328
isAPCS_ABI() const329 bool ARMSubtarget::isAPCS_ABI() const {
330 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
331 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
332 }
isAAPCS_ABI() const333 bool ARMSubtarget::isAAPCS_ABI() const {
334 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
335 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS ||
336 TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
337 }
isAAPCS16_ABI() const338 bool ARMSubtarget::isAAPCS16_ABI() const {
339 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
340 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
341 }
342
isROPI() const343 bool ARMSubtarget::isROPI() const {
344 return TM.getRelocationModel() == Reloc::ROPI ||
345 TM.getRelocationModel() == Reloc::ROPI_RWPI;
346 }
isRWPI() const347 bool ARMSubtarget::isRWPI() const {
348 return TM.getRelocationModel() == Reloc::RWPI ||
349 TM.getRelocationModel() == Reloc::ROPI_RWPI;
350 }
351
isGVIndirectSymbol(const GlobalValue * GV) const352 bool ARMSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const {
353 if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
354 return true;
355
356 // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
357 // the section that is being relocated. This means we have to use o load even
358 // for GVs that are known to be local to the dso.
359 if (isTargetMachO() && TM.isPositionIndependent() &&
360 (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
361 return true;
362
363 return false;
364 }
365
isGVInGOT(const GlobalValue * GV) const366 bool ARMSubtarget::isGVInGOT(const GlobalValue *GV) const {
367 return isTargetELF() && TM.isPositionIndependent() &&
368 !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
369 }
370
getMispredictionPenalty() const371 unsigned ARMSubtarget::getMispredictionPenalty() const {
372 return SchedModel.MispredictPenalty;
373 }
374
enableMachineScheduler() const375 bool ARMSubtarget::enableMachineScheduler() const {
376 // The MachineScheduler can increase register usage, so we use more high
377 // registers and end up with more T2 instructions that cannot be converted to
378 // T1 instructions. At least until we do better at converting to thumb1
379 // instructions, on cortex-m at Oz where we are size-paranoid, don't use the
380 // Machine scheduler, relying on the DAG register pressure scheduler instead.
381 if (isMClass() && hasMinSize())
382 return false;
383 // Enable the MachineScheduler before register allocation for subtargets
384 // with the use-misched feature.
385 return useMachineScheduler();
386 }
387
enableSubRegLiveness() const388 bool ARMSubtarget::enableSubRegLiveness() const { return EnableSubRegLiveness; }
389
390 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
enablePostRAScheduler() const391 bool ARMSubtarget::enablePostRAScheduler() const {
392 if (enableMachineScheduler())
393 return false;
394 if (disablePostRAScheduler())
395 return false;
396 // Thumb1 cores will generally not benefit from post-ra scheduling
397 return !isThumb1Only();
398 }
399
enablePostRAMachineScheduler() const400 bool ARMSubtarget::enablePostRAMachineScheduler() const {
401 if (!enableMachineScheduler())
402 return false;
403 if (disablePostRAScheduler())
404 return false;
405 return !isThumb1Only();
406 }
407
enableAtomicExpand() const408 bool ARMSubtarget::enableAtomicExpand() const { return hasAnyDataBarrier(); }
409
useStride4VFPs() const410 bool ARMSubtarget::useStride4VFPs() const {
411 // For general targets, the prologue can grow when VFPs are allocated with
412 // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
413 // format which it's more important to get right.
414 return isTargetWatchABI() ||
415 (useWideStrideVFP() && !OptMinSize);
416 }
417
useMovt() const418 bool ARMSubtarget::useMovt() const {
419 // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
420 // immediates as it is inherently position independent, and may be out of
421 // range otherwise.
422 return !NoMovt && hasV8MBaselineOps() &&
423 (isTargetWindows() || !OptMinSize || genExecuteOnly());
424 }
425
useFastISel() const426 bool ARMSubtarget::useFastISel() const {
427 // Enable fast-isel for any target, for testing only.
428 if (ForceFastISel)
429 return true;
430
431 // Limit fast-isel to the targets that are or have been tested.
432 if (!hasV6Ops())
433 return false;
434
435 // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
436 return TM.Options.EnableFastISel &&
437 ((isTargetMachO() && !isThumb1Only()) ||
438 (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
439 }
440
getGPRAllocationOrder(const MachineFunction & MF) const441 unsigned ARMSubtarget::getGPRAllocationOrder(const MachineFunction &MF) const {
442 // The GPR register class has multiple possible allocation orders, with
443 // tradeoffs preferred by different sub-architectures and optimisation goals.
444 // The allocation orders are:
445 // 0: (the default tablegen order, not used)
446 // 1: r14, r0-r13
447 // 2: r0-r7
448 // 3: r0-r7, r12, lr, r8-r11
449 // Note that the register allocator will change this order so that
450 // callee-saved registers are used later, as they require extra work in the
451 // prologue/epilogue (though we sometimes override that).
452
453 // For thumb1-only targets, only the low registers are allocatable.
454 if (isThumb1Only())
455 return 2;
456
457 // Allocate low registers first, so we can select more 16-bit instructions.
458 // We also (in ignoreCSRForAllocationOrder) override the default behaviour
459 // with regards to callee-saved registers, because pushing extra registers is
460 // much cheaper (in terms of code size) than using high registers. After
461 // that, we allocate r12 (doesn't need to be saved), lr (saving it means we
462 // can return with the pop, don't need an extra "bx lr") and then the rest of
463 // the high registers.
464 if (isThumb2() && MF.getFunction().hasMinSize())
465 return 3;
466
467 // Otherwise, allocate in the default order, using LR first because saving it
468 // allows a shorter epilogue sequence.
469 return 1;
470 }
471
ignoreCSRForAllocationOrder(const MachineFunction & MF,unsigned PhysReg) const472 bool ARMSubtarget::ignoreCSRForAllocationOrder(const MachineFunction &MF,
473 unsigned PhysReg) const {
474 // To minimize code size in Thumb2, we prefer the usage of low regs (lower
475 // cost per use) so we can use narrow encoding. By default, caller-saved
476 // registers (e.g. lr, r12) are always allocated first, regardless of
477 // their cost per use. When optForMinSize, we prefer the low regs even if
478 // they are CSR because usually push/pop can be folded into existing ones.
479 return isThumb2() && MF.getFunction().hasMinSize() &&
480 ARM::GPRRegClass.contains(PhysReg);
481 }
482