1; RUN: llc -mtriple=aarch64_be--linux-gnu < %s | FileCheck %s
2
3@vec_v8i16 = global <8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>
4
5; CHECK-LABEL: movi_modimm_t1:
6define void @movi_modimm_t1() nounwind {
7  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
8  ; CHECK-NEXT:    movi	   v[[REG2:[0-9]+]].4s, #1
9  ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
10  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
11  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
12  %rv = add <8 x i16> %in, <i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0>
13  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
14  ret void
15}
16
17; CHECK-LABEL: movi_modimm_t2:
18define void @movi_modimm_t2() nounwind {
19  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
20  ; CHECK-NEXT:    movi	   v[[REG2:[0-9]+]].4s, #1, lsl #8
21  ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
22  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
23  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
24  %rv = add <8 x i16> %in, <i16 256, i16 0, i16 256, i16 0, i16 256, i16 0, i16 256, i16 0>
25  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
26  ret void
27}
28
29; CHECK-LABEL: movi_modimm_t3:
30define void @movi_modimm_t3() nounwind {
31  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
32  ; CHECK-NEXT:    movi	   v[[REG2:[0-9]+]].4s, #1, lsl #16
33  ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
34  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
35  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
36  %rv = add <8 x i16> %in, <i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1>
37  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
38  ret void
39}
40
41; CHECK-LABEL: movi_modimm_t4:
42define void @movi_modimm_t4() nounwind {
43  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
44  ; CHECK-NEXT:    movi	   v[[REG2:[0-9]+]].4s, #1, lsl #24
45  ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
46  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
47  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
48  %rv = add <8 x i16> %in, <i16 0, i16 256, i16 0, i16 256, i16 0, i16 256, i16 0, i16 256>
49  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
50  ret void
51}
52
53; CHECK-LABEL: movi_modimm_t5:
54define void @movi_modimm_t5() nounwind {
55  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
56  ; CHECK-NEXT:    movi	   v[[REG2:[0-9]+]].8h, #1
57  ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
58  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
59  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
60  %rv = add <8 x i16> %in, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
61  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
62  ret void
63}
64
65; CHECK-LABEL: movi_modimm_t6:
66define void @movi_modimm_t6() nounwind {
67  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
68  ; CHECK-NEXT:    movi	   v[[REG2:[0-9]+]].8h, #1, lsl #8
69  ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
70  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
71  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
72  %rv = add <8 x i16> %in, <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256>
73  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
74  ret void
75}
76
77; CHECK-LABEL: movi_modimm_t7:
78define void @movi_modimm_t7() nounwind {
79  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
80  ; CHECK-NEXT:    movi	   v[[REG2:[0-9]+]].4s, #1, msl #8
81  ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
82  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
83  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
84  %rv = add <8 x i16> %in, <i16 511, i16 0, i16 511, i16 0, i16 511, i16 0, i16 511, i16 0>
85  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
86  ret void
87}
88
89; CHECK-LABEL: movi_modimm_t8:
90define void @movi_modimm_t8() nounwind {
91  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
92  ; CHECK-NEXT:    movi	   v[[REG2:[0-9]+]].4s, #1, msl #16
93  ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
94  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
95  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
96  %rv = add <8 x i16> %in, <i16 65535, i16 1, i16 65535, i16 1, i16 65535, i16 1, i16 65535, i16 1>
97  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
98  ret void
99}
100
101; CHECK-LABEL: movi_modimm_t9:
102define void @movi_modimm_t9() nounwind {
103  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
104  ; CHECK-NEXT:    movi	   v[[REG2:[0-9]+]].16b, #1
105  ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
106  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
107  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
108  %rv = add <8 x i16> %in, <i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257>
109  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
110  ret void
111}
112
113; CHECK-LABEL: movi_modimm_t10:
114define void @movi_modimm_t10() nounwind {
115  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
116  ; CHECK-NEXT:    movi	   v[[REG2:[0-9]+]].2d, #0x00ffff0000ffff
117  ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
118  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
119  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
120  %rv = add <8 x i16> %in, <i16 -1, i16 0, i16 -1, i16 0, i16 -1, i16 0, i16 -1, i16 0>
121  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
122  ret void
123}
124
125; CHECK-LABEL: fmov_modimm_t11:
126define void @fmov_modimm_t11() nounwind {
127  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
128  ; CHECK-NEXT:    fmov    v[[REG2:[0-9]+]].4s, #3.00000000
129  ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
130  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
131  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
132  %rv = add <8 x i16> %in, <i16 0, i16 16448, i16 0, i16 16448, i16 0, i16 16448, i16 0, i16 16448>
133  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
134  ret void
135}
136
137; CHECK-LABEL: fmov_modimm_t12:
138define void @fmov_modimm_t12() nounwind {
139  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
140  ; CHECK-NEXT:    fmov    v[[REG2:[0-9]+]].2d, #0.17968750
141  ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
142  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
143  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
144  %rv = add <8 x i16> %in, <i16 0, i16 0, i16 0, i16 16327, i16 0, i16 0, i16 0, i16 16327>
145  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
146  ret void
147}
148
149; CHECK-LABEL: mvni_modimm_t1:
150define void @mvni_modimm_t1() nounwind {
151  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
152  ; CHECK-NEXT:    mvni	   v[[REG2:[0-9]+]].4s, #1
153  ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
154  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
155  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
156  %rv = add <8 x i16> %in, <i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535>
157  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
158  ret void
159}
160
161; CHECK-LABEL: mvni_modimm_t2:
162define void @mvni_modimm_t2() nounwind {
163  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
164  ; CHECK-NEXT:    mvni	   v[[REG2:[0-9]+]].4s, #1, lsl #8
165  ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
166  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
167  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
168  %rv = add <8 x i16> %in, <i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535>
169  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
170  ret void
171}
172
173; CHECK-LABEL: mvni_modimm_t3:
174define void @mvni_modimm_t3() nounwind {
175  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
176  ; CHECK-NEXT:    mvni	   v[[REG2:[0-9]+]].4s, #1, lsl #16
177  ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
178  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
179  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
180  %rv = add <8 x i16> %in, <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534>
181  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
182  ret void
183}
184
185; CHECK-LABEL: mvni_modimm_t4:
186define void @mvni_modimm_t4() nounwind {
187  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
188  ; CHECK-NEXT:    mvni	   v[[REG2:[0-9]+]].4s, #1, lsl #24
189  ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
190  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
191  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
192  %rv = add <8 x i16> %in, <i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279>
193  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
194  ret void
195}
196
197; CHECK-LABEL: mvni_modimm_t5:
198define void @mvni_modimm_t5() nounwind {
199  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
200  ; CHECK-NEXT:    mvni	   v[[REG2:[0-9]+]].8h, #1
201  ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
202  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
203  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
204  %rv = add <8 x i16> %in, <i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534>
205  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
206  ret void
207}
208
209; CHECK-LABEL: mvni_modimm_t6:
210define void @mvni_modimm_t6() nounwind {
211  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
212  ; CHECK-NEXT:    mvni	   v[[REG2:[0-9]+]].8h, #1, lsl #8
213  ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
214  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
215  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
216  %rv = add <8 x i16> %in, <i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279>
217  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
218  ret void
219}
220
221; CHECK-LABEL: mvni_modimm_t7:
222define void @mvni_modimm_t7() nounwind {
223  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
224  ; CHECK-NEXT:    mvni	   v[[REG2:[0-9]+]].4s, #1, msl #8
225  ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
226  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
227  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
228  %rv = add <8 x i16> %in, <i16 65024, i16 65535, i16 65024, i16 65535, i16 65024, i16 65535, i16 65024, i16 65535>
229  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
230  ret void
231}
232
233; CHECK-LABEL: mvni_modimm_t8:
234define void @mvni_modimm_t8() nounwind {
235  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
236  ; CHECK-NEXT:    mvni	   v[[REG2:[0-9]+]].4s, #1, msl #16
237  ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
238  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
239  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
240  %rv = add <8 x i16> %in, <i16 0, i16 65534, i16 0, i16 65534, i16 0, i16 65534, i16 0, i16 65534>
241  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
242  ret void
243}
244
245; CHECK-LABEL: bic_modimm_t1:
246define void @bic_modimm_t1() nounwind {
247  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
248  ; CHECK-NEXT:    bic	   v[[REG2:[0-9]+]].4s, #1
249  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
250  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
251  %rv = and <8 x i16> %in, <i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535>
252  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
253  ret void
254}
255
256; CHECK-LABEL: bic_modimm_t2:
257define void @bic_modimm_t2() nounwind {
258  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
259  ; CHECK-NEXT:    bic	   v[[REG2:[0-9]+]].4s, #1, lsl #8
260  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
261  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
262  %rv = and <8 x i16> %in, <i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535>
263  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
264  ret void
265}
266
267; CHECK-LABEL: bic_modimm_t3:
268define void @bic_modimm_t3() nounwind {
269  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
270  ; CHECK-NEXT:    bic	   v[[REG2:[0-9]+]].4s, #1, lsl #16
271  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
272  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
273  %rv = and <8 x i16> %in, <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534>
274  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
275  ret void
276}
277
278; CHECK-LABEL: bic_modimm_t4:
279define void @bic_modimm_t4() nounwind {
280  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
281  ; CHECK-NEXT:    bic	   v[[REG2:[0-9]+]].4s, #1, lsl #24
282  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
283  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
284  %rv = and <8 x i16> %in, <i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279>
285  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
286  ret void
287}
288
289; CHECK-LABEL: bic_modimm_t5:
290define void @bic_modimm_t5() nounwind {
291  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
292  ; CHECK-NEXT:    bic	   v[[REG2:[0-9]+]].8h, #1
293  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
294  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
295  %rv = and <8 x i16> %in, <i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534>
296  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
297  ret void
298}
299
300; CHECK-LABEL: bic_modimm_t6:
301define void @bic_modimm_t6() nounwind {
302  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
303  ; CHECK-NEXT:    bic	   v[[REG2:[0-9]+]].8h, #1, lsl #8
304  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
305  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
306  %rv = and <8 x i16> %in, <i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279>
307  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
308  ret void
309}
310
311; CHECK-LABEL: orr_modimm_t1:
312define void @orr_modimm_t1() nounwind {
313  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
314  ; CHECK-NEXT:    orr	   v[[REG2:[0-9]+]].4s, #1
315  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
316  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
317  %rv = or <8 x i16> %in, <i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0>
318  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
319  ret void
320}
321
322; CHECK-LABEL: orr_modimm_t2:
323define void @orr_modimm_t2() nounwind {
324  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
325  ; CHECK-NEXT:    orr     v[[REG2:[0-9]+]].4s, #1, lsl #8
326  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
327  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
328  %rv = or <8 x i16> %in, <i16 256, i16 0, i16 256, i16 0, i16 256, i16 0, i16 256, i16 0>
329  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
330  ret void
331}
332
333; CHECK-LABEL: orr_modimm_t3:
334define void @orr_modimm_t3() nounwind {
335  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
336  ; CHECK-NEXT:    orr	   v[[REG2:[0-9]+]].4s, #1, lsl #16
337  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
338  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
339  %rv = or <8 x i16> %in, <i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1>
340  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
341  ret void
342}
343
344; CHECK-LABEL: orr_modimm_t4:
345define void @orr_modimm_t4() nounwind {
346  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
347  ; CHECK-NEXT:    orr	   v[[REG2:[0-9]+]].4s, #1, lsl #24
348  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
349  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
350  %rv = or <8 x i16> %in, <i16 0, i16 256, i16 0, i16 256, i16 0, i16 256, i16 0, i16 256>
351  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
352  ret void
353}
354
355; CHECK-LABEL: orr_modimm_t5:
356define void @orr_modimm_t5() nounwind {
357  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
358  ; CHECK-NEXT:    orr	   v[[REG2:[0-9]+]].8h, #1
359  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
360  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
361  %rv = or <8 x i16> %in, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
362  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
363  ret void
364}
365
366; CHECK-LABEL: orr_modimm_t6:
367define void @orr_modimm_t6() nounwind {
368  ; CHECK:         ld1     { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
369  ; CHECK-NEXT:    orr	   v[[REG2:[0-9]+]].8h, #1, lsl #8
370  ; CHECK-NEXT:    st1	   { v[[REG1]].8h }, [x{{[0-9]+}}]
371  %in = load <8 x i16>, <8 x i16>* @vec_v8i16
372  %rv = or <8 x i16> %in, <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256>
373  store <8 x i16> %rv, <8 x i16>* @vec_v8i16
374  ret void
375}
376
377declare i8 @f_v8i8(<8 x i8> %arg)
378declare i16 @f_v4i16(<4 x i16> %arg)
379declare i32 @f_v2i32(<2 x i32> %arg)
380declare i64 @f_v1i64(<1 x i64> %arg)
381declare i8 @f_v16i8(<16 x i8> %arg)
382declare i16 @f_v8i16(<8 x i16> %arg)
383declare i32 @f_v4i32(<4 x i32> %arg)
384declare i64 @f_v2i64(<2 x i64> %arg)
385
386; CHECK-LABEL: modimm_t1_call:
387define void @modimm_t1_call() {
388  ; CHECK:         movi    v[[REG1:[0-9]+]].2s, #8
389  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.8b, v[[REG1]].8b
390  ; CHECK-NEXT:    bl      f_v8i8
391  call i8 @f_v8i8(<8 x i8> <i8 8, i8 0, i8 0, i8 0, i8 8, i8 0, i8 0, i8 0>)
392  ; CHECK:         movi    v[[REG1:[0-9]+]].2s, #7
393  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.4h, v[[REG1]].4h
394  ; CHECK-NEXT:    bl      f_v4i16
395  call i16 @f_v4i16(<4 x i16> <i16 7, i16 0, i16 7, i16 0>)
396  ; CHECK:         movi    v[[REG1:[0-9]+]].2s, #6
397  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.2s, v[[REG1]].2s
398  ; CHECK-NEXT:    bl      f_v2i32
399  call i32 @f_v2i32(<2 x i32> <i32 6, i32 6>)
400  ; CHECK:         movi    v{{[0-9]+}}.2s, #5
401  ; CHECK-NEXT:    bl      f_v1i64
402  call i64 @f_v1i64(<1 x i64> <i64 21474836485>)
403  ; CHECK:         movi    v[[REG1:[0-9]+]].4s, #5
404  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].16b, v[[REG1]].16b
405  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
406  ; CHECK-NEXT:    bl      f_v16i8
407  call i8 @f_v16i8(<16 x i8> <i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0>)
408  ; CHECK:         movi    v[[REG1:[0-9]+]].4s, #4
409  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].8h, v[[REG1]].8h
410  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
411  ; CHECK-NEXT:    bl      f_v8i16
412  call i16 @f_v8i16(<8 x i16> <i16 4, i16 0, i16 4, i16 0, i16 4, i16 0, i16 4, i16 0>)
413  ; CHECK:         movi    v[[REG1:[0-9]+]].4s, #3
414  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].4s, v[[REG1]].4s
415  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
416  ; CHECK-NEXT:    bl      f_v4i32
417  call i32 @f_v4i32(<4 x i32> <i32 3, i32 3, i32 3, i32 3>)
418  ; CHECK:         movi    v[[REG:[0-9]+]].4s, #2
419  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
420  ; CHECK-NEXT:    bl      f_v2i64
421  call i64 @f_v2i64(<2 x i64> <i64 8589934594, i64 8589934594>)
422
423  ret void
424}
425
426; CHECK-LABEL: modimm_t2_call:
427define void @modimm_t2_call() {
428  ; CHECK:         movi    v[[REG1:[0-9]+]].2s, #8, lsl #8
429  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.8b, v[[REG1]].8b
430  ; CHECK-NEXT:    bl      f_v8i8
431  call i8 @f_v8i8(<8 x i8> <i8 0, i8 8, i8 0, i8 0, i8 0, i8 8, i8 0, i8 0>)
432  ; CHECK:         movi    v[[REG1:[0-9]+]].2s, #7, lsl #8
433  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.4h, v[[REG1]].4h
434  ; CHECK-NEXT:    bl      f_v4i16
435  call i16 @f_v4i16(<4 x i16> <i16 1792, i16 0, i16 1792, i16 0>)
436  ; CHECK:         movi    v[[REG1:[0-9]+]].2s, #6, lsl #8
437  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.2s, v[[REG1]].2s
438  ; CHECK-NEXT:    bl      f_v2i32
439  call i32 @f_v2i32(<2 x i32> <i32 1536, i32 1536>)
440  ; CHECK:         movi    v{{[0-9]+}}.2s, #5, lsl #8
441  ; CHECK-NEXT:    bl      f_v1i64
442  call i64 @f_v1i64(<1 x i64> <i64 5497558140160>)
443  ; CHECK:         movi    v[[REG1:[0-9]+]].4s, #5, lsl #8
444  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].16b, v[[REG1]].16b
445  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
446  ; CHECK-NEXT:    bl      f_v16i8
447  call i8 @f_v16i8(<16 x i8> <i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0>)
448  ; CHECK:         movi    v[[REG1:[0-9]+]].4s, #4, lsl #8
449  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].8h, v[[REG1]].8h
450  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
451  ; CHECK-NEXT:    bl      f_v8i16
452  call i16 @f_v8i16(<8 x i16> <i16 1024, i16 0, i16 1024, i16 0, i16 1024, i16 0, i16 1024, i16 0>)
453  ; CHECK:         movi    v[[REG1:[0-9]+]].4s, #3, lsl #8
454  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].4s, v[[REG1]].4s
455  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
456  ; CHECK-NEXT:    bl      f_v4i32
457  call i32 @f_v4i32(<4 x i32> <i32 768, i32 768, i32 768, i32 768>)
458  ; CHECK:         movi    v[[REG:[0-9]+]].4s, #2, lsl #8
459  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
460  ; CHECK-NEXT:    bl      f_v2i64
461  call i64 @f_v2i64(<2 x i64> <i64 2199023256064, i64 2199023256064>)
462
463  ret void
464}
465
466; CHECK-LABEL: modimm_t3_call:
467define void @modimm_t3_call() {
468  ; CHECK:         movi    v[[REG1:[0-9]+]].2s, #8, lsl #16
469  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.8b, v[[REG1]].8b
470  ; CHECK-NEXT:    bl      f_v8i8
471  call i8 @f_v8i8(<8 x i8> <i8 0, i8 0, i8 8, i8 0, i8 0, i8 0, i8 8, i8 0>)
472  ; CHECK:         movi    v[[REG1:[0-9]+]].2s, #7, lsl #16
473  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.4h, v[[REG1]].4h
474  ; CHECK-NEXT:    bl      f_v4i16
475  call i16 @f_v4i16(<4 x i16> <i16 0, i16 7, i16 0, i16 7>)
476  ; CHECK:         movi    v[[REG1:[0-9]+]].2s, #6, lsl #16
477  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.2s, v[[REG1]].2s
478  ; CHECK-NEXT:    bl      f_v2i32
479  call i32 @f_v2i32(<2 x i32> <i32 393216, i32 393216>)
480  ; CHECK:         movi    v{{[0-9]+}}.2s, #5, lsl #16
481  ; CHECK-NEXT:    bl      f_v1i64
482  call i64 @f_v1i64(<1 x i64> <i64 1407374883880960>)
483  ; CHECK:         movi    v[[REG1:[0-9]+]].4s, #5, lsl #16
484  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].16b, v[[REG1]].16b
485  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
486  ; CHECK-NEXT:    bl      f_v16i8
487  call i8 @f_v16i8(<16 x i8> <i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0>)
488  ; CHECK:         movi    v[[REG1:[0-9]+]].4s, #4, lsl #16
489  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].8h, v[[REG1]].8h
490  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
491  ; CHECK-NEXT:    bl      f_v8i16
492  call i16 @f_v8i16(<8 x i16> <i16 0, i16 4, i16 0, i16 4, i16 0, i16 4, i16 0, i16 4>)
493  ; CHECK:         movi    v[[REG1:[0-9]+]].4s, #3, lsl #16
494  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].4s, v[[REG1]].4s
495  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
496  ; CHECK-NEXT:    bl      f_v4i32
497  call i32 @f_v4i32(<4 x i32> <i32 196608, i32 196608, i32 196608, i32 196608>)
498  ; CHECK:         movi    v[[REG:[0-9]+]].4s, #2, lsl #16
499  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
500  ; CHECK-NEXT:    bl      f_v2i64
501  call i64 @f_v2i64(<2 x i64> <i64 562949953552384, i64 562949953552384>)
502
503  ret void
504}
505
506; CHECK-LABEL: modimm_t4_call:
507define void @modimm_t4_call() {
508  ; CHECK:         movi    v[[REG1:[0-9]+]].2s, #8, lsl #24
509  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.8b, v[[REG1]].8b
510  ; CHECK-NEXT:    bl      f_v8i8
511  call i8 @f_v8i8(<8 x i8> <i8 0, i8 0, i8 0, i8 8, i8 0, i8 0, i8 0, i8 8>)
512  ; CHECK:         movi    v[[REG1:[0-9]+]].2s, #7, lsl #24
513  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.4h, v[[REG1]].4h
514  ; CHECK-NEXT:    bl      f_v4i16
515  call i16 @f_v4i16(<4 x i16> <i16 0, i16 1792, i16 0, i16 1792>)
516  ; CHECK:         movi    v[[REG1:[0-9]+]].2s, #6, lsl #24
517  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.2s, v[[REG1]].2s
518  ; CHECK-NEXT:    bl      f_v2i32
519  call i32 @f_v2i32(<2 x i32> <i32 100663296, i32 100663296>)
520  ; CHECK:         movi    v{{[0-9]+}}.2s, #5, lsl #24
521  ; CHECK-NEXT:    bl      f_v1i64
522  call i64 @f_v1i64(<1 x i64> <i64 360287970273525760>)
523  ; CHECK:         movi    v[[REG1:[0-9]+]].4s, #5, lsl #24
524  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].16b, v[[REG1]].16b
525  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
526  ; CHECK-NEXT:    bl      f_v16i8
527  call i8 @f_v16i8(<16 x i8> <i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5>)
528  ; CHECK:         movi    v[[REG1:[0-9]+]].4s, #4, lsl #24
529  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].8h, v[[REG1]].8h
530  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
531  ; CHECK-NEXT:    bl      f_v8i16
532  call i16 @f_v8i16(<8 x i16> <i16 0, i16 1024, i16 0, i16 1024, i16 0, i16 1024, i16 0, i16 1024>)
533  ; CHECK:         movi    v[[REG1:[0-9]+]].4s, #3, lsl #24
534  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].4s, v[[REG1]].4s
535  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
536  ; CHECK-NEXT:    bl      f_v4i32
537  call i32 @f_v4i32(<4 x i32> <i32 50331648, i32 50331648, i32 50331648, i32 50331648>)
538  ; CHECK:         movi    v[[REG:[0-9]+]].4s, #2, lsl #24
539  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
540  ; CHECK-NEXT:    bl      f_v2i64
541  call i64 @f_v2i64(<2 x i64> <i64 144115188109410304, i64 144115188109410304>)
542
543  ret void
544}
545
546; CHECK-LABEL: modimm_t5_call:
547define void @modimm_t5_call() {
548  ; CHECK:         movi    v[[REG1:[0-9]+]].4h, #8
549  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.8b, v[[REG1]].8b
550  ; CHECK-NEXT:    bl      f_v8i8
551  call i8 @f_v8i8(<8 x i8> <i8 8, i8 0, i8 8, i8 0, i8 8, i8 0, i8 8, i8 0>)
552  ; CHECK:         movi    v[[REG1:[0-9]+]].4h, #7
553  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.4h, v[[REG1]].4h
554  ; CHECK-NEXT:    bl      f_v4i16
555  call i16 @f_v4i16(<4 x i16> <i16 7, i16 7, i16 7, i16 7>)
556  ; CHECK:         movi    v[[REG1:[0-9]+]].4h, #6
557  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.2s, v[[REG1]].2s
558  ; CHECK-NEXT:    bl      f_v2i32
559  call i32 @f_v2i32(<2 x i32> <i32 393222, i32 393222>)
560  ; CHECK:         movi    v{{[0-9]+}}.4h, #5
561  ; CHECK-NEXT:    bl      f_v1i64
562  call i64 @f_v1i64(<1 x i64> <i64 1407396358717445>)
563  ; CHECK:         movi    v[[REG1:[0-9]+]].8h, #5
564  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].16b, v[[REG1]].16b
565  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
566  ; CHECK-NEXT:    bl      f_v16i8
567  call i8 @f_v16i8(<16 x i8> <i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0>)
568  ; CHECK:         movi    v[[REG1:[0-9]+]].8h, #4
569  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].8h, v[[REG1]].8h
570  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
571  ; CHECK-NEXT:    bl      f_v8i16
572  call i16 @f_v8i16(<8 x i16> <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>)
573  ; CHECK:         movi    v[[REG1:[0-9]+]].8h, #3
574  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].4s, v[[REG1]].4s
575  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
576  ; CHECK-NEXT:    bl      f_v4i32
577  call i32 @f_v4i32(<4 x i32> <i32 196611, i32 196611, i32 196611, i32 196611>)
578  ; CHECK:         movi    v[[REG:[0-9]+]].8h, #2
579  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
580  ; CHECK-NEXT:    bl      f_v2i64
581  call i64 @f_v2i64(<2 x i64> <i64 562958543486978, i64 562958543486978>)
582
583  ret void
584}
585
586; CHECK-LABEL: modimm_t6_call:
587define void @modimm_t6_call() {
588  ; CHECK:         movi    v[[REG1:[0-9]+]].4h, #8, lsl #8
589  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.8b, v[[REG1]].8b
590  ; CHECK-NEXT:    bl      f_v8i8
591  call i8 @f_v8i8(<8 x i8> <i8 0, i8 8, i8 0, i8 8, i8 0, i8 8, i8 0, i8 8>)
592  ; CHECK:         movi    v[[REG1:[0-9]+]].4h, #7, lsl #8
593  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.4h, v[[REG1]].4h
594  ; CHECK-NEXT:    bl      f_v4i16
595  call i16 @f_v4i16(<4 x i16> <i16 1792, i16 1792, i16 1792, i16 1792>)
596  ; CHECK:         movi    v[[REG1:[0-9]+]].4h, #6, lsl #8
597  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.2s, v[[REG1]].2s
598  ; CHECK-NEXT:    bl      f_v2i32
599  call i32 @f_v2i32(<2 x i32> <i32 100664832, i32 100664832>)
600  ; CHECK:         movi    v{{[0-9]+}}.4h, #5, lsl #8
601  ; CHECK-NEXT:    bl      f_v1i64
602  call i64 @f_v1i64(<1 x i64> <i64 360293467831665920>)
603  ; CHECK:         movi    v[[REG1:[0-9]+]].8h, #5, lsl #8
604  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].16b, v[[REG1]].16b
605  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
606  ; CHECK-NEXT:    bl      f_v16i8
607  call i8 @f_v16i8(<16 x i8> <i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5>)
608  ; CHECK:         movi    v[[REG1:[0-9]+]].8h, #4, lsl #8
609  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].8h, v[[REG1]].8h
610  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
611  ; CHECK-NEXT:    bl      f_v8i16
612  call i16 @f_v8i16(<8 x i16> <i16 1024, i16 1024, i16 1024, i16 1024, i16 1024, i16 1024, i16 1024, i16 1024>)
613  ; CHECK:         movi    v[[REG1:[0-9]+]].8h, #3, lsl #8
614  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].4s, v[[REG1]].4s
615  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
616  ; CHECK-NEXT:    bl      f_v4i32
617  call i32 @f_v4i32(<4 x i32> <i32 50332416, i32 50332416, i32 50332416, i32 50332416>)
618  ; CHECK:         movi    v[[REG:[0-9]+]].8h, #2, lsl #8
619  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
620  ; CHECK-NEXT:    bl      f_v2i64
621  call i64 @f_v2i64(<2 x i64> <i64 144117387132666368, i64 144117387132666368>)
622
623  ret void
624}
625
626; CHECK-LABEL: modimm_t7_call:
627define void @modimm_t7_call() {
628  ; CHECK:         movi    v[[REG1:[0-9]+]].2s, #8, msl #8
629  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.8b, v[[REG1]].8b
630  ; CHECK-NEXT:    bl      f_v8i8
631  call i8 @f_v8i8(<8 x i8> <i8 255, i8 8, i8 0, i8 0, i8 255, i8 8, i8 0, i8 0>)
632  ; CHECK:         movi    v[[REG1:[0-9]+]].2s, #7, msl #8
633  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.4h, v[[REG1]].4h
634  ; CHECK-NEXT:    bl      f_v4i16
635  call i16 @f_v4i16(<4 x i16> <i16 2047, i16 0, i16 2047, i16 0>)
636  ; CHECK:         movi    v[[REG1:[0-9]+]].2s, #6, msl #8
637  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.2s, v[[REG1]].2s
638  ; CHECK-NEXT:    bl      f_v2i32
639  call i32 @f_v2i32(<2 x i32> <i32 1791, i32 1791>)
640  ; CHECK:         movi    v{{[0-9]+}}.2s, #5, msl #8
641  ; CHECK-NEXT:    bl      f_v1i64
642  call i64 @f_v1i64(<1 x i64> <i64 6592774800895>)
643  ; CHECK:         movi    v[[REG1:[0-9]+]].4s, #5, msl #8
644  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].16b, v[[REG1]].16b
645  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
646  ; CHECK-NEXT:    bl      f_v16i8
647  call i8 @f_v16i8(<16 x i8> <i8 255, i8 5, i8 0, i8 0, i8 255, i8 5, i8 0, i8 0, i8 255, i8 5, i8 0, i8 0, i8 255, i8 5, i8 0, i8 0>)
648  ; CHECK:         movi    v[[REG1:[0-9]+]].4s, #4, msl #8
649  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].8h, v[[REG1]].8h
650  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
651  ; CHECK-NEXT:    bl      f_v8i16
652  call i16 @f_v8i16(<8 x i16> <i16 1279, i16 0, i16 1279, i16 0, i16 1279, i16 0, i16 1279, i16 0>)
653  ; CHECK:         movi    v[[REG1:[0-9]+]].4s, #3, msl #8
654  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].4s, v[[REG1]].4s
655  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
656  ; CHECK-NEXT:    bl      f_v4i32
657  call i32 @f_v4i32(<4 x i32> <i32 1023, i32 1023, i32 1023, i32 1023>)
658  ; CHECK:         movi    v[[REG:[0-9]+]].4s, #2, msl #8
659  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
660  ; CHECK-NEXT:    bl      f_v2i64
661  call i64 @f_v2i64(<2 x i64> <i64 3294239916799, i64 3294239916799>)
662
663  ret void
664}
665
666; CHECK-LABEL: modimm_t8_call:
667define void @modimm_t8_call() {
668  ; CHECK:         movi    v[[REG1:[0-9]+]].2s, #8, msl #16
669  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.8b, v[[REG1]].8b
670  ; CHECK-NEXT:    bl      f_v8i8
671  call i8 @f_v8i8(<8 x i8> <i8 255, i8 255, i8 8, i8 0, i8 255, i8 255, i8 8, i8 0>)
672  ; CHECK:         movi    v[[REG1:[0-9]+]].2s, #7, msl #16
673  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.4h, v[[REG1]].4h
674  ; CHECK-NEXT:    bl      f_v4i16
675  call i16 @f_v4i16(<4 x i16> <i16 65535, i16 7, i16 65535, i16 7>)
676  ; CHECK:         movi    v[[REG1:[0-9]+]].2s, #6, msl #16
677  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.2s, v[[REG1]].2s
678  ; CHECK-NEXT:    bl      f_v2i32
679  call i32 @f_v2i32(<2 x i32> <i32 458751, i32 458751>)
680  ; CHECK:         movi    v{{[0-9]+}}.2s, #5, msl #16
681  ; CHECK-NEXT:    bl      f_v1i64
682  call i64 @f_v1i64(<1 x i64> <i64 1688845565689855>)
683  ; CHECK:         movi    v[[REG1:[0-9]+]].4s, #5, msl #16
684  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].16b, v[[REG1]].16b
685  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
686  ; CHECK-NEXT:    bl      f_v16i8
687  call i8 @f_v16i8(<16 x i8> <i8 255, i8 255, i8 5, i8 0, i8 255, i8 255, i8 5, i8 0, i8 255, i8 255, i8 5, i8 0, i8 255, i8 255, i8 5, i8 0>)
688  ; CHECK:         movi    v[[REG1:[0-9]+]].4s, #4, msl #16
689  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].8h, v[[REG1]].8h
690  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
691  ; CHECK-NEXT:    bl      f_v8i16
692  call i16 @f_v8i16(<8 x i16> <i16 65535, i16 4, i16 65535, i16 4, i16 65535, i16 4, i16 65535, i16 4>)
693  ; CHECK:         movi    v[[REG1:[0-9]+]].4s, #3, msl #16
694  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].4s, v[[REG1]].4s
695  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
696  ; CHECK-NEXT:    bl      f_v4i32
697  call i32 @f_v4i32(<4 x i32> <i32 262143, i32 262143, i32 262143, i32 262143>)
698  ; CHECK:         movi    v[[REG:[0-9]+]].4s, #2, msl #16
699  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
700  ; CHECK-NEXT:    bl      f_v2i64
701  call i64 @f_v2i64(<2 x i64> <i64 844420635361279, i64 844420635361279>)
702
703  ret void
704}
705
706; CHECK-LABEL: modimm_t9_call:
707define void @modimm_t9_call() {
708  ; CHECK:         movi    v[[REG1:[0-9]+]].8b, #8
709  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.8b, v[[REG1]].8b
710  ; CHECK-NEXT:    bl      f_v8i8
711  call i8 @f_v8i8(<8 x i8> <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>)
712  ; CHECK:         movi    v[[REG1:[0-9]+]].8b, #7
713  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.4h, v[[REG1]].4h
714  ; CHECK-NEXT:    bl      f_v4i16
715  call i16 @f_v4i16(<4 x i16> <i16 1799, i16 1799, i16 1799, i16 1799>)
716  ; CHECK:         movi    v[[REG1:[0-9]+]].8b, #6
717  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.2s, v[[REG1]].2s
718  ; CHECK-NEXT:    bl      f_v2i32
719  call i32 @f_v2i32(<2 x i32> <i32 101058054, i32 101058054>)
720  ; CHECK:         movi    v[[REG1:[0-9]+]].16b, #5
721  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].16b, v[[REG1]].16b
722  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
723  ; CHECK-NEXT:    bl      f_v16i8
724  call i8 @f_v16i8(<16 x i8> <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>)
725  ; CHECK:         movi    v[[REG1:[0-9]+]].16b, #4
726  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].8h, v[[REG1]].8h
727  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
728  ; CHECK-NEXT:    bl      f_v8i16
729  call i16 @f_v8i16(<8 x i16> <i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028>)
730  ; CHECK:         movi    v[[REG1:[0-9]+]].16b, #3
731  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].4s, v[[REG1]].4s
732  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
733  ; CHECK-NEXT:    bl      f_v4i32
734  call i32 @f_v4i32(<4 x i32> <i32 50529027, i32 50529027, i32 50529027, i32 50529027>)
735
736  ret void
737}
738
739; CHECK-LABEL: modimm_t10_call:
740define void @modimm_t10_call() {
741  ; CHECK:         movi    d[[REG1:[0-9]+]], #0x0000ff000000ff
742  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.8b, v[[REG1]].8b
743  ; CHECK-NEXT:    bl      f_v8i8
744  call i8 @f_v8i8(<8 x i8> <i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 0, i8 0>)
745  ; CHECK:         movi    d[[REG1:[0-9]+]], #0x00ffff0000ffff
746  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.4h, v[[REG1]].4h
747  ; CHECK-NEXT:    bl      f_v4i16
748  call i16 @f_v4i16(<4 x i16> <i16 -1, i16 0, i16 -1, i16 0>)
749  ; CHECK:         movi    v[[REG1:[0-9]+]].2d, #0xffffffffffffffff
750  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.2s, v[[REG1]].2s
751  ; CHECK-NEXT:    bl      f_v2i32
752  call i32 @f_v2i32(<2 x i32> <i32 -1, i32 -1>)
753  ; CHECK:         movi    v[[REG1:[0-9]+]].2d, #0xffffff00ffffff
754  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].16b, v[[REG1]].16b
755  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
756  ; CHECK-NEXT:    bl      f_v16i8
757  call i8 @f_v16i8(<16 x i8> <i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0>)
758  ; CHECK:         movi    v[[REG1:[0-9]+]].2d, #0xffffffffffff0000
759  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].8h, v[[REG1]].8h
760  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
761  ; CHECK-NEXT:    bl      f_v8i16
762  call i16 @f_v8i16(<8 x i16> <i16 0, i16 -1, i16 -1, i16 -1, i16 0, i16 -1, i16 -1, i16 -1>)
763  ; CHECK:         movi    v[[REG1:[0-9]+]].2d, #0xffffffff00000000
764  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].4s, v[[REG1]].4s
765  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
766  ; CHECK-NEXT:    bl      f_v4i32
767  call i32 @f_v4i32(<4 x i32> <i32 0, i32 -1, i32 0, i32 -1>)
768
769  ret void
770}
771
772; CHECK-LABEL: modimm_t11_call:
773define void @modimm_t11_call() {
774  ; CHECK:         fmov    v[[REG1:[0-9]+]].2s, #4.00000000
775  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.8b, v[[REG1]].8b
776  ; CHECK-NEXT:    bl      f_v8i8
777  call i8 @f_v8i8(<8 x i8> <i8 0, i8 0, i8 128, i8 64, i8 0, i8 0, i8 128, i8 64>)
778  ; CHECK:         fmov    v[[REG1:[0-9]+]].2s, #3.75000000
779  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.4h, v[[REG1]].4h
780  ; CHECK-NEXT:    bl      f_v4i16
781  call i16 @f_v4i16(<4 x i16> <i16 0, i16 16496, i16 0, i16 16496>)
782  ; CHECK:         fmov    v[[REG1:[0-9]+]].2s, #3.50000000
783  ; CHECK-NEXT:    rev64   v{{[0-9]+}}.2s, v[[REG1]].2s
784  ; CHECK-NEXT:    bl      f_v2i32
785  call i32 @f_v2i32(<2 x i32> <i32 1080033280, i32 1080033280>)
786  ; CHECK:         fmov    v{{[0-9]+}}.2s, #0.39062500
787  ; CHECK-NEXT:    bl      f_v1i64
788  call i64 @f_v1i64(<1 x i64> <i64 4523865826746957824>)
789  ; CHECK:         fmov    v[[REG1:[0-9]+]].4s, #3.25000000
790  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].16b, v[[REG1]].16b
791  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
792  ; CHECK-NEXT:    bl      f_v16i8
793  call i8 @f_v16i8(<16 x i8> <i8 0, i8 0, i8 80, i8 64, i8 0, i8 0, i8 80, i8 64, i8 0, i8 0, i8 80, i8 64, i8 0, i8 0, i8 80, i8 64>)
794  ; CHECK:         fmov    v[[REG1:[0-9]+]].4s, #3.00000000
795  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].8h, v[[REG1]].8h
796  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
797  ; CHECK-NEXT:    bl      f_v8i16
798  call i16 @f_v8i16(<8 x i16> <i16 0, i16 16448, i16 0, i16 16448, i16 0, i16 16448, i16 0, i16 16448>)
799  ; CHECK:         fmov    v[[REG1:[0-9]+]].4s, #2.75000000
800  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].4s, v[[REG1]].4s
801  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
802  ; CHECK-NEXT:    bl      f_v4i32
803  call i32 @f_v4i32(<4 x i32> <i32 1076887552, i32 1076887552, i32 1076887552, i32 1076887552>)
804  ; CHECK:         fmov    v[[REG:[0-9]+]].4s, #2.5000000
805  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
806  ; CHECK-NEXT:    bl      f_v2i64
807  call i64 @f_v2i64(<2 x i64> <i64 4620693218757967872, i64 4620693218757967872>)
808
809  ret void
810}
811
812; CHECK-LABEL: modimm_t12_call:
813define void @modimm_t12_call() {
814  ; CHECK:         fmov    v[[REG1:[0-9]+]].2d, #0.18750000
815  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].16b, v[[REG1]].16b
816  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
817  ; CHECK-NEXT:    bl      f_v16i8
818  call i8 @f_v16i8(<16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 200, i8 63, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 200, i8 63>)
819  ; CHECK:         fmov    v[[REG1:[0-9]+]].2d, #0.17968750
820  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].8h, v[[REG1]].8h
821  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
822  ; CHECK-NEXT:    bl      f_v8i16
823  call i16 @f_v8i16(<8 x i16> <i16 0, i16 0, i16 0, i16 16327, i16 0, i16 0, i16 0, i16 16327>)
824  ; CHECK:         fmov    v[[REG1:[0-9]+]].2d, #0.17187500
825  ; CHECK-NEXT:    rev64   v[[REG2:[0-9]+]].4s, v[[REG1]].4s
826  ; CHECK-NEXT:    ext     v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
827  ; CHECK-NEXT:    bl      f_v4i32
828  call i32 @f_v4i32(<4 x i32> <i32 0, i32 1069940736, i32 0, i32 1069940736>)
829
830  ret void
831}
832