1; RUN: llc -mtriple=arm64-eabi -mattr=crypto -aarch64-neon-syntax=apple -o - %s | FileCheck %s 2; RUN: llc -mtriple=arm64-eabi -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mattr=crypto -aarch64-neon-syntax=apple -o - %s 2>&1 | FileCheck %s --check-prefixes=CHECK,FALLBACK 3 4declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %data, <16 x i8> %key) 5declare <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8> %data, <16 x i8> %key) 6declare <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %data) 7declare <16 x i8> @llvm.aarch64.crypto.aesimc(<16 x i8> %data) 8 9define <16 x i8> @test_aese(<16 x i8> %data, <16 x i8> %key) { 10; CHECK-LABEL: test_aese: 11; CHECK: aese.16b v0, v1 12 %res = call <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %data, <16 x i8> %key) 13 ret <16 x i8> %res 14} 15 16define <16 x i8> @test_aesd(<16 x i8> %data, <16 x i8> %key) { 17; CHECK-LABEL: test_aesd: 18; CHECK: aesd.16b v0, v1 19 %res = call <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8> %data, <16 x i8> %key) 20 ret <16 x i8> %res 21} 22 23define <16 x i8> @test_aesmc(<16 x i8> %data) { 24; CHECK-LABEL: test_aesmc: 25; CHECK: aesmc.16b v0, v0 26 %res = call <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %data) 27 ret <16 x i8> %res 28} 29 30define <16 x i8> @test_aesimc(<16 x i8> %data) { 31; CHECK-LABEL: test_aesimc: 32; CHECK: aesimc.16b v0, v0 33 %res = call <16 x i8> @llvm.aarch64.crypto.aesimc(<16 x i8> %data) 34 ret <16 x i8> %res 35} 36 37declare <4 x i32> @llvm.aarch64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) 38declare <4 x i32> @llvm.aarch64.crypto.sha1p(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) 39declare <4 x i32> @llvm.aarch64.crypto.sha1m(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) 40declare i32 @llvm.aarch64.crypto.sha1h(i32 %hash_e) 41declare <4 x i32> @llvm.aarch64.crypto.sha1su0(<4 x i32> %wk0_3, <4 x i32> %wk4_7, <4 x i32> %wk8_11) 42declare <4 x i32> @llvm.aarch64.crypto.sha1su1(<4 x i32> %wk0_3, <4 x i32> %wk12_15) 43 44define <4 x i32> @test_sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) { 45; CHECK-LABEL: test_sha1c: 46; CHECK: fmov [[HASH_E:s[0-9]+]], w0 47; CHECK: sha1c.4s q0, [[HASH_E]], v1 48 %res = call <4 x i32> @llvm.aarch64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) 49 ret <4 x i32> %res 50} 51 52; <rdar://problem/14742333> Incomplete removal of unnecessary FMOV instructions in intrinsic SHA1 53define <4 x i32> @test_sha1c_in_a_row(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) { 54; CHECK-LABEL: test_sha1c_in_a_row: 55; CHECK: fmov [[HASH_E:s[0-9]+]], w0 56; CHECK: sha1c.4s q[[SHA1RES:[0-9]+]], [[HASH_E]], v1 57; CHECK-NOT: fmov 58; CHECK: sha1c.4s q0, s[[SHA1RES]], v1 59 %res = call <4 x i32> @llvm.aarch64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) 60 %extract = extractelement <4 x i32> %res, i32 0 61 %res2 = call <4 x i32> @llvm.aarch64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %extract, <4 x i32> %wk) 62 ret <4 x i32> %res2 63} 64 65define <4 x i32> @test_sha1p(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) { 66; CHECK-LABEL: test_sha1p: 67; CHECK: fmov [[HASH_E:s[0-9]+]], w0 68; CHECK: sha1p.4s q0, [[HASH_E]], v1 69 %res = call <4 x i32> @llvm.aarch64.crypto.sha1p(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) 70 ret <4 x i32> %res 71} 72 73define <4 x i32> @test_sha1m(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) { 74; CHECK-LABEL: test_sha1m: 75; CHECK: fmov [[HASH_E:s[0-9]+]], w0 76; CHECK: sha1m.4s q0, [[HASH_E]], v1 77 %res = call <4 x i32> @llvm.aarch64.crypto.sha1m(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) 78 ret <4 x i32> %res 79} 80 81; FALLBACK-NOT: remark{{.*}}test_sha1h 82define i32 @test_sha1h(i32 %hash_e) { 83; CHECK-LABEL: test_sha1h: 84; CHECK: fmov [[HASH_E:s[0-9]+]], w0 85; CHECK: sha1h [[RES:s[0-9]+]], [[HASH_E]] 86; CHECK: fmov w0, [[RES]] 87 %res = call i32 @llvm.aarch64.crypto.sha1h(i32 %hash_e) 88 ret i32 %res 89} 90 91define <4 x i32> @test_sha1su0(<4 x i32> %wk0_3, <4 x i32> %wk4_7, <4 x i32> %wk8_11) { 92; CHECK-LABEL: test_sha1su0: 93; CHECK: sha1su0.4s v0, v1, v2 94 %res = call <4 x i32> @llvm.aarch64.crypto.sha1su0(<4 x i32> %wk0_3, <4 x i32> %wk4_7, <4 x i32> %wk8_11) 95 ret <4 x i32> %res 96} 97 98define <4 x i32> @test_sha1su1(<4 x i32> %wk0_3, <4 x i32> %wk12_15) { 99; CHECK-LABEL: test_sha1su1: 100; CHECK: sha1su1.4s v0, v1 101 %res = call <4 x i32> @llvm.aarch64.crypto.sha1su1(<4 x i32> %wk0_3, <4 x i32> %wk12_15) 102 ret <4 x i32> %res 103} 104 105declare <4 x i32> @llvm.aarch64.crypto.sha256h(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk) 106declare <4 x i32> @llvm.aarch64.crypto.sha256h2(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk) 107declare <4 x i32> @llvm.aarch64.crypto.sha256su0(<4 x i32> %w0_3, <4 x i32> %w4_7) 108declare <4 x i32> @llvm.aarch64.crypto.sha256su1(<4 x i32> %w0_3, <4 x i32> %w8_11, <4 x i32> %w12_15) 109 110define <4 x i32> @test_sha256h(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk) { 111; CHECK-LABEL: test_sha256h: 112; CHECK: sha256h.4s q0, q1, v2 113 %res = call <4 x i32> @llvm.aarch64.crypto.sha256h(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk) 114 ret <4 x i32> %res 115} 116 117define <4 x i32> @test_sha256h2(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk) { 118; CHECK-LABEL: test_sha256h2: 119; CHECK: sha256h2.4s q0, q1, v2 120 121 %res = call <4 x i32> @llvm.aarch64.crypto.sha256h2(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk) 122 ret <4 x i32> %res 123} 124 125define <4 x i32> @test_sha256su0(<4 x i32> %w0_3, <4 x i32> %w4_7) { 126; CHECK-LABEL: test_sha256su0: 127; CHECK: sha256su0.4s v0, v1 128 %res = call <4 x i32> @llvm.aarch64.crypto.sha256su0(<4 x i32> %w0_3, <4 x i32> %w4_7) 129 ret <4 x i32> %res 130} 131 132define <4 x i32> @test_sha256su1(<4 x i32> %w0_3, <4 x i32> %w8_11, <4 x i32> %w12_15) { 133; CHECK-LABEL: test_sha256su1: 134; CHECK: sha256su1.4s v0, v1, v2 135 %res = call <4 x i32> @llvm.aarch64.crypto.sha256su1(<4 x i32> %w0_3, <4 x i32> %w8_11, <4 x i32> %w12_15) 136 ret <4 x i32> %res 137} 138