1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=aarch64-eabi | FileCheck %s
3
4;==--------------------------------------------------------------------------==
5; Tests for MOV-immediate implemented with ORR-immediate.
6;==--------------------------------------------------------------------------==
7
8; 64-bit immed with 32-bit pattern size, rotated by 0.
9define i64 @test64_32_rot0() nounwind {
10; CHECK-LABEL: test64_32_rot0:
11; CHECK:       // %bb.0:
12; CHECK-NEXT:    mov x0, #30064771079
13; CHECK-NEXT:    ret
14  ret i64 30064771079
15}
16
17; 64-bit immed with 32-bit pattern size, rotated by 2.
18define i64 @test64_32_rot2() nounwind {
19; CHECK-LABEL: test64_32_rot2:
20; CHECK:       // %bb.0:
21; CHECK-NEXT:    mov x0, #-4611686002321260541
22; CHECK-NEXT:    ret
23  ret i64 13835058071388291075
24}
25
26; 64-bit immed with 4-bit pattern size, rotated by 3.
27define i64 @test64_4_rot3() nounwind {
28; CHECK-LABEL: test64_4_rot3:
29; CHECK:       // %bb.0:
30; CHECK-NEXT:    mov x0, #-1229782938247303442
31; CHECK-NEXT:    ret
32  ret i64 17216961135462248174
33}
34
35; 64-bit immed with 64-bit pattern size, many bits.
36define i64 @test64_64_manybits() nounwind {
37; CHECK-LABEL: test64_64_manybits:
38; CHECK:       // %bb.0:
39; CHECK-NEXT:    mov x0, #4503599627304960
40; CHECK-NEXT:    ret
41  ret i64 4503599627304960
42}
43
44; 64-bit immed with 64-bit pattern size, one bit.
45define i64 @test64_64_onebit() nounwind {
46; CHECK-LABEL: test64_64_onebit:
47; CHECK:       // %bb.0:
48; CHECK-NEXT:    mov x0, #274877906944
49; CHECK-NEXT:    ret
50  ret i64 274877906944
51}
52
53; 32-bit immed with 32-bit pattern size, rotated by 16.
54define i32 @test32_32_rot16() nounwind {
55; CHECK-LABEL: test32_32_rot16:
56; CHECK:       // %bb.0:
57; CHECK-NEXT:    mov w0, #16711680
58; CHECK-NEXT:    ret
59  ret i32 16711680
60}
61
62; 32-bit immed with 2-bit pattern size, rotated by 1.
63define i32 @test32_2_rot1() nounwind {
64; CHECK-LABEL: test32_2_rot1:
65; CHECK:       // %bb.0:
66; CHECK-NEXT:    mov w0, #-1431655766
67; CHECK-NEXT:    ret
68  ret i32 2863311530
69}
70
71;==--------------------------------------------------------------------------==
72; Tests for MOVZ with MOVK.
73;==--------------------------------------------------------------------------==
74
75define i32 @movz() nounwind {
76; CHECK-LABEL: movz:
77; CHECK:       // %bb.0:
78; CHECK-NEXT:    mov w0, #5
79; CHECK-NEXT:    ret
80  ret i32 5
81}
82
83define i64 @movz_3movk() nounwind {
84; CHECK-LABEL: movz_3movk:
85; CHECK:       // %bb.0:
86; CHECK-NEXT:    mov x0, #22136
87; CHECK-NEXT:    movk x0, #43981, lsl #16
88; CHECK-NEXT:    movk x0, #4660, lsl #32
89; CHECK-NEXT:    movk x0, #5, lsl #48
90; CHECK-NEXT:    ret
91  ret i64 1427392313513592
92}
93
94define i64 @movz_movk_skip1() nounwind {
95; CHECK-LABEL: movz_movk_skip1:
96; CHECK:       // %bb.0:
97; CHECK-NEXT:    mov x0, #1126236160
98; CHECK-NEXT:    movk x0, #5, lsl #32
99; CHECK-NEXT:    ret
100  ret i64 22601072640
101}
102
103define i64 @movz_skip1_movk() nounwind {
104; CHECK-LABEL: movz_skip1_movk:
105; CHECK:       // %bb.0:
106; CHECK-NEXT:    mov x0, #4660
107; CHECK-NEXT:    movk x0, #34388, lsl #32
108; CHECK-NEXT:    ret
109  ret i64 147695335379508
110}
111
112; FIXME: Prefer "mov w0, #2863311530; lsl x0, x0, #4"
113; or "mov x0, #-6148914691236517206; and x0, x0, #45812984480"
114define i64 @orr_lsl_pattern() nounwind {
115; CHECK-LABEL: orr_lsl_pattern:
116; CHECK:       // %bb.0:
117; CHECK-NEXT:    mov x0, #43680
118; CHECK-NEXT:    movk x0, #43690, lsl #16
119; CHECK-NEXT:    movk x0, #10, lsl #32
120; CHECK-NEXT:    ret
121  ret i64 45812984480
122}
123
124; FIXME: prefer "mov x0, #-16639; lsl x0, x0, #24"
125define i64 @mvn_lsl_pattern() nounwind {
126; CHECK-LABEL: mvn_lsl_pattern:
127; CHECK:       // %bb.0:
128; CHECK-NEXT:    mov x0, #16777216
129; CHECK-NEXT:    movk x0, #65471, lsl #32
130; CHECK-NEXT:    movk x0, #65535, lsl #48
131; CHECK-NEXT:    ret
132  ret i64 -279156097024
133}
134
135; FIXME: prefer "mov w0, #-63; movk x0, #17, lsl #32"
136define i64 @mvn32_pattern_2() nounwind {
137; CHECK-LABEL: mvn32_pattern_2:
138; CHECK:       // %bb.0:
139; CHECK-NEXT:    mov x0, #65473
140; CHECK-NEXT:    movk x0, #65535, lsl #16
141; CHECK-NEXT:    movk x0, #17, lsl #32
142; CHECK-NEXT:    ret
143  ret i64 77309411265
144}
145
146;==--------------------------------------------------------------------------==
147; Tests for MOVN with MOVK.
148;==--------------------------------------------------------------------------==
149
150define i64 @movn() nounwind {
151; CHECK-LABEL: movn:
152; CHECK:       // %bb.0:
153; CHECK-NEXT:    mov x0, #-42
154; CHECK-NEXT:    ret
155  ret i64 -42
156}
157
158define i64 @movn_skip1_movk() nounwind {
159; CHECK-LABEL: movn_skip1_movk:
160; CHECK:       // %bb.0:
161; CHECK-NEXT:    mov x0, #-60876
162; CHECK-NEXT:    movk x0, #65494, lsl #32
163; CHECK-NEXT:    ret
164  ret i64 -176093720012
165}
166
167;==--------------------------------------------------------------------------==
168; Tests for ORR with MOVK.
169;==--------------------------------------------------------------------------==
170; rdar://14987673
171
172define i64 @orr_movk1() nounwind {
173; CHECK-LABEL: orr_movk1:
174; CHECK:       // %bb.0:
175; CHECK-NEXT:    mov x0, #72056494543077120
176; CHECK-NEXT:    movk x0, #57005, lsl #16
177; CHECK-NEXT:    ret
178  ret i64 72056498262245120
179}
180
181define i64 @orr_movk2() nounwind {
182; CHECK-LABEL: orr_movk2:
183; CHECK:       // %bb.0:
184; CHECK-NEXT:    mov x0, #72056494543077120
185; CHECK-NEXT:    movk x0, #57005, lsl #48
186; CHECK-NEXT:    ret
187  ret i64 -2400982650836746496
188}
189
190define i64 @orr_movk3() nounwind {
191; CHECK-LABEL: orr_movk3:
192; CHECK:       // %bb.0:
193; CHECK-NEXT:    mov x0, #72056494543077120
194; CHECK-NEXT:    movk x0, #57005, lsl #32
195; CHECK-NEXT:    ret
196  ret i64 72020953688702720
197}
198
199define i64 @orr_movk4() nounwind {
200; CHECK-LABEL: orr_movk4:
201; CHECK:       // %bb.0:
202; CHECK-NEXT:    mov x0, #72056494543077120
203; CHECK-NEXT:    movk x0, #57005
204; CHECK-NEXT:    ret
205  ret i64 72056494543068845
206}
207
208; rdar://14987618
209define i64 @orr_movk5() nounwind {
210; CHECK-LABEL: orr_movk5:
211; CHECK:       // %bb.0:
212; CHECK-NEXT:    mov x0, #-71777214294589696
213; CHECK-NEXT:    movk x0, #57005, lsl #16
214; CHECK-NEXT:    ret
215  ret i64 -71777214836900096
216}
217
218define i64 @orr_movk6() nounwind {
219; CHECK-LABEL: orr_movk6:
220; CHECK:       // %bb.0:
221; CHECK-NEXT:    mov x0, #-71777214294589696
222; CHECK-NEXT:    movk x0, #57005, lsl #16
223; CHECK-NEXT:    movk x0, #57005, lsl #48
224; CHECK-NEXT:    ret
225  ret i64 -2400982647117578496
226}
227
228define i64 @orr_movk7() nounwind {
229; CHECK-LABEL: orr_movk7:
230; CHECK:       // %bb.0:
231; CHECK-NEXT:    mov x0, #-71777214294589696
232; CHECK-NEXT:    movk x0, #57005, lsl #48
233; CHECK-NEXT:    ret
234  ret i64 -2400982646575268096
235}
236
237define i64 @orr_movk8() nounwind {
238; CHECK-LABEL: orr_movk8:
239; CHECK:       // %bb.0:
240; CHECK-NEXT:    mov x0, #-71777214294589696
241; CHECK-NEXT:    movk x0, #57005
242; CHECK-NEXT:    movk x0, #57005, lsl #48
243; CHECK-NEXT:    ret
244  ret i64 -2400982646575276371
245}
246
247; rdar://14987715
248define i64 @orr_movk9() nounwind {
249; CHECK-LABEL: orr_movk9:
250; CHECK:       // %bb.0:
251; CHECK-NEXT:    mov x0, #1152921435887370240
252; CHECK-NEXT:    movk x0, #65280
253; CHECK-NEXT:    movk x0, #57005, lsl #16
254; CHECK-NEXT:    ret
255  ret i64 1152921439623315200
256}
257
258define i64 @orr_movk10() nounwind {
259; CHECK-LABEL: orr_movk10:
260; CHECK:       // %bb.0:
261; CHECK-NEXT:    mov x0, #1152921504606846720
262; CHECK-NEXT:    movk x0, #57005, lsl #16
263; CHECK-NEXT:    ret
264  ret i64 1152921504047824640
265}
266
267define i64 @orr_movk11() nounwind {
268; CHECK-LABEL: orr_movk11:
269; CHECK:       // %bb.0:
270; CHECK-NEXT:    mov x0, #-65281
271; CHECK-NEXT:    movk x0, #57005, lsl #16
272; CHECK-NEXT:    movk x0, #65520, lsl #48
273; CHECK-NEXT:    ret
274  ret i64 -4222125209747201
275}
276
277define i64 @orr_movk12() nounwind {
278; CHECK-LABEL: orr_movk12:
279; CHECK:       // %bb.0:
280; CHECK-NEXT:    mov x0, #-4503599627370241
281; CHECK-NEXT:    movk x0, #57005, lsl #32
282; CHECK-NEXT:    ret
283  ret i64 -4258765016661761
284}
285
286define i64 @orr_movk13() nounwind {
287; CHECK-LABEL: orr_movk13:
288; CHECK:       // %bb.0:
289; CHECK-NEXT:    mov x0, #17592169267200
290; CHECK-NEXT:    movk x0, #57005
291; CHECK-NEXT:    movk x0, #57005, lsl #48
292; CHECK-NEXT:    ret
293  ret i64 -2401245434149282131
294}
295
296; rdar://13944082
297define i64 @g() nounwind {
298; CHECK-LABEL: g:
299; CHECK:       // %bb.0: // %entry
300; CHECK-NEXT:    mov x0, #2
301; CHECK-NEXT:    movk x0, #65535, lsl #48
302; CHECK-NEXT:    ret
303entry:
304  ret i64 -281474976710654
305}
306
307define i64 @orr_movk14() nounwind {
308; CHECK-LABEL: orr_movk14:
309; CHECK:       // %bb.0:
310; CHECK-NEXT:    mov x0, #-549755813888
311; CHECK-NEXT:    movk x0, #2048, lsl #16
312; CHECK-NEXT:    ret
313  ret i64 -549621596160
314}
315
316define i64 @orr_movk15() nounwind {
317; CHECK-LABEL: orr_movk15:
318; CHECK:       // %bb.0:
319; CHECK-NEXT:    mov x0, #549755813887
320; CHECK-NEXT:    movk x0, #63487, lsl #16
321; CHECK-NEXT:    ret
322  ret i64 549621596159
323}
324
325; FIXME: prefer "mov x0, #2147483646; orr x0, x0, #36028659580010496"
326define i64 @orr_movk16() nounwind {
327; CHECK-LABEL: orr_movk16:
328; CHECK:       // %bb.0:
329; CHECK-NEXT:    mov x0, #36028659580010496
330; CHECK-NEXT:    movk x0, #65534
331; CHECK-NEXT:    movk x0, #32767, lsl #16
332; CHECK-NEXT:    ret
333  ret i64 36028661727494142
334}
335
336define i64 @orr_movk17() nounwind {
337; CHECK-LABEL: orr_movk17:
338; CHECK:       // %bb.0:
339; CHECK-NEXT:    mov x0, #-1099511627776
340; CHECK-NEXT:    movk x0, #65280, lsl #16
341; CHECK-NEXT:    ret
342  ret i64 -1095233437696
343}
344
345define i64 @orr_movk18() nounwind {
346; CHECK-LABEL: orr_movk18:
347; CHECK:       // %bb.0:
348; CHECK-NEXT:    mov x0, #137438887936
349; CHECK-NEXT:    movk x0, #65473
350; CHECK-NEXT:    ret
351  ret i64 137438953409
352}
353
354; FIXME: prefer "mov x0, #72340172838076673; and x0, x0, #2199023255296"
355define i64 @orr_and() nounwind {
356; CHECK-LABEL: orr_and:
357; CHECK:       // %bb.0:
358; CHECK-NEXT:    mov x0, #256
359; CHECK-NEXT:    movk x0, #257, lsl #16
360; CHECK-NEXT:    movk x0, #257, lsl #32
361; CHECK-NEXT:    ret
362  ret i64 1103823438080
363}
364
365; FIXME: prefer "mov w0, #-1431655766; movk x0, #9, lsl #32"
366define i64 @movn_movk() nounwind {
367; CHECK-LABEL: movn_movk:
368; CHECK:       // %bb.0:
369; CHECK-NEXT:    mov x0, #43690
370; CHECK-NEXT:    movk x0, #43690, lsl #16
371; CHECK-NEXT:    movk x0, #9, lsl #32
372; CHECK-NEXT:    ret
373  ret i64 41518017194
374}
375
376; FIXME: prefer "mov w0, #-13690; orr x0, x0, #0x1111111111111111"
377define i64 @movn_orr() nounwind {
378; CHECK-LABEL: movn_orr:
379; CHECK:       // %bb.0:
380; CHECK-NEXT:    mov x0, #-51847
381; CHECK-NEXT:    movk x0, #4369, lsl #32
382; CHECK-NEXT:    movk x0, #4369, lsl #48
383; CHECK-NEXT:    ret
384  ret i64 1229782942255887737
385}
386
387; FIXME: prefer "mov w0, #-305397761; eor x0, x0, #0x3333333333333333"
388define i64 @movn_eor() nounwind {
389; CHECK-LABEL: movn_eor:
390; CHECK:       // %bb.0:
391; CHECK-NEXT:    mov x0, #3689348814741910323
392; CHECK-NEXT:    movk x0, #52428
393; CHECK-NEXT:    movk x0, #8455, lsl #16
394; CHECK-NEXT:    ret
395  ret i64 3689348814437076172
396}
397
398; FIXME: prefer "mov x0, #536866816; orr x0, x0, #0x3fff800000000000"
399define i64 @orr_orr_64() nounwind {
400; CHECK-LABEL: orr_orr_64:
401; CHECK:       // %bb.0:
402; CHECK-NEXT:    mov x0, #4611545280939032576
403; CHECK-NEXT:    movk x0, #61440
404; CHECK-NEXT:    movk x0, #8191, lsl #16
405; CHECK-NEXT:    ret
406  ret i64 4611545281475899392
407}
408
409; FIXME: prefer "mov x0, #558551907040256; orr x0, x0, #0x1000100010001000"
410define i64 @orr_orr_32() nounwind {
411; CHECK-LABEL: orr_orr_32:
412; CHECK:       // %bb.0:
413; CHECK-NEXT:    mov x0, #-287953294993589248
414; CHECK-NEXT:    movk x0, #7169, lsl #16
415; CHECK-NEXT:    movk x0, #7169, lsl #48
416; CHECK-NEXT:    ret
417  ret i64 2018171185438784512
418}
419
420; FIXME: prefer "mov x0, #281479271743489; orr x0, x0, #0x1000100010001000"
421define i64 @orr_orr_16() nounwind {
422; CHECK-LABEL: orr_orr_16:
423; CHECK:       // %bb.0:
424; CHECK-NEXT:    mov x0, #4097
425; CHECK-NEXT:    movk x0, #4097, lsl #16
426; CHECK-NEXT:    movk x0, #4097, lsl #32
427; CHECK-NEXT:    movk x0, #4097, lsl #48
428; CHECK-NEXT:    ret
429  ret i64 1153220576333074433
430}
431
432; FIXME: prefer "mov x0, #144680345676153346; orr x0, x0, #0x1818181818181818"
433define i64 @orr_orr_8() nounwind {
434; CHECK-LABEL: orr_orr_8:
435; CHECK:       // %bb.0:
436; CHECK-NEXT:    mov x0, #6682
437; CHECK-NEXT:    movk x0, #6682, lsl #16
438; CHECK-NEXT:    movk x0, #6682, lsl #32
439; CHECK-NEXT:    movk x0, #6682, lsl #48
440; CHECK-NEXT:    ret
441  ret i64 1880844493789993498
442}
443
444; FIXME: prefer "mov x0, #-6148914691236517206; orr x0, x0, #0x0FFFFF0000000000"
445define i64 @orr_64_orr_8() nounwind {
446; CHECK-LABEL: orr_64_orr_8:
447; CHECK:       // %bb.0:
448; CHECK-NEXT:    mov x0, #-6148914691236517206
449; CHECK-NEXT:    movk x0, #65450, lsl #32
450; CHECK-NEXT:    movk x0, #45055, lsl #48
451; CHECK-NEXT:    ret
452  ret i64 -5764607889538110806
453}
454