1; RUN: llc -aarch64-load-store-renaming=true -verify-machineinstrs -mtriple=arm64-linux-gnu -pre-RA-sched=linearize -enable-misched=false -disable-post-ra < %s | FileCheck %s 2 3%va_list = type {i8*, i8*, i8*, i32, i32} 4 5@var = global %va_list zeroinitializer, align 8 6 7declare void @llvm.va_start(i8*) 8 9define void @test_simple(i32 %n, ...) { 10; CHECK-LABEL: test_simple: 11; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]] 12; CHECK: add [[STACK_TOP:x[0-9]+]], sp, #[[STACKSIZE]] 13 14; CHECK: adrp x[[VA_LIST_HI:[0-9]+]], var 15; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, :lo12:var 16 17; CHECK-DAG: stp x6, x7, [sp, # 18; ... omit middle ones ... 19; CHECK-DAG: str x1, [sp, #[[GR_BASE:[0-9]+]]] 20 21; CHECK-DAG: stp q0, q1, [sp] 22; ... omit middle ones ... 23; CHECK-DAG: stp q6, q7, [sp, # 24 25; CHECK: str [[STACK_TOP]], [x[[VA_LIST]]] 26 27; CHECK: add [[GR_TOPTMP:x[0-9]+]], sp, #[[GR_BASE]] 28; CHECK: add [[GR_TOP:x[0-9]+]], [[GR_TOPTMP]], #56 29 30 31; CHECK: mov [[VR_TOPTMP:x[0-9]+]], sp 32; CHECK: add [[VR_TOP:x[0-9]+]], [[VR_TOPTMP]], #128 33; CHECK: stp [[GR_TOP]], [[VR_TOP]], [x[[VA_LIST]], #8] 34 35; CHECK: mov [[GRVR:x[0-9]+]], #-56 36; CHECK: movk [[GRVR]], #65408, lsl #32 37; CHECK: str [[GRVR]], [x[[VA_LIST]], #24] 38 39 %addr = bitcast %va_list* @var to i8* 40 call void @llvm.va_start(i8* %addr) 41 42 ret void 43} 44 45define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) { 46; CHECK-LABEL: test_fewargs: 47; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]] 48; CHECK: add [[STACK_TOP:x[0-9]+]], sp, #[[STACKSIZE]] 49 50; CHECK: adrp x[[VA_LIST_HI:[0-9]+]], var 51; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, :lo12:var 52 53; CHECK-DAG: stp x6, x7, [sp, # 54; ... omit middle ones ... 55; CHECK-DAG: str x3, [sp, #[[GR_BASE:[0-9]+]]] 56 57; CHECK-DAG: stp q6, q7, [sp, #80] 58; ... omit middle ones ... 59; CHECK-DAG: str q1, [sp] 60 61; CHECK: str [[STACK_TOP]], [x[[VA_LIST]]] 62 63; CHECK: add [[GR_TOPTMP:x[0-9]+]], sp, #[[GR_BASE]] 64; CHECK: add [[GR_TOP:x[0-9]+]], [[GR_TOPTMP]], #40 65 66; CHECK: mov [[VR_TOPTMP:x[0-9]+]], sp 67; CHECK: add [[VR_TOP:x[0-9]+]], [[VR_TOPTMP]], #112 68; CHECK: stp [[GR_TOP]], [[VR_TOP]], [x[[VA_LIST]], #8] 69 70; CHECK: mov [[GRVR_OFFS:x[0-9]+]], #-40 71; CHECK: movk [[GRVR_OFFS]], #65424, lsl #32 72; CHECK: str [[GRVR_OFFS]], [x[[VA_LIST]], #24] 73 74 %addr = bitcast %va_list* @var to i8* 75 call void @llvm.va_start(i8* %addr) 76 77 ret void 78} 79 80define void @test_nospare([8 x i64], [8 x float], ...) { 81; CHECK-LABEL: test_nospare: 82 83 %addr = bitcast %va_list* @var to i8* 84 call void @llvm.va_start(i8* %addr) 85; CHECK-NOT: sub sp, sp 86; CHECK: mov [[STACK:x[0-9]+]], sp 87; CHECK: add x[[VAR:[0-9]+]], {{x[0-9]+}}, :lo12:var 88; CHECK: str [[STACK]], [x[[VAR]]] 89 90 ret void 91} 92 93; If there are non-variadic arguments on the stack (here two i64s) then the 94; __stack field should point just past them. 95define void @test_offsetstack([8 x i64], [2 x i64], [3 x float], ...) { 96; CHECK-LABEL: test_offsetstack: 97 98; CHECK-DAG: stp {{q[0-9]+}}, {{q[0-9]+}}, [sp, #48] 99; CHECK-DAG: stp {{q[0-9]+}}, {{q[0-9]+}}, [sp, #16] 100; CHECK-DAG: str {{q[0-9]+}}, [sp] 101; CHECK-DAG: add [[STACK_TOP:x[0-9]+]], sp, #96 102; CHECK-DAG: add x[[VAR:[0-9]+]], {{x[0-9]+}}, :lo12:var 103; CHECK-DAG: str [[STACK_TOP]], [x[[VAR]]] 104 105 %addr = bitcast %va_list* @var to i8* 106 call void @llvm.va_start(i8* %addr) 107 ret void 108} 109 110declare void @llvm.va_end(i8*) 111 112define void @test_va_end() nounwind { 113; CHECK-LABEL: test_va_end: 114; CHECK-NEXT: %bb.0 115 116 %addr = bitcast %va_list* @var to i8* 117 call void @llvm.va_end(i8* %addr) 118 119 ret void 120; CHECK-NEXT: ret 121} 122 123declare void @llvm.va_copy(i8* %dest, i8* %src) 124 125@second_list = global %va_list zeroinitializer 126 127define void @test_va_copy() { 128; CHECK-LABEL: test_va_copy: 129 %srcaddr = bitcast %va_list* @var to i8* 130 %dstaddr = bitcast %va_list* @second_list to i8* 131 call void @llvm.va_copy(i8* %dstaddr, i8* %srcaddr) 132 133; CHECK: add x[[SRC:[0-9]+]], {{x[0-9]+}}, :lo12:var 134 135; CHECK: ldp [[BLOCK:q[0-9]+]], [[BLOCK:q[0-9]+]], [x[[SRC]]] 136; CHECK: add x[[DST:[0-9]+]], {{x[0-9]+}}, :lo12:second_list 137; CHECK: stp [[BLOCK:q[0-9]+]], [[BLOCK:q[0-9]+]], [x[[DST]]] 138 ret void 139; CHECK: ret 140} 141