1; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s
2
3define <8 x i16> @testShiftRightArith_v8i16(<8 x i16> %a, <8 x i16> %b) #0 {
4; CHECK-LABEL: testShiftRightArith_v8i16:
5; CHECK: neg.8h	[[REG1:v[0-9]+]], [[REG1]]
6; CHECK-NEXT: sshl.8h [[REG2:v[0-9]+]], [[REG2]], [[REG1]]
7
8entry:
9  %a.addr = alloca <8 x i16>, align 16
10  %b.addr = alloca <8 x i16>, align 16
11  store <8 x i16> %a, <8 x i16>* %a.addr, align 16
12  store <8 x i16> %b, <8 x i16>* %b.addr, align 16
13  %0 = load <8 x i16>, <8 x i16>* %a.addr, align 16
14  %1 = load <8 x i16>, <8 x i16>* %b.addr, align 16
15  %shr = ashr <8 x i16> %0, %1
16  ret <8 x i16> %shr
17}
18
19define <4 x i32> @testShiftRightArith_v4i32(<4 x i32> %a, <4 x i32> %b) #0 {
20; CHECK-LABEL: testShiftRightArith_v4i32:
21; CHECK: neg.4s	[[REG3:v[0-9]+]], [[REG3]]
22; CHECK-NEXT: sshl.4s [[REG4:v[0-9]+]], [[REG4]], [[REG3]]
23entry:
24  %a.addr = alloca <4 x i32>, align 32
25  %b.addr = alloca <4 x i32>, align 32
26  store <4 x i32> %a, <4 x i32>* %a.addr, align 32
27  store <4 x i32> %b, <4 x i32>* %b.addr, align 32
28  %0 = load <4 x i32>, <4 x i32>* %a.addr, align 32
29  %1 = load <4 x i32>, <4 x i32>* %b.addr, align 32
30  %shr = ashr <4 x i32> %0, %1
31  ret <4 x i32> %shr
32}
33
34define <8 x i16> @testShiftRightLogical(<8 x i16> %a, <8 x i16> %b) #0 {
35; CHECK: testShiftRightLogical
36; CHECK: neg.8h	[[REG5:v[0-9]+]], [[REG5]]
37; CHECK-NEXT: ushl.8h [[REG6:v[0-9]+]], [[REG6]], [[REG5]]
38entry:
39  %a.addr = alloca <8 x i16>, align 16
40  %b.addr = alloca <8 x i16>, align 16
41  store <8 x i16> %a, <8 x i16>* %a.addr, align 16
42  store <8 x i16> %b, <8 x i16>* %b.addr, align 16
43  %0 = load <8 x i16>, <8 x i16>* %a.addr, align 16
44  %1 = load <8 x i16>, <8 x i16>* %b.addr, align 16
45  %shr = lshr <8 x i16> %0, %1
46  ret <8 x i16> %shr
47}
48
49define <1 x i64> @sshr_v1i64(<1 x i64> %A) nounwind {
50; CHECK-LABEL: sshr_v1i64:
51; CHECK: sshr d0, d0, #63
52  %tmp3 = ashr <1 x i64> %A, < i64 63 >
53  ret <1 x i64> %tmp3
54}
55
56define <1 x i64> @ushr_v1i64(<1 x i64> %A) nounwind {
57; CHECK-LABEL: ushr_v1i64:
58; CHECK: ushr d0, d0, #63
59  %tmp3 = lshr <1 x i64> %A, < i64 63 >
60  ret <1 x i64> %tmp3
61}
62
63attributes #0 = { nounwind }
64