1; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
2
3; CHECK-LABEL: fn1_vector:
4; CHECK:      adrp x[[BASE:[0-9]+]], .LCP
5; CHECK-NEXT: ldr q[[NUM:[0-9]+]], [x[[BASE]],
6; CHECK-NEXT: mul v0.16b, v0.16b, v[[NUM]].16b
7; CHECK-NEXT: ret
8define <16 x i8> @fn1_vector(<16 x i8> %arg) {
9entry:
10  %shl = shl <16 x i8> %arg, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
11  %mul = mul <16 x i8> %shl, <i8 0, i8 1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
12  ret <16 x i8> %mul
13}
14
15; CHECK-LABEL: fn2_vector:
16; CHECK:      adrp x[[BASE:[0-9]+]], .LCP
17; CHECK-NEXT: ldr q[[NUM:[0-9]+]], [x[[BASE]],
18; CHECK-NEXT: mul v0.16b, v0.16b, v[[NUM]].16b
19; CHECK-NEXT: ret
20define <16 x i8> @fn2_vector(<16 x i8> %arg) {
21entry:
22  %mul = mul <16 x i8> %arg, <i8 0, i8 1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
23  %shl = shl <16 x i8> %mul, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
24  ret <16 x i8> %shl
25}
26
27; CHECK-LABEL: fn1_vector_undef:
28; CHECK:      adrp x[[BASE:[0-9]+]], .LCP
29; CHECK-NEXT: ldr q[[NUM:[0-9]+]], [x[[BASE]],
30; CHECK-NEXT: mul v0.16b, v0.16b, v[[NUM]].16b
31; CHECK-NEXT: ret
32define <16 x i8> @fn1_vector_undef(<16 x i8> %arg) {
33entry:
34  %shl = shl <16 x i8> %arg, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
35  %mul = mul <16 x i8> %shl, <i8 undef, i8 1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
36  ret <16 x i8> %mul
37}
38
39; CHECK-LABEL: fn2_vector_undef:
40; CHECK:      adrp x[[BASE:[0-9]+]], .LCP
41; CHECK-NEXT: ldr q[[NUM:[0-9]+]], [x[[BASE]],
42; CHECK-NEXT: mul v0.16b, v0.16b, v[[NUM]].16b
43; CHECK-NEXT: ret
44define <16 x i8> @fn2_vector_undef(<16 x i8> %arg) {
45entry:
46  %mul = mul <16 x i8> %arg, <i8 undef, i8 1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
47  %shl = shl <16 x i8> %mul, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
48  ret <16 x i8> %shl
49}
50
51; CHECK-LABEL: fn1_scalar:
52; CHECK:      mov w[[REG:[0-9]+]], #1664
53; CHECK-NEXT: mul w0, w0, w[[REG]]
54; CHECK-NEXT: ret
55define i32 @fn1_scalar(i32 %arg) {
56entry:
57  %shl = shl i32 %arg, 7
58  %mul = mul i32 %shl, 13
59  ret i32 %mul
60}
61
62; CHECK-LABEL: fn2_scalar:
63; CHECK:      mov w[[REG:[0-9]+]], #1664
64; CHECK-NEXT: mul w0, w0, w[[REG]]
65; CHECK-NEXT: ret
66define i32 @fn2_scalar(i32 %arg) {
67entry:
68  %mul = mul i32 %arg, 13
69  %shl = shl i32 %mul, 7
70  ret i32 %shl
71}
72
73; CHECK-LABEL: fn1_scalar_undef:
74; CHECK:      mov w0
75; CHECK-NEXT: ret
76define i32 @fn1_scalar_undef(i32 %arg) {
77entry:
78  %shl = shl i32 %arg, 7
79  %mul = mul i32 %shl, undef
80  ret i32 %mul
81}
82
83; CHECK-LABEL: fn2_scalar_undef:
84; CHECK:      mov w0
85; CHECK-NEXT: ret
86define i32 @fn2_scalar_undef(i32 %arg) {
87entry:
88  %mul = mul i32 %arg, undef
89  %shl = shl i32 %mul, 7
90  ret i32 %shl
91}
92
93; CHECK-LABEL: fn1_scalar_opaque:
94; CHECK:      mov w[[REG:[0-9]+]], #13
95; CHECK-NEXT: mul w[[REG]], w0, w[[REG]]
96; CHECK-NEXT: lsl w0, w[[REG]], #7
97; CHECK-NEXT: ret
98define i32 @fn1_scalar_opaque(i32 %arg) {
99entry:
100  %bitcast = bitcast i32 13 to i32
101  %shl = shl i32 %arg, 7
102  %mul = mul i32 %shl, %bitcast
103  ret i32 %mul
104}
105
106; CHECK-LABEL: fn2_scalar_opaque:
107; CHECK:      mov w[[REG:[0-9]+]], #13
108; CHECK-NEXT: mul w[[REG]], w0, w[[REG]]
109; CHECK-NEXT: lsl w0, w[[REG]], #7
110; CHECK-NEXT: ret
111define i32 @fn2_scalar_opaque(i32 %arg) {
112entry:
113  %bitcast = bitcast i32 13 to i32
114  %mul = mul i32 %arg, %bitcast
115  %shl = shl i32 %mul, 7
116  ret i32 %shl
117}
118