1# RUN: llc -mtriple=aarch64-linux-gnu -mcpu=falkor -run-pass falkor-hwpf-fix-late -o - %s | FileCheck %s 2--- 3# Verify that the tag collision between the loads is resolved for various load opcodes. 4 5# CHECK-LABEL: name: hwpf1 6# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0 7# CHECK: LDRWui $[[BASE]], 0 8# CHECK: LDRWui $x1, 1 9name: hwpf1 10tracksRegLiveness: true 11body: | 12 bb.0: 13 liveins: $w0, $x1 14 15 $w2 = LDRWui $x1, 0 :: ("aarch64-strided-access" load 4) 16 $w2 = LDRWui $x1, 1 17 18 $w0 = SUBWri $w0, 1, 0 19 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv 20 Bcc 9, %bb.0, implicit $nzcv 21 22 bb.1: 23 RET_ReallyLR 24... 25--- 26# CHECK-LABEL: name: hwpf2 27# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0 28# CHECK: LD1i64 $q2, 0, $[[BASE]] 29# CHECK: LDRWui $x1, 0 30name: hwpf2 31tracksRegLiveness: true 32body: | 33 bb.0: 34 liveins: $w0, $x1, $q2 35 36 $q2 = LD1i64 $q2, 0, $x1 :: ("aarch64-strided-access" load 4) 37 $w2 = LDRWui $x1, 0 38 39 $w0 = SUBWri $w0, 1, 0 40 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv 41 Bcc 9, %bb.0, implicit $nzcv 42 43 bb.1: 44 RET_ReallyLR 45... 46--- 47# CHECK-LABEL: name: hwpf3 48# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0 49# CHECK: LD1i8 $q2, 0, $[[BASE]] 50# CHECK: LDRWui $x1, 0 51name: hwpf3 52tracksRegLiveness: true 53body: | 54 bb.0: 55 liveins: $w0, $x1, $q2 56 57 $q2 = LD1i8 $q2, 0, $x1 :: ("aarch64-strided-access" load 4) 58 $w0 = LDRWui $x1, 0 59 60 $w0 = SUBWri $w0, 1, 0 61 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv 62 Bcc 9, %bb.0, implicit $nzcv 63 64 bb.1: 65 RET_ReallyLR 66... 67--- 68# CHECK-LABEL: name: hwpf4 69# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0 70# CHECK: LD1Onev1d $[[BASE]] 71# CHECK: LDRWui $x1, 0 72name: hwpf4 73tracksRegLiveness: true 74body: | 75 bb.0: 76 liveins: $w0, $x1 77 78 $d2 = LD1Onev1d $x1 :: ("aarch64-strided-access" load 4) 79 $w2 = LDRWui $x1, 0 80 81 $w0 = SUBWri $w0, 1, 0 82 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv 83 Bcc 9, %bb.0, implicit $nzcv 84 85 bb.1: 86 RET_ReallyLR 87... 88--- 89# CHECK-LABEL: name: hwpf5 90# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0 91# CHECK: LD1Twov1d $[[BASE]] 92# CHECK: LDRWui $x1, 0 93name: hwpf5 94tracksRegLiveness: true 95body: | 96 bb.0: 97 liveins: $w0, $x1 98 99 $d2_d3 = LD1Twov1d $x1 :: ("aarch64-strided-access" load 4) 100 $w0 = LDRWui $x1, 0 101 102 $w0 = SUBWri $w0, 1, 0 103 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv 104 Bcc 9, %bb.0, implicit $nzcv 105 106 bb.1: 107 RET_ReallyLR 108... 109--- 110# CHECK-LABEL: name: hwpf6 111# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0 112# CHECK: LDPQi $[[BASE]] 113# CHECK: LDRWui $x1, 3 114name: hwpf6 115tracksRegLiveness: true 116body: | 117 bb.0: 118 liveins: $w0, $x1 119 120 $q2, $q3 = LDPQi $x1, 3 :: ("aarch64-strided-access" load 4) 121 $w0 = LDRWui $x1, 3 122 123 $w0 = SUBWri $w0, 1, 0 124 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv 125 Bcc 9, %bb.0, implicit $nzcv 126 127 bb.1: 128 RET_ReallyLR 129... 130--- 131# CHECK-LABEL: name: hwpf7 132# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0 133# CHECK: LDPXi $[[BASE]] 134# CHECK: LDRWui $x1, 2 135name: hwpf7 136tracksRegLiveness: true 137body: | 138 bb.0: 139 liveins: $w0, $x1 140 141 $x2, $x3 = LDPXi $x1, 3 :: ("aarch64-strided-access" load 4) 142 $w2 = LDRWui $x1, 2 143 144 $w0 = SUBWri $w0, 1, 0 145 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv 146 Bcc 9, %bb.0, implicit $nzcv 147 148 bb.1: 149 RET_ReallyLR 150... 151--- 152# Verify that the tag collision between the loads is resolved and written back 153# for post increment addressing for various load opcodes. 154 155# CHECK-LABEL: name: hwpfinc1 156# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0 157# CHECK: LDRWpost $[[BASE]], 0 158# CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0 159# CHECK: LDRWui $x1, 1 160name: hwpfinc1 161tracksRegLiveness: true 162body: | 163 bb.0: 164 liveins: $w0, $x1 165 166 $x1, $w2 = LDRWpost $x1, 0 :: ("aarch64-strided-access" load 4) 167 $w2 = LDRWui $x1, 1 168 169 $w0 = SUBWri $w0, 1, 0 170 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv 171 Bcc 9, %bb.0, implicit $nzcv 172 173 bb.1: 174 RET_ReallyLR 175... 176--- 177# CHECK-LABEL: name: hwpfinc2 178# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0 179# CHECK: LD1i64_POST $q2, 0, $[[BASE]] 180# CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0 181# CHECK: LDRWui $x1, 1 182name: hwpfinc2 183tracksRegLiveness: true 184body: | 185 bb.0: 186 liveins: $w0, $x1, $q2 187 188 $x1, $q2 = LD1i64_POST $q2, 0, $x1, $x1 :: ("aarch64-strided-access" load 4) 189 $w2 = LDRWui $x1, 132 190 191 $w0 = SUBWri $w0, 1, 0 192 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv 193 Bcc 9, %bb.0, implicit $nzcv 194 195 bb.1: 196 RET_ReallyLR 197... 198--- 199# CHECK-LABEL: name: hwpfinc3 200# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0 201# CHECK: LD1i8_POST $q2, 0, $[[BASE]] 202# CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0 203# CHECK: LDRWui $x1, 132 204name: hwpfinc3 205tracksRegLiveness: true 206body: | 207 bb.0: 208 liveins: $w0, $x1, $q2 209 210 $x1, $q2 = LD1i8_POST $q2, 0, $x1, $x1 :: ("aarch64-strided-access" load 4) 211 $w0 = LDRWui $x1, 132 212 213 $w0 = SUBWri $w0, 1, 0 214 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv 215 Bcc 9, %bb.0, implicit $nzcv 216 217 bb.1: 218 RET_ReallyLR 219... 220--- 221# CHECK-LABEL: name: hwpfinc4 222# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0 223# CHECK: LD1Rv1d_POST $[[BASE]] 224# CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0 225# CHECK: LDRWui $x1, 252 226name: hwpfinc4 227tracksRegLiveness: true 228body: | 229 bb.0: 230 liveins: $w0, $x1, $q2 231 232 $x1, $d2 = LD1Rv1d_POST $x1, $xzr :: ("aarch64-strided-access" load 4) 233 $w2 = LDRWui $x1, 252 234 235 $w0 = SUBWri $w0, 1, 0 236 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv 237 Bcc 9, %bb.0, implicit $nzcv 238 239 bb.1: 240 RET_ReallyLR 241... 242--- 243# CHECK-LABEL: name: hwpfinc5 244# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0 245# CHECK: LD3Threev2s_POST $[[BASE]] 246# CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0 247# CHECK: LDRWroX $x17, $x0 248name: hwpfinc5 249tracksRegLiveness: true 250body: | 251 bb.0: 252 liveins: $w0, $x1, $x17, $q2 253 254 $x1, $d2_d3_d4 = LD3Threev2s_POST $x1, $x0 :: ("aarch64-strided-access" load 4) 255 $w0 = LDRWroX $x17, $x0, 0, 0 256 257 $w0 = SUBWri $w0, 1, 0 258 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv 259 Bcc 9, %bb.0, implicit $nzcv 260 261 bb.1: 262 RET_ReallyLR 263... 264--- 265# CHECK-LABEL: name: hwpfinc6 266# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0 267# CHECK: LDPDpost $[[BASE]] 268# CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0 269# CHECK: LDRWui $x17, 2 270name: hwpfinc6 271tracksRegLiveness: true 272body: | 273 bb.0: 274 liveins: $w0, $x1, $x17, $q2 275 276 $x1, $d2, $d3 = LDPDpost $x1, 3 :: ("aarch64-strided-access" load 4) 277 $w16 = LDRWui $x17, 2 278 279 $w0 = SUBWri $w0, 1, 0 280 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv 281 Bcc 9, %bb.0, implicit $nzcv 282 283 bb.1: 284 RET_ReallyLR 285... 286--- 287# CHECK-LABEL: name: hwpfinc7 288# CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0 289# CHECK: LDPXpost $[[BASE]] 290# CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0 291# CHECK: LDRWui $x17, 2 292name: hwpfinc7 293tracksRegLiveness: true 294body: | 295 bb.0: 296 liveins: $w0, $x1, $x17, $q2 297 298 $x1, $x2, $x3 = LDPXpost $x1, 3 :: ("aarch64-strided-access" load 4) 299 $w18 = LDRWui $x17, 2 300 301 $w0 = SUBWri $w0, 1, 0 302 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv 303 Bcc 9, %bb.0, implicit $nzcv 304 305 bb.1: 306 RET_ReallyLR 307... 308--- 309# Check that we handle case of strided load with no HW prefetcher tag correctly. 310 311# CHECK-LABEL: name: hwpf_notagbug 312# CHECK-NOT: ORRXrs $xzr 313# CHECK: LDARW $x1 314# CHECK-NOT: ORRXrs $xzr 315# CHECK: LDRWui $x1 316name: hwpf_notagbug 317tracksRegLiveness: true 318body: | 319 bb.0: 320 liveins: $w0, $x1, $x17 321 322 $w1 = LDARW $x1 :: ("aarch64-strided-access" load 4) 323 $w1 = LDRWui $x1, 0 :: ("aarch64-strided-access" load 4) 324 $w17 = LDRWui $x17, 0 :: ("aarch64-strided-access" load 4) 325 326 $w0 = SUBWri $w0, 1, 0 327 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv 328 Bcc 9, %bb.0, implicit $nzcv 329 330 bb.1: 331 RET_ReallyLR 332... 333--- 334# Check that we treat sp based loads as non-prefetching. 335 336# CHECK-LABEL: name: hwpf_spbase 337# CHECK-NOT: ORRXrs $xzr 338# CHECK: LDRWui $x15 339# CHECK: LDRWui $sp 340name: hwpf_spbase 341tracksRegLiveness: true 342body: | 343 bb.0: 344 liveins: $w0, $x15 345 346 $w1 = LDRWui $x15, 0 :: ("aarch64-strided-access" load 4) 347 $w17 = LDRWui $sp, 0 348 349 $w0 = SUBWri $w0, 1, 0 350 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv 351 Bcc 9, %bb.0, implicit $nzcv 352 353 bb.1: 354 RET_ReallyLR 355... 356--- 357# Check that non-base registers are considered live when finding a 358# scratch register by making sure we don't use $x2 for the scratch 359# register for the inserted ORRXrs. 360# CHECK-LABEL: name: hwpf_offreg 361# CHECK: $x3 = ORRXrs $xzr, $x1, 0 362# CHECK: $w10 = LDRWroX $x3, $x2, 0, 0 363name: hwpf_offreg 364tracksRegLiveness: true 365body: | 366 bb.0: 367 liveins: $w0, $x1, $x2, $x17, $x18 368 369 $w10 = LDRWroX $x1, $x2, 0, 0 :: ("aarch64-strided-access" load 4) 370 371 $x2 = ORRXrs $xzr, $x10, 0 372 $w26 = LDRWroX $x1, $x2, 0, 0 373 374 $w0 = SUBWri $w0, 1, 0 375 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv 376 Bcc 9, %bb.0, implicit $nzcv 377 378 bb.1: 379 RET_ReallyLR 380... 381