1; RUN: llc < %s -mtriple=aarch64-linux-gnuabi -O2 -tail-dup-placement=0 | FileCheck %s
2; -tail-dup-placement causes tail duplication during layout. This breaks the
3; assumptions of the test case as written (specifically, it creates an
4; additional cmp instruction, creating a false positive), so we pass
5; -tail-dup-placement=0 to restore the original behavior
6
7; marked as external to prevent possible optimizations
8@a = external global i32
9@b = external global i32
10@c = external global i32
11@d = external global i32
12@e = external global i32
13
14define void @combine-sign-comparisons-by-cse(i32 *%arg) {
15; CHECK: cmp
16; CHECK: b.ge
17; CHECK-NOT: cmp
18; CHECK: b.le
19
20entry:
21  %a = load i32, i32* @a, align 4
22  %b = load i32, i32* @b, align 4
23  %c = load i32, i32* @c, align 4
24  %d = load i32, i32* @d, align 4
25  %e = load i32, i32* @e, align 4
26
27  %cmp = icmp slt i32 %a, %e
28  br i1 %cmp, label %land.lhs.true, label %lor.lhs.false
29
30land.lhs.true:
31  %cmp1 = icmp eq i32 %b, %c
32  br i1 %cmp1, label %return, label %if.end
33
34lor.lhs.false:
35  %cmp2 = icmp sgt i32 %a, %e
36  br i1 %cmp2, label %land.lhs.true3, label %if.end
37
38land.lhs.true3:
39  %cmp4 = icmp eq i32 %b, %d
40  br i1 %cmp4, label %return, label %if.end
41
42if.end:
43  br label %return
44
45return:
46  %retval.0 = phi i32 [ 0, %if.end ], [ 1, %land.lhs.true3 ], [ 1, %land.lhs.true ]
47  store i32 %a, i32 *%arg
48  ret void
49}
50
51define void @combine_vector_zeros(<8 x i8>* %p, <16 x i8>* %q) {
52; CHECK-LABEL: combine_vector_zeros:
53; CHECK: movi v[[REG:[0-9]+]].2d, #0
54; CHECK-NOT: movi
55; CHECK: str d[[REG]], [x0]
56; CHECK: str q[[REG]], [x1]
57entry:
58  store <8 x i8> zeroinitializer, <8 x i8>* %p
59  store <16 x i8> zeroinitializer, <16 x i8>* %q
60  ret void
61}
62
63define void @combine_vector_ones(<2 x i32>* %p, <4 x i32>* %q) {
64; CHECK-LABEL: combine_vector_ones:
65; CHECK: movi v[[REG:[0-9]+]].2d, #0xffffffffffffffff
66; CHECK-NOT: movi
67; CHECK: str d[[REG]], [x0]
68; CHECK: str q[[REG]], [x1]
69entry:
70  store <2 x i32> <i32 -1, i32 -1>, <2 x i32>* %p
71  store <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32>* %q
72  ret void
73}
74