1; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s 2 3define <8 x i8> @cmeq8xi8(<8 x i8> %A, <8 x i8> %B) { 4; CHECK-LABEL: cmeq8xi8: 5; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 6 %tmp3 = icmp eq <8 x i8> %A, %B; 7 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 8 ret <8 x i8> %tmp4 9} 10 11define <16 x i8> @cmeq16xi8(<16 x i8> %A, <16 x i8> %B) { 12; CHECK-LABEL: cmeq16xi8: 13; CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 14 %tmp3 = icmp eq <16 x i8> %A, %B; 15 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 16 ret <16 x i8> %tmp4 17} 18 19define <4 x i16> @cmeq4xi16(<4 x i16> %A, <4 x i16> %B) { 20; CHECK-LABEL: cmeq4xi16: 21; CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h 22 %tmp3 = icmp eq <4 x i16> %A, %B; 23 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 24 ret <4 x i16> %tmp4 25} 26 27define <8 x i16> @cmeq8xi16(<8 x i16> %A, <8 x i16> %B) { 28; CHECK-LABEL: cmeq8xi16: 29; CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h 30 %tmp3 = icmp eq <8 x i16> %A, %B; 31 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 32 ret <8 x i16> %tmp4 33} 34 35define <2 x i32> @cmeq2xi32(<2 x i32> %A, <2 x i32> %B) { 36; CHECK-LABEL: cmeq2xi32: 37; CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 38 %tmp3 = icmp eq <2 x i32> %A, %B; 39 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 40 ret <2 x i32> %tmp4 41} 42 43define <4 x i32> @cmeq4xi32(<4 x i32> %A, <4 x i32> %B) { 44; CHECK-LABEL: cmeq4xi32: 45; CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s 46 %tmp3 = icmp eq <4 x i32> %A, %B; 47 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 48 ret <4 x i32> %tmp4 49} 50 51define <2 x i64> @cmeq2xi64(<2 x i64> %A, <2 x i64> %B) { 52; CHECK-LABEL: cmeq2xi64: 53; CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 54 %tmp3 = icmp eq <2 x i64> %A, %B; 55 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 56 ret <2 x i64> %tmp4 57} 58 59define <8 x i8> @cmne8xi8(<8 x i8> %A, <8 x i8> %B) { 60; CHECK-LABEL: cmne8xi8: 61; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 62; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 63 %tmp3 = icmp ne <8 x i8> %A, %B; 64 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 65 ret <8 x i8> %tmp4 66} 67 68define <16 x i8> @cmne16xi8(<16 x i8> %A, <16 x i8> %B) { 69; CHECK-LABEL: cmne16xi8: 70; CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 71; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 72 %tmp3 = icmp ne <16 x i8> %A, %B; 73 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 74 ret <16 x i8> %tmp4 75} 76 77define <4 x i16> @cmne4xi16(<4 x i16> %A, <4 x i16> %B) { 78; CHECK-LABEL: cmne4xi16: 79; CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h 80; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 81 %tmp3 = icmp ne <4 x i16> %A, %B; 82 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 83 ret <4 x i16> %tmp4 84} 85 86define <8 x i16> @cmne8xi16(<8 x i16> %A, <8 x i16> %B) { 87; CHECK-LABEL: cmne8xi16: 88; CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h 89; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 90 %tmp3 = icmp ne <8 x i16> %A, %B; 91 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 92 ret <8 x i16> %tmp4 93} 94 95define <2 x i32> @cmne2xi32(<2 x i32> %A, <2 x i32> %B) { 96; CHECK-LABEL: cmne2xi32: 97; CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 98; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 99 %tmp3 = icmp ne <2 x i32> %A, %B; 100 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 101 ret <2 x i32> %tmp4 102} 103 104define <4 x i32> @cmne4xi32(<4 x i32> %A, <4 x i32> %B) { 105; CHECK-LABEL: cmne4xi32: 106; CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s 107; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 108 %tmp3 = icmp ne <4 x i32> %A, %B; 109 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 110 ret <4 x i32> %tmp4 111} 112 113define <2 x i64> @cmne2xi64(<2 x i64> %A, <2 x i64> %B) { 114; CHECK-LABEL: cmne2xi64: 115; CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 116; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 117 %tmp3 = icmp ne <2 x i64> %A, %B; 118 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 119 ret <2 x i64> %tmp4 120} 121 122define <8 x i8> @cmgt8xi8(<8 x i8> %A, <8 x i8> %B) { 123; CHECK-LABEL: cmgt8xi8: 124; CHECK: cmgt {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 125 %tmp3 = icmp sgt <8 x i8> %A, %B; 126 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 127 ret <8 x i8> %tmp4 128} 129 130define <16 x i8> @cmgt16xi8(<16 x i8> %A, <16 x i8> %B) { 131; CHECK-LABEL: cmgt16xi8: 132; CHECK: cmgt {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 133 %tmp3 = icmp sgt <16 x i8> %A, %B; 134 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 135 ret <16 x i8> %tmp4 136} 137 138define <4 x i16> @cmgt4xi16(<4 x i16> %A, <4 x i16> %B) { 139; CHECK-LABEL: cmgt4xi16: 140; CHECK: cmgt {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h 141 %tmp3 = icmp sgt <4 x i16> %A, %B; 142 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 143 ret <4 x i16> %tmp4 144} 145 146define <8 x i16> @cmgt8xi16(<8 x i16> %A, <8 x i16> %B) { 147; CHECK-LABEL: cmgt8xi16: 148; CHECK: cmgt {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h 149 %tmp3 = icmp sgt <8 x i16> %A, %B; 150 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 151 ret <8 x i16> %tmp4 152} 153 154define <2 x i32> @cmgt2xi32(<2 x i32> %A, <2 x i32> %B) { 155; CHECK-LABEL: cmgt2xi32: 156; CHECK: cmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 157 %tmp3 = icmp sgt <2 x i32> %A, %B; 158 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 159 ret <2 x i32> %tmp4 160} 161 162define <4 x i32> @cmgt4xi32(<4 x i32> %A, <4 x i32> %B) { 163; CHECK-LABEL: cmgt4xi32: 164; CHECK: cmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s 165 %tmp3 = icmp sgt <4 x i32> %A, %B; 166 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 167 ret <4 x i32> %tmp4 168} 169 170define <2 x i64> @cmgt2xi64(<2 x i64> %A, <2 x i64> %B) { 171; CHECK-LABEL: cmgt2xi64: 172; CHECK: cmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 173 %tmp3 = icmp sgt <2 x i64> %A, %B; 174 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 175 ret <2 x i64> %tmp4 176} 177 178define <8 x i8> @cmlt8xi8(<8 x i8> %A, <8 x i8> %B) { 179; CHECK-LABEL: cmlt8xi8: 180; Using registers other than v0, v1 are possible, but would be odd. 181; LT implemented as GT, so check reversed operands. 182; CHECK: cmgt {{v[0-9]+}}.8b, v1.8b, v0.8b 183 %tmp3 = icmp slt <8 x i8> %A, %B; 184 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 185 ret <8 x i8> %tmp4 186} 187 188define <16 x i8> @cmlt16xi8(<16 x i8> %A, <16 x i8> %B) { 189; CHECK-LABEL: cmlt16xi8: 190; Using registers other than v0, v1 are possible, but would be odd. 191; LT implemented as GT, so check reversed operands. 192; CHECK: cmgt {{v[0-9]+}}.16b, v1.16b, v0.16b 193 %tmp3 = icmp slt <16 x i8> %A, %B; 194 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 195 ret <16 x i8> %tmp4 196} 197 198define <4 x i16> @cmlt4xi16(<4 x i16> %A, <4 x i16> %B) { 199; CHECK-LABEL: cmlt4xi16: 200; Using registers other than v0, v1 are possible, but would be odd. 201; LT implemented as GT, so check reversed operands. 202; CHECK: cmgt {{v[0-9]+}}.4h, v1.4h, v0.4h 203 %tmp3 = icmp slt <4 x i16> %A, %B; 204 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 205 ret <4 x i16> %tmp4 206} 207 208define <8 x i16> @cmlt8xi16(<8 x i16> %A, <8 x i16> %B) { 209; CHECK-LABEL: cmlt8xi16: 210; Using registers other than v0, v1 are possible, but would be odd. 211; LT implemented as GT, so check reversed operands. 212; CHECK: cmgt {{v[0-9]+}}.8h, v1.8h, v0.8h 213 %tmp3 = icmp slt <8 x i16> %A, %B; 214 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 215 ret <8 x i16> %tmp4 216} 217 218define <2 x i32> @cmlt2xi32(<2 x i32> %A, <2 x i32> %B) { 219; CHECK-LABEL: cmlt2xi32: 220; Using registers other than v0, v1 are possible, but would be odd. 221; LT implemented as GT, so check reversed operands. 222; CHECK: cmgt {{v[0-9]+}}.2s, v1.2s, v0.2s 223 %tmp3 = icmp slt <2 x i32> %A, %B; 224 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 225 ret <2 x i32> %tmp4 226} 227 228define <4 x i32> @cmlt4xi32(<4 x i32> %A, <4 x i32> %B) { 229; CHECK-LABEL: cmlt4xi32: 230; Using registers other than v0, v1 are possible, but would be odd. 231; LT implemented as GT, so check reversed operands. 232; CHECK: cmgt {{v[0-9]+}}.4s, v1.4s, v0.4s 233 %tmp3 = icmp slt <4 x i32> %A, %B; 234 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 235 ret <4 x i32> %tmp4 236} 237 238define <2 x i64> @cmlt2xi64(<2 x i64> %A, <2 x i64> %B) { 239; CHECK-LABEL: cmlt2xi64: 240; Using registers other than v0, v1 are possible, but would be odd. 241; LT implemented as GT, so check reversed operands. 242; CHECK: cmgt {{v[0-9]+}}.2d, v1.2d, v0.2d 243 %tmp3 = icmp slt <2 x i64> %A, %B; 244 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 245 ret <2 x i64> %tmp4 246} 247 248define <8 x i8> @cmge8xi8(<8 x i8> %A, <8 x i8> %B) { 249; CHECK-LABEL: cmge8xi8: 250; CHECK: cmge {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 251 %tmp3 = icmp sge <8 x i8> %A, %B; 252 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 253 ret <8 x i8> %tmp4 254} 255 256define <16 x i8> @cmge16xi8(<16 x i8> %A, <16 x i8> %B) { 257; CHECK-LABEL: cmge16xi8: 258; CHECK: cmge {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 259 %tmp3 = icmp sge <16 x i8> %A, %B; 260 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 261 ret <16 x i8> %tmp4 262} 263 264define <4 x i16> @cmge4xi16(<4 x i16> %A, <4 x i16> %B) { 265; CHECK-LABEL: cmge4xi16: 266; CHECK: cmge {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h 267 %tmp3 = icmp sge <4 x i16> %A, %B; 268 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 269 ret <4 x i16> %tmp4 270} 271 272define <8 x i16> @cmge8xi16(<8 x i16> %A, <8 x i16> %B) { 273; CHECK-LABEL: cmge8xi16: 274; CHECK: cmge {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h 275 %tmp3 = icmp sge <8 x i16> %A, %B; 276 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 277 ret <8 x i16> %tmp4 278} 279 280define <2 x i32> @cmge2xi32(<2 x i32> %A, <2 x i32> %B) { 281; CHECK-LABEL: cmge2xi32: 282; CHECK: cmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 283 %tmp3 = icmp sge <2 x i32> %A, %B; 284 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 285 ret <2 x i32> %tmp4 286} 287 288define <4 x i32> @cmge4xi32(<4 x i32> %A, <4 x i32> %B) { 289; CHECK-LABEL: cmge4xi32: 290; CHECK: cmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s 291 %tmp3 = icmp sge <4 x i32> %A, %B; 292 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 293 ret <4 x i32> %tmp4 294} 295 296define <2 x i64> @cmge2xi64(<2 x i64> %A, <2 x i64> %B) { 297; CHECK-LABEL: cmge2xi64: 298; CHECK: cmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 299 %tmp3 = icmp sge <2 x i64> %A, %B; 300 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 301 ret <2 x i64> %tmp4 302} 303 304define <8 x i8> @cmle8xi8(<8 x i8> %A, <8 x i8> %B) { 305; CHECK-LABEL: cmle8xi8: 306; Using registers other than v0, v1 are possible, but would be odd. 307; LE implemented as GE, so check reversed operands. 308; CHECK: cmge {{v[0-9]+}}.8b, v1.8b, v0.8b 309 %tmp3 = icmp sle <8 x i8> %A, %B; 310 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 311 ret <8 x i8> %tmp4 312} 313 314define <16 x i8> @cmle16xi8(<16 x i8> %A, <16 x i8> %B) { 315; CHECK-LABEL: cmle16xi8: 316; Using registers other than v0, v1 are possible, but would be odd. 317; LE implemented as GE, so check reversed operands. 318; CHECK: cmge {{v[0-9]+}}.16b, v1.16b, v0.16b 319 %tmp3 = icmp sle <16 x i8> %A, %B; 320 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 321 ret <16 x i8> %tmp4 322} 323 324define <4 x i16> @cmle4xi16(<4 x i16> %A, <4 x i16> %B) { 325; CHECK-LABEL: cmle4xi16: 326; Using registers other than v0, v1 are possible, but would be odd. 327; LE implemented as GE, so check reversed operands. 328; CHECK: cmge {{v[0-9]+}}.4h, v1.4h, v0.4h 329 %tmp3 = icmp sle <4 x i16> %A, %B; 330 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 331 ret <4 x i16> %tmp4 332} 333 334define <8 x i16> @cmle8xi16(<8 x i16> %A, <8 x i16> %B) { 335; CHECK-LABEL: cmle8xi16: 336; Using registers other than v0, v1 are possible, but would be odd. 337; LE implemented as GE, so check reversed operands. 338; CHECK: cmge {{v[0-9]+}}.8h, v1.8h, v0.8h 339 %tmp3 = icmp sle <8 x i16> %A, %B; 340 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 341 ret <8 x i16> %tmp4 342} 343 344define <2 x i32> @cmle2xi32(<2 x i32> %A, <2 x i32> %B) { 345; CHECK-LABEL: cmle2xi32: 346; Using registers other than v0, v1 are possible, but would be odd. 347; LE implemented as GE, so check reversed operands. 348; CHECK: cmge {{v[0-9]+}}.2s, v1.2s, v0.2s 349 %tmp3 = icmp sle <2 x i32> %A, %B; 350 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 351 ret <2 x i32> %tmp4 352} 353 354define <4 x i32> @cmle4xi32(<4 x i32> %A, <4 x i32> %B) { 355; CHECK-LABEL: cmle4xi32: 356; Using registers other than v0, v1 are possible, but would be odd. 357; LE implemented as GE, so check reversed operands. 358; CHECK: cmge {{v[0-9]+}}.4s, v1.4s, v0.4s 359 %tmp3 = icmp sle <4 x i32> %A, %B; 360 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 361 ret <4 x i32> %tmp4 362} 363 364define <2 x i64> @cmle2xi64(<2 x i64> %A, <2 x i64> %B) { 365; CHECK-LABEL: cmle2xi64: 366; Using registers other than v0, v1 are possible, but would be odd. 367; LE implemented as GE, so check reversed operands. 368; CHECK: cmge {{v[0-9]+}}.2d, v1.2d, v0.2d 369 %tmp3 = icmp sle <2 x i64> %A, %B; 370 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 371 ret <2 x i64> %tmp4 372} 373 374define <8 x i8> @cmhi8xi8(<8 x i8> %A, <8 x i8> %B) { 375; CHECK-LABEL: cmhi8xi8: 376; CHECK: cmhi {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 377 %tmp3 = icmp ugt <8 x i8> %A, %B; 378 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 379 ret <8 x i8> %tmp4 380} 381 382define <16 x i8> @cmhi16xi8(<16 x i8> %A, <16 x i8> %B) { 383; CHECK-LABEL: cmhi16xi8: 384; CHECK: cmhi {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 385 %tmp3 = icmp ugt <16 x i8> %A, %B; 386 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 387 ret <16 x i8> %tmp4 388} 389 390define <4 x i16> @cmhi4xi16(<4 x i16> %A, <4 x i16> %B) { 391; CHECK-LABEL: cmhi4xi16: 392; CHECK: cmhi {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h 393 %tmp3 = icmp ugt <4 x i16> %A, %B; 394 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 395 ret <4 x i16> %tmp4 396} 397 398define <8 x i16> @cmhi8xi16(<8 x i16> %A, <8 x i16> %B) { 399; CHECK-LABEL: cmhi8xi16: 400; CHECK: cmhi {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h 401 %tmp3 = icmp ugt <8 x i16> %A, %B; 402 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 403 ret <8 x i16> %tmp4 404} 405 406define <2 x i32> @cmhi2xi32(<2 x i32> %A, <2 x i32> %B) { 407; CHECK-LABEL: cmhi2xi32: 408; CHECK: cmhi {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 409 %tmp3 = icmp ugt <2 x i32> %A, %B; 410 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 411 ret <2 x i32> %tmp4 412} 413 414define <4 x i32> @cmhi4xi32(<4 x i32> %A, <4 x i32> %B) { 415; CHECK-LABEL: cmhi4xi32: 416; CHECK: cmhi {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s 417 %tmp3 = icmp ugt <4 x i32> %A, %B; 418 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 419 ret <4 x i32> %tmp4 420} 421 422define <2 x i64> @cmhi2xi64(<2 x i64> %A, <2 x i64> %B) { 423; CHECK-LABEL: cmhi2xi64: 424; CHECK: cmhi {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 425 %tmp3 = icmp ugt <2 x i64> %A, %B; 426 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 427 ret <2 x i64> %tmp4 428} 429 430define <8 x i8> @cmlo8xi8(<8 x i8> %A, <8 x i8> %B) { 431; CHECK-LABEL: cmlo8xi8: 432; Using registers other than v0, v1 are possible, but would be odd. 433; LO implemented as HI, so check reversed operands. 434; CHECK: cmhi {{v[0-9]+}}.8b, v1.8b, v0.8b 435 %tmp3 = icmp ult <8 x i8> %A, %B; 436 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 437 ret <8 x i8> %tmp4 438} 439 440define <16 x i8> @cmlo16xi8(<16 x i8> %A, <16 x i8> %B) { 441; CHECK-LABEL: cmlo16xi8: 442; Using registers other than v0, v1 are possible, but would be odd. 443; LO implemented as HI, so check reversed operands. 444; CHECK: cmhi {{v[0-9]+}}.16b, v1.16b, v0.16b 445 %tmp3 = icmp ult <16 x i8> %A, %B; 446 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 447 ret <16 x i8> %tmp4 448} 449 450define <4 x i16> @cmlo4xi16(<4 x i16> %A, <4 x i16> %B) { 451; CHECK-LABEL: cmlo4xi16: 452; Using registers other than v0, v1 are possible, but would be odd. 453; LO implemented as HI, so check reversed operands. 454; CHECK: cmhi {{v[0-9]+}}.4h, v1.4h, v0.4h 455 %tmp3 = icmp ult <4 x i16> %A, %B; 456 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 457 ret <4 x i16> %tmp4 458} 459 460define <8 x i16> @cmlo8xi16(<8 x i16> %A, <8 x i16> %B) { 461; CHECK-LABEL: cmlo8xi16: 462; Using registers other than v0, v1 are possible, but would be odd. 463; LO implemented as HI, so check reversed operands. 464; CHECK: cmhi {{v[0-9]+}}.8h, v1.8h, v0.8h 465 %tmp3 = icmp ult <8 x i16> %A, %B; 466 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 467 ret <8 x i16> %tmp4 468} 469 470define <2 x i32> @cmlo2xi32(<2 x i32> %A, <2 x i32> %B) { 471; CHECK-LABEL: cmlo2xi32: 472; Using registers other than v0, v1 are possible, but would be odd. 473; LO implemented as HI, so check reversed operands. 474; CHECK: cmhi {{v[0-9]+}}.2s, v1.2s, v0.2s 475 %tmp3 = icmp ult <2 x i32> %A, %B; 476 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 477 ret <2 x i32> %tmp4 478} 479 480define <4 x i32> @cmlo4xi32(<4 x i32> %A, <4 x i32> %B) { 481; CHECK-LABEL: cmlo4xi32: 482; Using registers other than v0, v1 are possible, but would be odd. 483; LO implemented as HI, so check reversed operands. 484; CHECK: cmhi {{v[0-9]+}}.4s, v1.4s, v0.4s 485 %tmp3 = icmp ult <4 x i32> %A, %B; 486 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 487 ret <4 x i32> %tmp4 488} 489 490define <2 x i64> @cmlo2xi64(<2 x i64> %A, <2 x i64> %B) { 491; CHECK-LABEL: cmlo2xi64: 492; Using registers other than v0, v1 are possible, but would be odd. 493; LO implemented as HI, so check reversed operands. 494; CHECK: cmhi {{v[0-9]+}}.2d, v1.2d, v0.2d 495 %tmp3 = icmp ult <2 x i64> %A, %B; 496 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 497 ret <2 x i64> %tmp4 498} 499 500define <8 x i8> @cmhs8xi8(<8 x i8> %A, <8 x i8> %B) { 501; CHECK-LABEL: cmhs8xi8: 502; CHECK: cmhs {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 503 %tmp3 = icmp uge <8 x i8> %A, %B; 504 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 505 ret <8 x i8> %tmp4 506} 507 508define <16 x i8> @cmhs16xi8(<16 x i8> %A, <16 x i8> %B) { 509; CHECK-LABEL: cmhs16xi8: 510; CHECK: cmhs {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 511 %tmp3 = icmp uge <16 x i8> %A, %B; 512 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 513 ret <16 x i8> %tmp4 514} 515 516define <4 x i16> @cmhs4xi16(<4 x i16> %A, <4 x i16> %B) { 517; CHECK-LABEL: cmhs4xi16: 518; CHECK: cmhs {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h 519 %tmp3 = icmp uge <4 x i16> %A, %B; 520 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 521 ret <4 x i16> %tmp4 522} 523 524define <8 x i16> @cmhs8xi16(<8 x i16> %A, <8 x i16> %B) { 525; CHECK-LABEL: cmhs8xi16: 526; CHECK: cmhs {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h 527 %tmp3 = icmp uge <8 x i16> %A, %B; 528 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 529 ret <8 x i16> %tmp4 530} 531 532define <2 x i32> @cmhs2xi32(<2 x i32> %A, <2 x i32> %B) { 533; CHECK-LABEL: cmhs2xi32: 534; CHECK: cmhs {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 535 %tmp3 = icmp uge <2 x i32> %A, %B; 536 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 537 ret <2 x i32> %tmp4 538} 539 540define <4 x i32> @cmhs4xi32(<4 x i32> %A, <4 x i32> %B) { 541; CHECK-LABEL: cmhs4xi32: 542; CHECK: cmhs {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s 543 %tmp3 = icmp uge <4 x i32> %A, %B; 544 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 545 ret <4 x i32> %tmp4 546} 547 548define <2 x i64> @cmhs2xi64(<2 x i64> %A, <2 x i64> %B) { 549; CHECK-LABEL: cmhs2xi64: 550; CHECK: cmhs {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 551 %tmp3 = icmp uge <2 x i64> %A, %B; 552 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 553 ret <2 x i64> %tmp4 554} 555 556define <8 x i8> @cmls8xi8(<8 x i8> %A, <8 x i8> %B) { 557; CHECK-LABEL: cmls8xi8: 558; Using registers other than v0, v1 are possible, but would be odd. 559; LS implemented as HS, so check reversed operands. 560; CHECK: cmhs {{v[0-9]+}}.8b, v1.8b, v0.8b 561 %tmp3 = icmp ule <8 x i8> %A, %B; 562 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 563 ret <8 x i8> %tmp4 564} 565 566define <16 x i8> @cmls16xi8(<16 x i8> %A, <16 x i8> %B) { 567; CHECK-LABEL: cmls16xi8: 568; Using registers other than v0, v1 are possible, but would be odd. 569; LS implemented as HS, so check reversed operands. 570; CHECK: cmhs {{v[0-9]+}}.16b, v1.16b, v0.16b 571 %tmp3 = icmp ule <16 x i8> %A, %B; 572 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 573 ret <16 x i8> %tmp4 574} 575 576define <4 x i16> @cmls4xi16(<4 x i16> %A, <4 x i16> %B) { 577; CHECK-LABEL: cmls4xi16: 578; Using registers other than v0, v1 are possible, but would be odd. 579; LS implemented as HS, so check reversed operands. 580; CHECK: cmhs {{v[0-9]+}}.4h, v1.4h, v0.4h 581 %tmp3 = icmp ule <4 x i16> %A, %B; 582 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 583 ret <4 x i16> %tmp4 584} 585 586define <8 x i16> @cmls8xi16(<8 x i16> %A, <8 x i16> %B) { 587; CHECK-LABEL: cmls8xi16: 588; Using registers other than v0, v1 are possible, but would be odd. 589; LS implemented as HS, so check reversed operands. 590; CHECK: cmhs {{v[0-9]+}}.8h, v1.8h, v0.8h 591 %tmp3 = icmp ule <8 x i16> %A, %B; 592 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 593 ret <8 x i16> %tmp4 594} 595 596define <2 x i32> @cmls2xi32(<2 x i32> %A, <2 x i32> %B) { 597; CHECK-LABEL: cmls2xi32: 598; Using registers other than v0, v1 are possible, but would be odd. 599; LS implemented as HS, so check reversed operands. 600; CHECK: cmhs {{v[0-9]+}}.2s, v1.2s, v0.2s 601 %tmp3 = icmp ule <2 x i32> %A, %B; 602 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 603 ret <2 x i32> %tmp4 604} 605 606define <4 x i32> @cmls4xi32(<4 x i32> %A, <4 x i32> %B) { 607; CHECK-LABEL: cmls4xi32: 608; Using registers other than v0, v1 are possible, but would be odd. 609; LS implemented as HS, so check reversed operands. 610; CHECK: cmhs {{v[0-9]+}}.4s, v1.4s, v0.4s 611 %tmp3 = icmp ule <4 x i32> %A, %B; 612 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 613 ret <4 x i32> %tmp4 614} 615 616define <2 x i64> @cmls2xi64(<2 x i64> %A, <2 x i64> %B) { 617; CHECK-LABEL: cmls2xi64: 618; Using registers other than v0, v1 are possible, but would be odd. 619; LS implemented as HS, so check reversed operands. 620; CHECK: cmhs {{v[0-9]+}}.2d, v1.2d, v0.2d 621 %tmp3 = icmp ule <2 x i64> %A, %B; 622 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 623 ret <2 x i64> %tmp4 624} 625 626define <8 x i8> @cmtst8xi8(<8 x i8> %A, <8 x i8> %B) { 627; CHECK-LABEL: cmtst8xi8: 628; CHECK: cmtst {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 629 %tmp3 = and <8 x i8> %A, %B 630 %tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer 631 %tmp5 = sext <8 x i1> %tmp4 to <8 x i8> 632 ret <8 x i8> %tmp5 633} 634 635define <16 x i8> @cmtst16xi8(<16 x i8> %A, <16 x i8> %B) { 636; CHECK-LABEL: cmtst16xi8: 637; CHECK: cmtst {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 638 %tmp3 = and <16 x i8> %A, %B 639 %tmp4 = icmp ne <16 x i8> %tmp3, zeroinitializer 640 %tmp5 = sext <16 x i1> %tmp4 to <16 x i8> 641 ret <16 x i8> %tmp5 642} 643 644define <4 x i16> @cmtst4xi16(<4 x i16> %A, <4 x i16> %B) { 645; CHECK-LABEL: cmtst4xi16: 646; CHECK: cmtst {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h 647 %tmp3 = and <4 x i16> %A, %B 648 %tmp4 = icmp ne <4 x i16> %tmp3, zeroinitializer 649 %tmp5 = sext <4 x i1> %tmp4 to <4 x i16> 650 ret <4 x i16> %tmp5 651} 652 653define <8 x i16> @cmtst8xi16(<8 x i16> %A, <8 x i16> %B) { 654; CHECK-LABEL: cmtst8xi16: 655; CHECK: cmtst {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h 656 %tmp3 = and <8 x i16> %A, %B 657 %tmp4 = icmp ne <8 x i16> %tmp3, zeroinitializer 658 %tmp5 = sext <8 x i1> %tmp4 to <8 x i16> 659 ret <8 x i16> %tmp5 660} 661 662define <2 x i32> @cmtst2xi32(<2 x i32> %A, <2 x i32> %B) { 663; CHECK-LABEL: cmtst2xi32: 664; CHECK: cmtst {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 665 %tmp3 = and <2 x i32> %A, %B 666 %tmp4 = icmp ne <2 x i32> %tmp3, zeroinitializer 667 %tmp5 = sext <2 x i1> %tmp4 to <2 x i32> 668 ret <2 x i32> %tmp5 669} 670 671define <4 x i32> @cmtst4xi32(<4 x i32> %A, <4 x i32> %B) { 672; CHECK-LABEL: cmtst4xi32: 673; CHECK: cmtst {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s 674 %tmp3 = and <4 x i32> %A, %B 675 %tmp4 = icmp ne <4 x i32> %tmp3, zeroinitializer 676 %tmp5 = sext <4 x i1> %tmp4 to <4 x i32> 677 ret <4 x i32> %tmp5 678} 679 680define <2 x i64> @cmtst2xi64(<2 x i64> %A, <2 x i64> %B) { 681; CHECK-LABEL: cmtst2xi64: 682; CHECK: cmtst {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 683 %tmp3 = and <2 x i64> %A, %B 684 %tmp4 = icmp ne <2 x i64> %tmp3, zeroinitializer 685 %tmp5 = sext <2 x i1> %tmp4 to <2 x i64> 686 ret <2 x i64> %tmp5 687} 688 689 690 691define <8 x i8> @cmeqz8xi8(<8 x i8> %A) { 692; CHECK-LABEL: cmeqz8xi8: 693; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}} 694 %tmp3 = icmp eq <8 x i8> %A, zeroinitializer; 695 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 696 ret <8 x i8> %tmp4 697} 698 699define <16 x i8> @cmeqz16xi8(<16 x i8> %A) { 700; CHECK-LABEL: cmeqz16xi8: 701; CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}} 702 %tmp3 = icmp eq <16 x i8> %A, zeroinitializer; 703 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 704 ret <16 x i8> %tmp4 705} 706 707define <4 x i16> @cmeqz4xi16(<4 x i16> %A) { 708; CHECK-LABEL: cmeqz4xi16: 709; CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}} 710 %tmp3 = icmp eq <4 x i16> %A, zeroinitializer; 711 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 712 ret <4 x i16> %tmp4 713} 714 715define <8 x i16> @cmeqz8xi16(<8 x i16> %A) { 716; CHECK-LABEL: cmeqz8xi16: 717; CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}} 718 %tmp3 = icmp eq <8 x i16> %A, zeroinitializer; 719 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 720 ret <8 x i16> %tmp4 721} 722 723define <2 x i32> @cmeqz2xi32(<2 x i32> %A) { 724; CHECK-LABEL: cmeqz2xi32: 725; CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}} 726 %tmp3 = icmp eq <2 x i32> %A, zeroinitializer; 727 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 728 ret <2 x i32> %tmp4 729} 730 731define <4 x i32> @cmeqz4xi32(<4 x i32> %A) { 732; CHECK-LABEL: cmeqz4xi32: 733; CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}} 734 %tmp3 = icmp eq <4 x i32> %A, zeroinitializer; 735 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 736 ret <4 x i32> %tmp4 737} 738 739define <2 x i64> @cmeqz2xi64(<2 x i64> %A) { 740; CHECK-LABEL: cmeqz2xi64: 741; CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}} 742 %tmp3 = icmp eq <2 x i64> %A, zeroinitializer; 743 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 744 ret <2 x i64> %tmp4 745} 746 747 748define <8 x i8> @cmgez8xi8(<8 x i8> %A) { 749; CHECK-LABEL: cmgez8xi8: 750; CHECK: cmge {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}} 751 %tmp3 = icmp sge <8 x i8> %A, zeroinitializer; 752 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 753 ret <8 x i8> %tmp4 754} 755 756define <16 x i8> @cmgez16xi8(<16 x i8> %A) { 757; CHECK-LABEL: cmgez16xi8: 758; CHECK: cmge {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}} 759 %tmp3 = icmp sge <16 x i8> %A, zeroinitializer; 760 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 761 ret <16 x i8> %tmp4 762} 763 764define <4 x i16> @cmgez4xi16(<4 x i16> %A) { 765; CHECK-LABEL: cmgez4xi16: 766; CHECK: cmge {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}} 767 %tmp3 = icmp sge <4 x i16> %A, zeroinitializer; 768 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 769 ret <4 x i16> %tmp4 770} 771 772define <8 x i16> @cmgez8xi16(<8 x i16> %A) { 773; CHECK-LABEL: cmgez8xi16: 774; CHECK: cmge {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}} 775 %tmp3 = icmp sge <8 x i16> %A, zeroinitializer; 776 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 777 ret <8 x i16> %tmp4 778} 779 780define <2 x i32> @cmgez2xi32(<2 x i32> %A) { 781; CHECK-LABEL: cmgez2xi32: 782; CHECK: cmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}} 783 %tmp3 = icmp sge <2 x i32> %A, zeroinitializer; 784 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 785 ret <2 x i32> %tmp4 786} 787 788define <4 x i32> @cmgez4xi32(<4 x i32> %A) { 789; CHECK-LABEL: cmgez4xi32: 790; CHECK: cmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}} 791 %tmp3 = icmp sge <4 x i32> %A, zeroinitializer; 792 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 793 ret <4 x i32> %tmp4 794} 795 796define <2 x i64> @cmgez2xi64(<2 x i64> %A) { 797; CHECK-LABEL: cmgez2xi64: 798; CHECK: cmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}} 799 %tmp3 = icmp sge <2 x i64> %A, zeroinitializer; 800 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 801 ret <2 x i64> %tmp4 802} 803 804 805define <8 x i8> @cmgez8xi8_alt(<8 x i8> %A) { 806; CHECK-LABEL: cmgez8xi8_alt: 807; CHECK: cmge {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}} 808 %sign = ashr <8 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> 809 %not = xor <8 x i8> %sign, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 810 ret <8 x i8> %not 811} 812 813define <16 x i8> @cmgez16xi8_alt(<16 x i8> %A) { 814; CHECK-LABEL: cmgez16xi8_alt: 815; CHECK: cmge {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}} 816 %sign = ashr <16 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> 817 %not = xor <16 x i8> %sign, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 818 ret <16 x i8> %not 819} 820 821define <4 x i16> @cmgez4xi16_alt(<4 x i16> %A) { 822; CHECK-LABEL: cmgez4xi16_alt: 823; CHECK: cmge {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}} 824 %sign = ashr <4 x i16> %A, <i16 15, i16 15, i16 15, i16 15> 825 %not = xor <4 x i16> %sign, <i16 -1, i16 -1, i16 -1, i16 -1> 826 ret <4 x i16> %not 827} 828 829define <8 x i16> @cmgez8xi16_alt(<8 x i16> %A) { 830; CHECK-LABEL: cmgez8xi16_alt: 831; CHECK: cmge {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}} 832 %sign = ashr <8 x i16> %A, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> 833 %not = xor <8 x i16> %sign, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> 834 ret <8 x i16> %not 835} 836 837define <2 x i32> @cmgez2xi32_alt(<2 x i32> %A) { 838; CHECK-LABEL: cmgez2xi32_alt: 839; CHECK: cmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}} 840 %sign = ashr <2 x i32> %A, <i32 31, i32 31> 841 %not = xor <2 x i32> %sign, <i32 -1, i32 -1> 842 ret <2 x i32> %not 843} 844 845define <4 x i32> @cmgez4xi32_alt(<4 x i32> %A) { 846; CHECK-LABEL: cmgez4xi32_alt: 847; CHECK: cmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}} 848 %sign = ashr <4 x i32> %A, <i32 31, i32 31, i32 31, i32 31> 849 %not = xor <4 x i32> %sign, <i32 -1, i32 -1, i32 -1, i32 -1> 850 ret <4 x i32> %not 851} 852 853define <2 x i64> @cmgez2xi64_alt(<2 x i64> %A) { 854; CHECK-LABEL: cmgez2xi64_alt: 855; CHECK: cmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}} 856 %sign = ashr <2 x i64> %A, <i64 63, i64 63> 857 %not = xor <2 x i64> %sign, <i64 -1, i64 -1> 858 ret <2 x i64> %not 859} 860 861 862define <8 x i8> @cmgtz8xi8(<8 x i8> %A) { 863; CHECK-LABEL: cmgtz8xi8: 864; CHECK: cmgt {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}} 865 %tmp3 = icmp sgt <8 x i8> %A, zeroinitializer; 866 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 867 ret <8 x i8> %tmp4 868} 869 870define <16 x i8> @cmgtz16xi8(<16 x i8> %A) { 871; CHECK-LABEL: cmgtz16xi8: 872; CHECK: cmgt {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}} 873 %tmp3 = icmp sgt <16 x i8> %A, zeroinitializer; 874 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 875 ret <16 x i8> %tmp4 876} 877 878define <4 x i16> @cmgtz4xi16(<4 x i16> %A) { 879; CHECK-LABEL: cmgtz4xi16: 880; CHECK: cmgt {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}} 881 %tmp3 = icmp sgt <4 x i16> %A, zeroinitializer; 882 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 883 ret <4 x i16> %tmp4 884} 885 886define <8 x i16> @cmgtz8xi16(<8 x i16> %A) { 887; CHECK-LABEL: cmgtz8xi16: 888; CHECK: cmgt {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}} 889 %tmp3 = icmp sgt <8 x i16> %A, zeroinitializer; 890 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 891 ret <8 x i16> %tmp4 892} 893 894define <2 x i32> @cmgtz2xi32(<2 x i32> %A) { 895; CHECK-LABEL: cmgtz2xi32: 896; CHECK: cmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}} 897 %tmp3 = icmp sgt <2 x i32> %A, zeroinitializer; 898 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 899 ret <2 x i32> %tmp4 900} 901 902define <4 x i32> @cmgtz4xi32(<4 x i32> %A) { 903; CHECK-LABEL: cmgtz4xi32: 904; CHECK: cmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}} 905 %tmp3 = icmp sgt <4 x i32> %A, zeroinitializer; 906 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 907 ret <4 x i32> %tmp4 908} 909 910define <2 x i64> @cmgtz2xi64(<2 x i64> %A) { 911; CHECK-LABEL: cmgtz2xi64: 912; CHECK: cmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}} 913 %tmp3 = icmp sgt <2 x i64> %A, zeroinitializer; 914 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 915 ret <2 x i64> %tmp4 916} 917 918define <8 x i8> @cmlez8xi8(<8 x i8> %A) { 919; CHECK-LABEL: cmlez8xi8: 920; CHECK: cmle {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}} 921 %tmp3 = icmp sle <8 x i8> %A, zeroinitializer; 922 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 923 ret <8 x i8> %tmp4 924} 925 926define <16 x i8> @cmlez16xi8(<16 x i8> %A) { 927; CHECK-LABEL: cmlez16xi8: 928; CHECK: cmle {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}} 929 %tmp3 = icmp sle <16 x i8> %A, zeroinitializer; 930 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 931 ret <16 x i8> %tmp4 932} 933 934define <4 x i16> @cmlez4xi16(<4 x i16> %A) { 935; CHECK-LABEL: cmlez4xi16: 936; CHECK: cmle {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}} 937 %tmp3 = icmp sle <4 x i16> %A, zeroinitializer; 938 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 939 ret <4 x i16> %tmp4 940} 941 942define <8 x i16> @cmlez8xi16(<8 x i16> %A) { 943; CHECK-LABEL: cmlez8xi16: 944; CHECK: cmle {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}} 945 %tmp3 = icmp sle <8 x i16> %A, zeroinitializer; 946 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 947 ret <8 x i16> %tmp4 948} 949 950define <2 x i32> @cmlez2xi32(<2 x i32> %A) { 951; CHECK-LABEL: cmlez2xi32: 952; CHECK: cmle {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}} 953 %tmp3 = icmp sle <2 x i32> %A, zeroinitializer; 954 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 955 ret <2 x i32> %tmp4 956} 957 958define <4 x i32> @cmlez4xi32(<4 x i32> %A) { 959; CHECK-LABEL: cmlez4xi32: 960; CHECK: cmle {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}} 961 %tmp3 = icmp sle <4 x i32> %A, zeroinitializer; 962 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 963 ret <4 x i32> %tmp4 964} 965 966define <2 x i64> @cmlez2xi64(<2 x i64> %A) { 967; CHECK-LABEL: cmlez2xi64: 968; CHECK: cmle {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}} 969 %tmp3 = icmp sle <2 x i64> %A, zeroinitializer; 970 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 971 ret <2 x i64> %tmp4 972} 973 974define <8 x i8> @cmltz8xi8(<8 x i8> %A) { 975; CHECK-LABEL: cmltz8xi8: 976; CHECK: cmlt {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}} 977 %tmp3 = icmp slt <8 x i8> %A, zeroinitializer; 978 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 979 ret <8 x i8> %tmp4 980} 981 982define <16 x i8> @cmltz16xi8(<16 x i8> %A) { 983; CHECK-LABEL: cmltz16xi8: 984; CHECK: cmlt {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}} 985 %tmp3 = icmp slt <16 x i8> %A, zeroinitializer; 986 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 987 ret <16 x i8> %tmp4 988} 989 990define <4 x i16> @cmltz4xi16(<4 x i16> %A) { 991; CHECK-LABEL: cmltz4xi16: 992; CHECK: cmlt {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}} 993 %tmp3 = icmp slt <4 x i16> %A, zeroinitializer; 994 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 995 ret <4 x i16> %tmp4 996} 997 998define <8 x i16> @cmltz8xi16(<8 x i16> %A) { 999; CHECK-LABEL: cmltz8xi16: 1000; CHECK: cmlt {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}} 1001 %tmp3 = icmp slt <8 x i16> %A, zeroinitializer; 1002 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 1003 ret <8 x i16> %tmp4 1004} 1005 1006define <2 x i32> @cmltz2xi32(<2 x i32> %A) { 1007; CHECK-LABEL: cmltz2xi32: 1008; CHECK: cmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}} 1009 %tmp3 = icmp slt <2 x i32> %A, zeroinitializer; 1010 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1011 ret <2 x i32> %tmp4 1012} 1013 1014define <4 x i32> @cmltz4xi32(<4 x i32> %A) { 1015; CHECK-LABEL: cmltz4xi32: 1016; CHECK: cmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}} 1017 %tmp3 = icmp slt <4 x i32> %A, zeroinitializer; 1018 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1019 ret <4 x i32> %tmp4 1020} 1021 1022define <2 x i64> @cmltz2xi64(<2 x i64> %A) { 1023; CHECK-LABEL: cmltz2xi64: 1024; CHECK: cmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}} 1025 %tmp3 = icmp slt <2 x i64> %A, zeroinitializer; 1026 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1027 ret <2 x i64> %tmp4 1028} 1029 1030define <8 x i8> @cmneqz8xi8(<8 x i8> %A) { 1031; CHECK-LABEL: cmneqz8xi8: 1032; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}} 1033; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1034 %tmp3 = icmp ne <8 x i8> %A, zeroinitializer; 1035 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 1036 ret <8 x i8> %tmp4 1037} 1038 1039define <16 x i8> @cmneqz16xi8(<16 x i8> %A) { 1040; CHECK-LABEL: cmneqz16xi8: 1041; CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}} 1042; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1043 %tmp3 = icmp ne <16 x i8> %A, zeroinitializer; 1044 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 1045 ret <16 x i8> %tmp4 1046} 1047 1048define <4 x i16> @cmneqz4xi16(<4 x i16> %A) { 1049; CHECK-LABEL: cmneqz4xi16: 1050; CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}} 1051; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1052 %tmp3 = icmp ne <4 x i16> %A, zeroinitializer; 1053 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 1054 ret <4 x i16> %tmp4 1055} 1056 1057define <8 x i16> @cmneqz8xi16(<8 x i16> %A) { 1058; CHECK-LABEL: cmneqz8xi16: 1059; CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}} 1060; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1061 %tmp3 = icmp ne <8 x i16> %A, zeroinitializer; 1062 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 1063 ret <8 x i16> %tmp4 1064} 1065 1066define <2 x i32> @cmneqz2xi32(<2 x i32> %A) { 1067; CHECK-LABEL: cmneqz2xi32: 1068; CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}} 1069; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1070 %tmp3 = icmp ne <2 x i32> %A, zeroinitializer; 1071 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1072 ret <2 x i32> %tmp4 1073} 1074 1075define <4 x i32> @cmneqz4xi32(<4 x i32> %A) { 1076; CHECK-LABEL: cmneqz4xi32: 1077; CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}} 1078; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1079 %tmp3 = icmp ne <4 x i32> %A, zeroinitializer; 1080 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1081 ret <4 x i32> %tmp4 1082} 1083 1084define <2 x i64> @cmneqz2xi64(<2 x i64> %A) { 1085; CHECK-LABEL: cmneqz2xi64: 1086; CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}} 1087; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1088 %tmp3 = icmp ne <2 x i64> %A, zeroinitializer; 1089 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1090 ret <2 x i64> %tmp4 1091} 1092 1093define <8 x i8> @cmhsz8xi8(<8 x i8> %A) { 1094; CHECK-LABEL: cmhsz8xi8: 1095; CHECK: movi {{v[0-9]+}}.8b, #{{0x2|2}} 1096; CHECK-NEXT: cmhs {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1097 %tmp3 = icmp uge <8 x i8> %A, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2> 1098 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 1099 ret <8 x i8> %tmp4 1100} 1101 1102define <16 x i8> @cmhsz16xi8(<16 x i8> %A) { 1103; CHECK-LABEL: cmhsz16xi8: 1104; CHECK: movi {{v[0-9]+}}.16b, #{{0x2|2}} 1105; CHECK-NEXT: cmhs {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1106 %tmp3 = icmp uge <16 x i8> %A, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2> 1107 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 1108 ret <16 x i8> %tmp4 1109} 1110 1111define <4 x i16> @cmhsz4xi16(<4 x i16> %A) { 1112; CHECK-LABEL: cmhsz4xi16: 1113; CHECK: movi {{v[0-9]+}}.4h, #{{0x2|2}} 1114; CHECK-NEXT: cmhs {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h 1115 %tmp3 = icmp uge <4 x i16> %A, <i16 2, i16 2, i16 2, i16 2> 1116 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 1117 ret <4 x i16> %tmp4 1118} 1119 1120define <8 x i16> @cmhsz8xi16(<8 x i16> %A) { 1121; CHECK-LABEL: cmhsz8xi16: 1122; CHECK: movi {{v[0-9]+}}.8h, #{{0x2|2}} 1123; CHECK-NEXT: cmhs {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h 1124 %tmp3 = icmp uge <8 x i16> %A, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2> 1125 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 1126 ret <8 x i16> %tmp4 1127} 1128 1129define <2 x i32> @cmhsz2xi32(<2 x i32> %A) { 1130; CHECK-LABEL: cmhsz2xi32: 1131; CHECK: movi {{v[0-9]+}}.2s, #{{0x2|2}} 1132; CHECK-NEXT: cmhs {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 1133 %tmp3 = icmp uge <2 x i32> %A, <i32 2, i32 2> 1134 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1135 ret <2 x i32> %tmp4 1136} 1137 1138define <4 x i32> @cmhsz4xi32(<4 x i32> %A) { 1139; CHECK-LABEL: cmhsz4xi32: 1140; CHECK: movi {{v[0-9]+}}.4s, #{{0x2|2}} 1141; CHECK-NEXT: cmhs {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s 1142 %tmp3 = icmp uge <4 x i32> %A, <i32 2, i32 2, i32 2, i32 2> 1143 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1144 ret <4 x i32> %tmp4 1145} 1146 1147define <2 x i64> @cmhsz2xi64(<2 x i64> %A) { 1148; CHECK-LABEL: cmhsz2xi64: 1149; CHECK: mov w[[TWO:[0-9]+]], #2 1150; CHECK-NEXT: {{v[0-9]+}}.2d, x[[TWO]] 1151; CHECK-NEXT: cmhs {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 1152 %tmp3 = icmp uge <2 x i64> %A, <i64 2, i64 2> 1153 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1154 ret <2 x i64> %tmp4 1155} 1156 1157 1158define <8 x i8> @cmhiz8xi8(<8 x i8> %A) { 1159; CHECK-LABEL: cmhiz8xi8: 1160; CHECK: movi {{v[0-9]+}}.8b, #{{0x1|1}} 1161; CHECK-NEXT: cmhi {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1162 %tmp3 = icmp ugt <8 x i8> %A, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> 1163 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 1164 ret <8 x i8> %tmp4 1165} 1166 1167define <16 x i8> @cmhiz16xi8(<16 x i8> %A) { 1168; CHECK-LABEL: cmhiz16xi8: 1169; CHECK: movi {{v[0-9]+}}.16b, #{{0x1|1}} 1170; CHECK-NEXT: cmhi {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1171 %tmp3 = icmp ugt <16 x i8> %A, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> 1172 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 1173 ret <16 x i8> %tmp4 1174} 1175 1176define <4 x i16> @cmhiz4xi16(<4 x i16> %A) { 1177; CHECK-LABEL: cmhiz4xi16: 1178; CHECK: movi {{v[0-9]+}}.4h, #{{0x1|1}} 1179; CHECK-NEXT: cmhi {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h 1180 %tmp3 = icmp ugt <4 x i16> %A, <i16 1, i16 1, i16 1, i16 1> 1181 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 1182 ret <4 x i16> %tmp4 1183} 1184 1185define <8 x i16> @cmhiz8xi16(<8 x i16> %A) { 1186; CHECK-LABEL: cmhiz8xi16: 1187; CHECK: movi {{v[0-9]+}}.8h, #{{0x1|1}} 1188; CHECK-NEXT: cmhi {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h 1189 %tmp3 = icmp ugt <8 x i16> %A, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 1190 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 1191 ret <8 x i16> %tmp4 1192} 1193 1194define <2 x i32> @cmhiz2xi32(<2 x i32> %A) { 1195; CHECK-LABEL: cmhiz2xi32: 1196; CHECK: movi {{v[0-9]+}}.2s, #{{0x1|1}} 1197; CHECK-NEXT: cmhi {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 1198 %tmp3 = icmp ugt <2 x i32> %A, <i32 1, i32 1> 1199 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1200 ret <2 x i32> %tmp4 1201} 1202 1203define <4 x i32> @cmhiz4xi32(<4 x i32> %A) { 1204; CHECK-LABEL: cmhiz4xi32: 1205; CHECK: movi {{v[0-9]+}}.4s, #{{0x1|1}} 1206; CHECK-NEXT: cmhi {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s 1207 %tmp3 = icmp ugt <4 x i32> %A, <i32 1, i32 1, i32 1, i32 1> 1208 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1209 ret <4 x i32> %tmp4 1210} 1211 1212define <2 x i64> @cmhiz2xi64(<2 x i64> %A) { 1213; CHECK-LABEL: cmhiz2xi64: 1214; CHECK: mov w[[ONE:[0-9]+]], #1 1215; CHECK-NEXT: dup {{v[0-9]+}}.2d, x[[ONE]] 1216; CHECK-NEXT: cmhi {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 1217 %tmp3 = icmp ugt <2 x i64> %A, <i64 1, i64 1> 1218 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1219 ret <2 x i64> %tmp4 1220} 1221 1222define <8 x i8> @cmlsz8xi8(<8 x i8> %A) { 1223; CHECK-LABEL: cmlsz8xi8: 1224; Using registers other than v0, v1 are possible, but would be odd. 1225; LS implemented as HS, so check reversed operands. 1226; CHECK: movi {{v1.8b|v1.2d}}, #{{0x0|0}} 1227; CHECK-NEXT: cmhs {{v[0-9]+}}.8b, v1.8b, v0.8b 1228 %tmp3 = icmp ule <8 x i8> %A, zeroinitializer; 1229 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 1230 ret <8 x i8> %tmp4 1231} 1232 1233define <16 x i8> @cmlsz16xi8(<16 x i8> %A) { 1234; CHECK-LABEL: cmlsz16xi8: 1235; Using registers other than v0, v1 are possible, but would be odd. 1236; LS implemented as HS, so check reversed operands. 1237; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}} 1238; CHECK-NEXT: cmhs {{v[0-9]+}}.16b, v1.16b, v0.16b 1239 %tmp3 = icmp ule <16 x i8> %A, zeroinitializer; 1240 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 1241 ret <16 x i8> %tmp4 1242} 1243 1244define <4 x i16> @cmlsz4xi16(<4 x i16> %A) { 1245; CHECK-LABEL: cmlsz4xi16: 1246; Using registers other than v0, v1 are possible, but would be odd. 1247; LS implemented as HS, so check reversed operands. 1248; CHECK: movi {{v1.8b|v1.2d}}, #{{0x0|0}} 1249; CHECK-NEXT: cmhs {{v[0-9]+}}.4h, v1.4h, v0.4h 1250 %tmp3 = icmp ule <4 x i16> %A, zeroinitializer; 1251 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 1252 ret <4 x i16> %tmp4 1253} 1254 1255define <8 x i16> @cmlsz8xi16(<8 x i16> %A) { 1256; CHECK-LABEL: cmlsz8xi16: 1257; Using registers other than v0, v1 are possible, but would be odd. 1258; LS implemented as HS, so check reversed operands. 1259; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}} 1260; CHECK-NEXT: cmhs {{v[0-9]+}}.8h, v1.8h, v0.8h 1261 %tmp3 = icmp ule <8 x i16> %A, zeroinitializer; 1262 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 1263 ret <8 x i16> %tmp4 1264} 1265 1266define <2 x i32> @cmlsz2xi32(<2 x i32> %A) { 1267; CHECK-LABEL: cmlsz2xi32: 1268; Using registers other than v0, v1 are possible, but would be odd. 1269; LS implemented as HS, so check reversed operands. 1270; CHECK: movi {{v1.8b|v1.2d}}, #{{0x0|0}} 1271; CHECK-NEXT: cmhs {{v[0-9]+}}.2s, v1.2s, v0.2s 1272 %tmp3 = icmp ule <2 x i32> %A, zeroinitializer; 1273 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1274 ret <2 x i32> %tmp4 1275} 1276 1277define <4 x i32> @cmlsz4xi32(<4 x i32> %A) { 1278; CHECK-LABEL: cmlsz4xi32: 1279; Using registers other than v0, v1 are possible, but would be odd. 1280; LS implemented as HS, so check reversed operands. 1281; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}} 1282; CHECK-NEXT: cmhs {{v[0-9]+}}.4s, v1.4s, v0.4s 1283 %tmp3 = icmp ule <4 x i32> %A, zeroinitializer; 1284 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1285 ret <4 x i32> %tmp4 1286} 1287 1288define <2 x i64> @cmlsz2xi64(<2 x i64> %A) { 1289; CHECK-LABEL: cmlsz2xi64: 1290; Using registers other than v0, v1 are possible, but would be odd. 1291; LS implemented as HS, so check reversed operands. 1292; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}} 1293; CHECK-NEXT: cmhs {{v[0-9]+}}.2d, v1.2d, v0.2d 1294 %tmp3 = icmp ule <2 x i64> %A, zeroinitializer; 1295 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1296 ret <2 x i64> %tmp4 1297} 1298 1299define <8 x i8> @cmloz8xi8(<8 x i8> %A) { 1300; CHECK-LABEL: cmloz8xi8: 1301; Using registers other than v0, v1 are possible, but would be odd. 1302; LO implemented as HI, so check reversed operands. 1303; CHECK: movi v1.8b, #{{0x2|2}} 1304; CHECK-NEXT: cmhi {{v[0-9]+}}.8b, v1.8b, {{v[0-9]+}}.8b 1305 %tmp3 = icmp ult <8 x i8> %A, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2> 1306 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 1307 ret <8 x i8> %tmp4 1308} 1309 1310define <16 x i8> @cmloz16xi8(<16 x i8> %A) { 1311; CHECK-LABEL: cmloz16xi8: 1312; Using registers other than v0, v1 are possible, but would be odd. 1313; LO implemented as HI, so check reversed operands. 1314; CHECK: movi v1.16b, #{{0x2|2}} 1315; CHECK-NEXT: cmhi {{v[0-9]+}}.16b, v1.16b, v0.16b 1316 %tmp3 = icmp ult <16 x i8> %A, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2> 1317 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 1318 ret <16 x i8> %tmp4 1319} 1320 1321define <4 x i16> @cmloz4xi16(<4 x i16> %A) { 1322; CHECK-LABEL: cmloz4xi16: 1323; Using registers other than v0, v1 are possible, but would be odd. 1324; LO implemented as HI, so check reversed operands. 1325; CHECK: movi v1.4h, #{{0x2|2}} 1326; CHECK-NEXT: cmhi {{v[0-9]+}}.4h, v1.4h, v0.4h 1327 %tmp3 = icmp ult <4 x i16> %A, <i16 2, i16 2, i16 2, i16 2> 1328 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 1329 ret <4 x i16> %tmp4 1330} 1331 1332define <8 x i16> @cmloz8xi16(<8 x i16> %A) { 1333; CHECK-LABEL: cmloz8xi16: 1334; Using registers other than v0, v1 are possible, but would be odd. 1335; LO implemented as HI, so check reversed operands. 1336; CHECK: movi v1.8h, #{{0x2|2}} 1337; CHECK-NEXT: cmhi {{v[0-9]+}}.8h, v1.8h, v0.8h 1338 %tmp3 = icmp ult <8 x i16> %A, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2> 1339 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 1340 ret <8 x i16> %tmp4 1341} 1342 1343define <2 x i32> @cmloz2xi32(<2 x i32> %A) { 1344; CHECK-LABEL: cmloz2xi32: 1345; Using registers other than v0, v1 are possible, but would be odd. 1346; LO implemented as HI, so check reversed operands. 1347; CHECK: movi v1.2s, #{{0x2|2}} 1348; CHECK-NEXT: cmhi {{v[0-9]+}}.2s, v1.2s, v0.2s 1349 %tmp3 = icmp ult <2 x i32> %A, <i32 2, i32 2> 1350 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1351 ret <2 x i32> %tmp4 1352} 1353 1354define <4 x i32> @cmloz4xi32(<4 x i32> %A) { 1355; CHECK-LABEL: cmloz4xi32: 1356; Using registers other than v0, v1 are possible, but would be odd. 1357; LO implemented as HI, so check reversed operands. 1358; CHECK: movi v1.4s, #{{0x2|2}} 1359; CHECK-NEXT: cmhi {{v[0-9]+}}.4s, v1.4s, v0.4s 1360 %tmp3 = icmp ult <4 x i32> %A, <i32 2, i32 2, i32 2, i32 2> 1361 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1362 ret <4 x i32> %tmp4 1363} 1364 1365define <2 x i64> @cmloz2xi64(<2 x i64> %A) { 1366; CHECK-LABEL: cmloz2xi64: 1367; Using registers other than v0, v1 are possible, but would be odd. 1368; LO implemented as HI, so check reversed operands. 1369; CHECK: mov w[[TWO:[0-9]+]], #2 1370; CHECK-NEXT: dup v1.2d, x[[TWO]] 1371; CHECK-NEXT: cmhi {{v[0-9]+}}.2d, v1.2d, v0.2d 1372 %tmp3 = icmp ult <2 x i64> %A, <i64 2, i64 2> 1373 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1374 ret <2 x i64> %tmp4 1375} 1376 1377 1378define <2 x i32> @fcmoeq2xfloat(<2 x float> %A, <2 x float> %B) { 1379; CHECK-LABEL: fcmoeq2xfloat: 1380; CHECK: fcmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 1381 %tmp3 = fcmp oeq <2 x float> %A, %B 1382 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1383 ret <2 x i32> %tmp4 1384} 1385 1386define <4 x i32> @fcmoeq4xfloat(<4 x float> %A, <4 x float> %B) { 1387; CHECK-LABEL: fcmoeq4xfloat: 1388; CHECK: fcmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s 1389 %tmp3 = fcmp oeq <4 x float> %A, %B 1390 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1391 ret <4 x i32> %tmp4 1392} 1393define <2 x i64> @fcmoeq2xdouble(<2 x double> %A, <2 x double> %B) { 1394; CHECK-LABEL: fcmoeq2xdouble: 1395; CHECK: fcmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 1396 %tmp3 = fcmp oeq <2 x double> %A, %B 1397 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1398 ret <2 x i64> %tmp4 1399} 1400 1401define <2 x i32> @fcmoge2xfloat(<2 x float> %A, <2 x float> %B) { 1402; CHECK-LABEL: fcmoge2xfloat: 1403; CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 1404 %tmp3 = fcmp oge <2 x float> %A, %B 1405 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1406 ret <2 x i32> %tmp4 1407} 1408 1409define <4 x i32> @fcmoge4xfloat(<4 x float> %A, <4 x float> %B) { 1410; CHECK-LABEL: fcmoge4xfloat: 1411; CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s 1412 %tmp3 = fcmp oge <4 x float> %A, %B 1413 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1414 ret <4 x i32> %tmp4 1415} 1416define <2 x i64> @fcmoge2xdouble(<2 x double> %A, <2 x double> %B) { 1417; CHECK-LABEL: fcmoge2xdouble: 1418; CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 1419 %tmp3 = fcmp oge <2 x double> %A, %B 1420 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1421 ret <2 x i64> %tmp4 1422} 1423 1424define <2 x i32> @fcmogt2xfloat(<2 x float> %A, <2 x float> %B) { 1425; CHECK-LABEL: fcmogt2xfloat: 1426; CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 1427 %tmp3 = fcmp ogt <2 x float> %A, %B 1428 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1429 ret <2 x i32> %tmp4 1430} 1431 1432define <4 x i32> @fcmogt4xfloat(<4 x float> %A, <4 x float> %B) { 1433; CHECK-LABEL: fcmogt4xfloat: 1434; CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s 1435 %tmp3 = fcmp ogt <4 x float> %A, %B 1436 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1437 ret <4 x i32> %tmp4 1438} 1439define <2 x i64> @fcmogt2xdouble(<2 x double> %A, <2 x double> %B) { 1440; CHECK-LABEL: fcmogt2xdouble: 1441; CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 1442 %tmp3 = fcmp ogt <2 x double> %A, %B 1443 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1444 ret <2 x i64> %tmp4 1445} 1446 1447define <2 x i32> @fcmole2xfloat(<2 x float> %A, <2 x float> %B) { 1448; CHECK-LABEL: fcmole2xfloat: 1449; Using registers other than v0, v1 are possible, but would be odd. 1450; OLE implemented as OGE, so check reversed operands. 1451; CHECK: fcmge {{v[0-9]+}}.2s, v1.2s, v0.2s 1452 %tmp3 = fcmp ole <2 x float> %A, %B 1453 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1454 ret <2 x i32> %tmp4 1455} 1456 1457define <4 x i32> @fcmole4xfloat(<4 x float> %A, <4 x float> %B) { 1458; CHECK-LABEL: fcmole4xfloat: 1459; Using registers other than v0, v1 are possible, but would be odd. 1460; OLE implemented as OGE, so check reversed operands. 1461; CHECK: fcmge {{v[0-9]+}}.4s, v1.4s, v0.4s 1462 %tmp3 = fcmp ole <4 x float> %A, %B 1463 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1464 ret <4 x i32> %tmp4 1465} 1466define <2 x i64> @fcmole2xdouble(<2 x double> %A, <2 x double> %B) { 1467; CHECK-LABEL: fcmole2xdouble: 1468; Using registers other than v0, v1 are possible, but would be odd. 1469; OLE implemented as OGE, so check reversed operands. 1470; CHECK: fcmge {{v[0-9]+}}.2d, v1.2d, v0.2d 1471 %tmp3 = fcmp ole <2 x double> %A, %B 1472 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1473 ret <2 x i64> %tmp4 1474} 1475 1476define <2 x i32> @fcmolt2xfloat(<2 x float> %A, <2 x float> %B) { 1477; CHECK-LABEL: fcmolt2xfloat: 1478; Using registers other than v0, v1 are possible, but would be odd. 1479; OLE implemented as OGE, so check reversed operands. 1480; CHECK: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s 1481 %tmp3 = fcmp olt <2 x float> %A, %B 1482 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1483 ret <2 x i32> %tmp4 1484} 1485 1486define <4 x i32> @fcmolt4xfloat(<4 x float> %A, <4 x float> %B) { 1487; CHECK-LABEL: fcmolt4xfloat: 1488; Using registers other than v0, v1 are possible, but would be odd. 1489; OLE implemented as OGE, so check reversed operands. 1490; CHECK: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s 1491 %tmp3 = fcmp olt <4 x float> %A, %B 1492 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1493 ret <4 x i32> %tmp4 1494} 1495define <2 x i64> @fcmolt2xdouble(<2 x double> %A, <2 x double> %B) { 1496; CHECK-LABEL: fcmolt2xdouble: 1497; Using registers other than v0, v1 are possible, but would be odd. 1498; OLE implemented as OGE, so check reversed operands. 1499; CHECK: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d 1500 %tmp3 = fcmp olt <2 x double> %A, %B 1501 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1502 ret <2 x i64> %tmp4 1503} 1504 1505define <2 x i32> @fcmone2xfloat(<2 x float> %A, <2 x float> %B) { 1506; CHECK-LABEL: fcmone2xfloat: 1507; Using registers other than v0, v1 are possible, but would be odd. 1508; ONE = OGT | OLT, OLT implemented as OGT so check reversed operands 1509; CHECK: fcmgt {{v[0-9]+}}.2s, v0.2s, v1.2s 1510; CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s 1511; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1512 %tmp3 = fcmp one <2 x float> %A, %B 1513 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1514 ret <2 x i32> %tmp4 1515} 1516 1517define <4 x i32> @fcmone4xfloat(<4 x float> %A, <4 x float> %B) { 1518; CHECK-LABEL: fcmone4xfloat: 1519; Using registers other than v0, v1 are possible, but would be odd. 1520; ONE = OGT | OLT, OLT implemented as OGT so check reversed operands 1521; CHECK: fcmgt {{v[0-9]+}}.4s, v0.4s, v1.4s 1522; CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s 1523; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1524 %tmp3 = fcmp one <4 x float> %A, %B 1525 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1526 ret <4 x i32> %tmp4 1527} 1528define <2 x i64> @fcmone2xdouble(<2 x double> %A, <2 x double> %B) { 1529; CHECK-LABEL: fcmone2xdouble: 1530; Using registers other than v0, v1 are possible, but would be odd. 1531; ONE = OGT | OLT, OLT implemented as OGT so check reversed operands 1532; CHECK: fcmgt {{v[0-9]+}}.2d, v0.2d, v1.2d 1533; CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d 1534; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1535; todo check reversed operands 1536 %tmp3 = fcmp one <2 x double> %A, %B 1537 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1538 ret <2 x i64> %tmp4 1539} 1540 1541 1542define <2 x i32> @fcmord2xfloat(<2 x float> %A, <2 x float> %B) { 1543; CHECK-LABEL: fcmord2xfloat: 1544; Using registers other than v0, v1 are possible, but would be odd. 1545; ORD = OGE | OLT, OLT implemented as OGT, so check reversed operands. 1546; CHECK: fcmge {{v[0-9]+}}.2s, v0.2s, v1.2s 1547; CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s 1548; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1549 %tmp3 = fcmp ord <2 x float> %A, %B 1550 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1551 ret <2 x i32> %tmp4 1552} 1553 1554 1555define <4 x i32> @fcmord4xfloat(<4 x float> %A, <4 x float> %B) { 1556; CHECK-LABEL: fcmord4xfloat: 1557; Using registers other than v0, v1 are possible, but would be odd. 1558; ORD = OGE | OLT, OLT implemented as OGT, so check reversed operands. 1559; CHECK: fcmge {{v[0-9]+}}.4s, v0.4s, v1.4s 1560; CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s 1561; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1562 %tmp3 = fcmp ord <4 x float> %A, %B 1563 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1564 ret <4 x i32> %tmp4 1565} 1566 1567define <2 x i64> @fcmord2xdouble(<2 x double> %A, <2 x double> %B) { 1568; CHECK-LABEL: fcmord2xdouble: 1569; Using registers other than v0, v1 are possible, but would be odd. 1570; ORD = OGE | OLT, OLT implemented as OGT, so check reversed operands. 1571; CHECK: fcmge {{v[0-9]+}}.2d, v0.2d, v1.2d 1572; CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d 1573; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1574 %tmp3 = fcmp ord <2 x double> %A, %B 1575 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1576 ret <2 x i64> %tmp4 1577} 1578 1579 1580define <2 x i32> @fcmuno2xfloat(<2 x float> %A, <2 x float> %B) { 1581; CHECK-LABEL: fcmuno2xfloat: 1582; Using registers other than v0, v1 are possible, but would be odd. 1583; UNO = !(OGE | OLT), OLT implemented as OGT, so check reversed operands. 1584; CHECK: fcmge {{v[0-9]+}}.2s, v0.2s, v1.2s 1585; CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s 1586; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1587; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1588 %tmp3 = fcmp uno <2 x float> %A, %B 1589 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1590 ret <2 x i32> %tmp4 1591} 1592 1593define <4 x i32> @fcmuno4xfloat(<4 x float> %A, <4 x float> %B) { 1594; CHECK-LABEL: fcmuno4xfloat: 1595; Using registers other than v0, v1 are possible, but would be odd. 1596; UNO = !(OGE | OLT), OLT implemented as OGT, so check reversed operands. 1597; CHECK: fcmge {{v[0-9]+}}.4s, v0.4s, v1.4s 1598; CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s 1599; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1600; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1601 %tmp3 = fcmp uno <4 x float> %A, %B 1602 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1603 ret <4 x i32> %tmp4 1604} 1605 1606define <2 x i64> @fcmuno2xdouble(<2 x double> %A, <2 x double> %B) { 1607; CHECK-LABEL: fcmuno2xdouble: 1608; Using registers other than v0, v1 are possible, but would be odd. 1609; UNO = !(OGE | OLT), OLT implemented as OGT, so check reversed operands. 1610; CHECK: fcmge {{v[0-9]+}}.2d, v0.2d, v1.2d 1611; CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d 1612; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1613; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1614 %tmp3 = fcmp uno <2 x double> %A, %B 1615 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1616 ret <2 x i64> %tmp4 1617} 1618 1619define <2 x i32> @fcmueq2xfloat(<2 x float> %A, <2 x float> %B) { 1620; CHECK-LABEL: fcmueq2xfloat: 1621; Using registers other than v0, v1 are possible, but would be odd. 1622; UEQ = !ONE = !(OGT | OLT), OLT implemented as OGT so check reversed operands 1623; CHECK: fcmgt {{v[0-9]+}}.2s, v0.2s, v1.2s 1624; CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s 1625; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1626; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1627 %tmp3 = fcmp ueq <2 x float> %A, %B 1628 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1629 ret <2 x i32> %tmp4 1630} 1631 1632define <4 x i32> @fcmueq4xfloat(<4 x float> %A, <4 x float> %B) { 1633; CHECK-LABEL: fcmueq4xfloat: 1634; Using registers other than v0, v1 are possible, but would be odd. 1635; UEQ = !ONE = !(OGT | OLT), OLT implemented as OGT so check reversed operands 1636; CHECK: fcmgt {{v[0-9]+}}.4s, v0.4s, v1.4s 1637; CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s 1638; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1639; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1640 %tmp3 = fcmp ueq <4 x float> %A, %B 1641 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1642 ret <4 x i32> %tmp4 1643} 1644 1645define <2 x i64> @fcmueq2xdouble(<2 x double> %A, <2 x double> %B) { 1646; CHECK-LABEL: fcmueq2xdouble: 1647; Using registers other than v0, v1 are possible, but would be odd. 1648; UEQ = !ONE = !(OGT | OLT), OLT implemented as OGT so check reversed operands 1649; CHECK: fcmgt {{v[0-9]+}}.2d, v0.2d, v1.2d 1650; CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d 1651; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1652; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1653 %tmp3 = fcmp ueq <2 x double> %A, %B 1654 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1655 ret <2 x i64> %tmp4 1656} 1657 1658define <2 x i32> @fcmuge2xfloat(<2 x float> %A, <2 x float> %B) { 1659; CHECK-LABEL: fcmuge2xfloat: 1660; Using registers other than v0, v1 are possible, but would be odd. 1661; UGE = ULE with swapped operands, ULE implemented as !OGT. 1662; CHECK: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s 1663; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1664 %tmp3 = fcmp uge <2 x float> %A, %B 1665 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1666 ret <2 x i32> %tmp4 1667} 1668 1669define <4 x i32> @fcmuge4xfloat(<4 x float> %A, <4 x float> %B) { 1670; CHECK-LABEL: fcmuge4xfloat: 1671; Using registers other than v0, v1 are possible, but would be odd. 1672; UGE = ULE with swapped operands, ULE implemented as !OGT. 1673; CHECK: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s 1674; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1675 %tmp3 = fcmp uge <4 x float> %A, %B 1676 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1677 ret <4 x i32> %tmp4 1678} 1679 1680define <2 x i64> @fcmuge2xdouble(<2 x double> %A, <2 x double> %B) { 1681; CHECK-LABEL: fcmuge2xdouble: 1682; Using registers other than v0, v1 are possible, but would be odd. 1683; UGE = ULE with swapped operands, ULE implemented as !OGT. 1684; CHECK: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d 1685; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1686 %tmp3 = fcmp uge <2 x double> %A, %B 1687 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1688 ret <2 x i64> %tmp4 1689} 1690 1691define <2 x i32> @fcmugt2xfloat(<2 x float> %A, <2 x float> %B) { 1692; CHECK-LABEL: fcmugt2xfloat: 1693; Using registers other than v0, v1 are possible, but would be odd. 1694; UGT = ULT with swapped operands, ULT implemented as !OGE. 1695; CHECK: fcmge {{v[0-9]+}}.2s, v1.2s, v0.2s 1696; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1697 %tmp3 = fcmp ugt <2 x float> %A, %B 1698 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1699 ret <2 x i32> %tmp4 1700} 1701 1702define <4 x i32> @fcmugt4xfloat(<4 x float> %A, <4 x float> %B) { 1703; CHECK-LABEL: fcmugt4xfloat: 1704; Using registers other than v0, v1 are possible, but would be odd. 1705; UGT = ULT with swapped operands, ULT implemented as !OGE. 1706; CHECK: fcmge {{v[0-9]+}}.4s, v1.4s, v0.4s 1707; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1708 %tmp3 = fcmp ugt <4 x float> %A, %B 1709 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1710 ret <4 x i32> %tmp4 1711} 1712define <2 x i64> @fcmugt2xdouble(<2 x double> %A, <2 x double> %B) { 1713; CHECK-LABEL: fcmugt2xdouble: 1714; CHECK: fcmge {{v[0-9]+}}.2d, v1.2d, v0.2d 1715; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1716 %tmp3 = fcmp ugt <2 x double> %A, %B 1717 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1718 ret <2 x i64> %tmp4 1719} 1720 1721define <2 x i32> @fcmule2xfloat(<2 x float> %A, <2 x float> %B) { 1722; CHECK-LABEL: fcmule2xfloat: 1723; Using registers other than v0, v1 are possible, but would be odd. 1724; ULE implemented as !OGT. 1725; CHECK: fcmgt {{v[0-9]+}}.2s, v0.2s, v1.2s 1726; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1727 %tmp3 = fcmp ule <2 x float> %A, %B 1728 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1729 ret <2 x i32> %tmp4 1730} 1731 1732define <4 x i32> @fcmule4xfloat(<4 x float> %A, <4 x float> %B) { 1733; CHECK-LABEL: fcmule4xfloat: 1734; Using registers other than v0, v1 are possible, but would be odd. 1735; ULE implemented as !OGT. 1736; CHECK: fcmgt {{v[0-9]+}}.4s, v0.4s, v1.4s 1737; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1738 %tmp3 = fcmp ule <4 x float> %A, %B 1739 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1740 ret <4 x i32> %tmp4 1741} 1742define <2 x i64> @fcmule2xdouble(<2 x double> %A, <2 x double> %B) { 1743; CHECK-LABEL: fcmule2xdouble: 1744; Using registers other than v0, v1 are possible, but would be odd. 1745; ULE implemented as !OGT. 1746; CHECK: fcmgt {{v[0-9]+}}.2d, v0.2d, v1.2d 1747; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1748 %tmp3 = fcmp ule <2 x double> %A, %B 1749 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1750 ret <2 x i64> %tmp4 1751} 1752 1753define <2 x i32> @fcmult2xfloat(<2 x float> %A, <2 x float> %B) { 1754; CHECK-LABEL: fcmult2xfloat: 1755; Using registers other than v0, v1 are possible, but would be odd. 1756; ULT implemented as !OGE. 1757; CHECK: fcmge {{v[0-9]+}}.2s, v0.2s, v1.2s 1758; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1759 %tmp3 = fcmp ult <2 x float> %A, %B 1760 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1761 ret <2 x i32> %tmp4 1762} 1763 1764define <4 x i32> @fcmult4xfloat(<4 x float> %A, <4 x float> %B) { 1765; CHECK-LABEL: fcmult4xfloat: 1766; Using registers other than v0, v1 are possible, but would be odd. 1767; ULT implemented as !OGE. 1768; CHECK: fcmge {{v[0-9]+}}.4s, v0.4s, v1.4s 1769; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1770 %tmp3 = fcmp ult <4 x float> %A, %B 1771 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1772 ret <4 x i32> %tmp4 1773} 1774define <2 x i64> @fcmult2xdouble(<2 x double> %A, <2 x double> %B) { 1775; CHECK-LABEL: fcmult2xdouble: 1776; Using registers other than v0, v1 are possible, but would be odd. 1777; ULT implemented as !OGE. 1778; CHECK: fcmge {{v[0-9]+}}.2d, v0.2d, v1.2d 1779; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1780 %tmp3 = fcmp ult <2 x double> %A, %B 1781 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1782 ret <2 x i64> %tmp4 1783} 1784 1785define <2 x i32> @fcmune2xfloat(<2 x float> %A, <2 x float> %B) { 1786; CHECK-LABEL: fcmune2xfloat: 1787; Using registers other than v0, v1 are possible, but would be odd. 1788; UNE = !OEQ. 1789; CHECK: fcmeq {{v[0-9]+}}.2s, v0.2s, v1.2s 1790; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1791 %tmp3 = fcmp une <2 x float> %A, %B 1792 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1793 ret <2 x i32> %tmp4 1794} 1795 1796define <4 x i32> @fcmune4xfloat(<4 x float> %A, <4 x float> %B) { 1797; CHECK-LABEL: fcmune4xfloat: 1798; Using registers other than v0, v1 are possible, but would be odd. 1799; UNE = !OEQ. 1800; CHECK: fcmeq {{v[0-9]+}}.4s, v0.4s, v1.4s 1801; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1802 %tmp3 = fcmp une <4 x float> %A, %B 1803 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1804 ret <4 x i32> %tmp4 1805} 1806define <2 x i64> @fcmune2xdouble(<2 x double> %A, <2 x double> %B) { 1807; CHECK-LABEL: fcmune2xdouble: 1808; Using registers other than v0, v1 are possible, but would be odd. 1809; UNE = !OEQ. 1810; CHECK: fcmeq {{v[0-9]+}}.2d, v0.2d, v1.2d 1811; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1812 %tmp3 = fcmp une <2 x double> %A, %B 1813 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1814 ret <2 x i64> %tmp4 1815} 1816 1817define <2 x i32> @fcmoeqz2xfloat(<2 x float> %A) { 1818; CHECK-LABEL: fcmoeqz2xfloat: 1819; CHECK: fcmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 1820 %tmp3 = fcmp oeq <2 x float> %A, zeroinitializer 1821 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1822 ret <2 x i32> %tmp4 1823} 1824 1825define <4 x i32> @fcmoeqz4xfloat(<4 x float> %A) { 1826; CHECK-LABEL: fcmoeqz4xfloat: 1827; CHECK: fcmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 1828 %tmp3 = fcmp oeq <4 x float> %A, zeroinitializer 1829 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1830 ret <4 x i32> %tmp4 1831} 1832define <2 x i64> @fcmoeqz2xdouble(<2 x double> %A) { 1833; CHECK-LABEL: fcmoeqz2xdouble: 1834; CHECK: fcmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 1835 %tmp3 = fcmp oeq <2 x double> %A, zeroinitializer 1836 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1837 ret <2 x i64> %tmp4 1838} 1839 1840 1841define <2 x i32> @fcmogez2xfloat(<2 x float> %A) { 1842; CHECK-LABEL: fcmogez2xfloat: 1843; CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 1844 %tmp3 = fcmp oge <2 x float> %A, zeroinitializer 1845 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1846 ret <2 x i32> %tmp4 1847} 1848 1849define <4 x i32> @fcmogez4xfloat(<4 x float> %A) { 1850; CHECK-LABEL: fcmogez4xfloat: 1851; CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 1852 %tmp3 = fcmp oge <4 x float> %A, zeroinitializer 1853 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1854 ret <4 x i32> %tmp4 1855} 1856define <2 x i64> @fcmogez2xdouble(<2 x double> %A) { 1857; CHECK-LABEL: fcmogez2xdouble: 1858; CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 1859 %tmp3 = fcmp oge <2 x double> %A, zeroinitializer 1860 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1861 ret <2 x i64> %tmp4 1862} 1863 1864define <2 x i32> @fcmogtz2xfloat(<2 x float> %A) { 1865; CHECK-LABEL: fcmogtz2xfloat: 1866; CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 1867 %tmp3 = fcmp ogt <2 x float> %A, zeroinitializer 1868 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1869 ret <2 x i32> %tmp4 1870} 1871 1872define <4 x i32> @fcmogtz4xfloat(<4 x float> %A) { 1873; CHECK-LABEL: fcmogtz4xfloat: 1874; CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 1875 %tmp3 = fcmp ogt <4 x float> %A, zeroinitializer 1876 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1877 ret <4 x i32> %tmp4 1878} 1879define <2 x i64> @fcmogtz2xdouble(<2 x double> %A) { 1880; CHECK-LABEL: fcmogtz2xdouble: 1881; CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 1882 %tmp3 = fcmp ogt <2 x double> %A, zeroinitializer 1883 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1884 ret <2 x i64> %tmp4 1885} 1886 1887define <2 x i32> @fcmoltz2xfloat(<2 x float> %A) { 1888; CHECK-LABEL: fcmoltz2xfloat: 1889; CHECK: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 1890 %tmp3 = fcmp olt <2 x float> %A, zeroinitializer 1891 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1892 ret <2 x i32> %tmp4 1893} 1894 1895define <4 x i32> @fcmoltz4xfloat(<4 x float> %A) { 1896; CHECK-LABEL: fcmoltz4xfloat: 1897; CHECK: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 1898 %tmp3 = fcmp olt <4 x float> %A, zeroinitializer 1899 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1900 ret <4 x i32> %tmp4 1901} 1902 1903define <2 x i64> @fcmoltz2xdouble(<2 x double> %A) { 1904; CHECK-LABEL: fcmoltz2xdouble: 1905; CHECK: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 1906 %tmp3 = fcmp olt <2 x double> %A, zeroinitializer 1907 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1908 ret <2 x i64> %tmp4 1909} 1910 1911define <2 x i32> @fcmolez2xfloat(<2 x float> %A) { 1912; CHECK-LABEL: fcmolez2xfloat: 1913; CHECK: fcmle {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 1914 %tmp3 = fcmp ole <2 x float> %A, zeroinitializer 1915 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1916 ret <2 x i32> %tmp4 1917} 1918 1919define <4 x i32> @fcmolez4xfloat(<4 x float> %A) { 1920; CHECK-LABEL: fcmolez4xfloat: 1921; CHECK: fcmle {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 1922 %tmp3 = fcmp ole <4 x float> %A, zeroinitializer 1923 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1924 ret <4 x i32> %tmp4 1925} 1926 1927define <2 x i64> @fcmolez2xdouble(<2 x double> %A) { 1928; CHECK-LABEL: fcmolez2xdouble: 1929; CHECK: fcmle {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 1930 %tmp3 = fcmp ole <2 x double> %A, zeroinitializer 1931 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1932 ret <2 x i64> %tmp4 1933} 1934 1935define <2 x i32> @fcmonez2xfloat(<2 x float> %A) { 1936; CHECK-LABEL: fcmonez2xfloat: 1937; ONE with zero = OLT | OGT 1938; CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 1939; CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 1940; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1941 %tmp3 = fcmp one <2 x float> %A, zeroinitializer 1942 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1943 ret <2 x i32> %tmp4 1944} 1945 1946define <4 x i32> @fcmonez4xfloat(<4 x float> %A) { 1947; CHECK-LABEL: fcmonez4xfloat: 1948; ONE with zero = OLT | OGT 1949; CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 1950; CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 1951; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1952 %tmp3 = fcmp one <4 x float> %A, zeroinitializer 1953 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1954 ret <4 x i32> %tmp4 1955} 1956define <2 x i64> @fcmonez2xdouble(<2 x double> %A) { 1957; CHECK-LABEL: fcmonez2xdouble: 1958; ONE with zero = OLT | OGT 1959; CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 1960; CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 1961; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1962 %tmp3 = fcmp one <2 x double> %A, zeroinitializer 1963 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1964 ret <2 x i64> %tmp4 1965} 1966 1967define <2 x i32> @fcmordz2xfloat(<2 x float> %A) { 1968; CHECK-LABEL: fcmordz2xfloat: 1969; ORD with zero = OLT | OGE 1970; CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 1971; CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 1972; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1973 %tmp3 = fcmp ord <2 x float> %A, zeroinitializer 1974 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1975 ret <2 x i32> %tmp4 1976} 1977 1978define <4 x i32> @fcmordz4xfloat(<4 x float> %A) { 1979; CHECK-LABEL: fcmordz4xfloat: 1980; ORD with zero = OLT | OGE 1981; CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 1982; CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 1983; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1984 %tmp3 = fcmp ord <4 x float> %A, zeroinitializer 1985 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1986 ret <4 x i32> %tmp4 1987} 1988define <2 x i64> @fcmordz2xdouble(<2 x double> %A) { 1989; CHECK-LABEL: fcmordz2xdouble: 1990; ORD with zero = OLT | OGE 1991; CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 1992; CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 1993; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1994 %tmp3 = fcmp ord <2 x double> %A, zeroinitializer 1995 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1996 ret <2 x i64> %tmp4 1997} 1998 1999define <2 x i32> @fcmueqz2xfloat(<2 x float> %A) { 2000; CHECK-LABEL: fcmueqz2xfloat: 2001; UEQ with zero = !ONE = !(OLT |OGT) 2002; CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 2003; CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 2004; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 2005; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 2006 %tmp3 = fcmp ueq <2 x float> %A, zeroinitializer 2007 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2008 ret <2 x i32> %tmp4 2009} 2010 2011define <4 x i32> @fcmueqz4xfloat(<4 x float> %A) { 2012; CHECK-LABEL: fcmueqz4xfloat: 2013; UEQ with zero = !ONE = !(OLT |OGT) 2014; CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 2015; CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 2016; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2017; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2018 %tmp3 = fcmp ueq <4 x float> %A, zeroinitializer 2019 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2020 ret <4 x i32> %tmp4 2021} 2022 2023define <2 x i64> @fcmueqz2xdouble(<2 x double> %A) { 2024; CHECK-LABEL: fcmueqz2xdouble: 2025; UEQ with zero = !ONE = !(OLT |OGT) 2026; CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 2027; CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 2028; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2029; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2030 %tmp3 = fcmp ueq <2 x double> %A, zeroinitializer 2031 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2032 ret <2 x i64> %tmp4 2033} 2034 2035define <2 x i32> @fcmugez2xfloat(<2 x float> %A) { 2036; CHECK-LABEL: fcmugez2xfloat: 2037; UGE with zero = !OLT 2038; CHECK: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 2039; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 2040 %tmp3 = fcmp uge <2 x float> %A, zeroinitializer 2041 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2042 ret <2 x i32> %tmp4 2043} 2044 2045define <4 x i32> @fcmugez4xfloat(<4 x float> %A) { 2046; CHECK-LABEL: fcmugez4xfloat: 2047; UGE with zero = !OLT 2048; CHECK: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 2049; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2050 %tmp3 = fcmp uge <4 x float> %A, zeroinitializer 2051 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2052 ret <4 x i32> %tmp4 2053} 2054define <2 x i64> @fcmugez2xdouble(<2 x double> %A) { 2055; CHECK-LABEL: fcmugez2xdouble: 2056; UGE with zero = !OLT 2057; CHECK: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 2058; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2059 %tmp3 = fcmp uge <2 x double> %A, zeroinitializer 2060 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2061 ret <2 x i64> %tmp4 2062} 2063 2064define <2 x i32> @fcmugtz2xfloat(<2 x float> %A) { 2065; CHECK-LABEL: fcmugtz2xfloat: 2066; UGT with zero = !OLE 2067; CHECK: fcmle {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 2068; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 2069 %tmp3 = fcmp ugt <2 x float> %A, zeroinitializer 2070 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2071 ret <2 x i32> %tmp4 2072} 2073 2074define <4 x i32> @fcmugtz4xfloat(<4 x float> %A) { 2075; CHECK-LABEL: fcmugtz4xfloat: 2076; UGT with zero = !OLE 2077; CHECK: fcmle {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 2078; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2079 %tmp3 = fcmp ugt <4 x float> %A, zeroinitializer 2080 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2081 ret <4 x i32> %tmp4 2082} 2083define <2 x i64> @fcmugtz2xdouble(<2 x double> %A) { 2084; CHECK-LABEL: fcmugtz2xdouble: 2085; UGT with zero = !OLE 2086; CHECK: fcmle {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 2087; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2088 %tmp3 = fcmp ugt <2 x double> %A, zeroinitializer 2089 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2090 ret <2 x i64> %tmp4 2091} 2092 2093define <2 x i32> @fcmultz2xfloat(<2 x float> %A) { 2094; CHECK-LABEL: fcmultz2xfloat: 2095; ULT with zero = !OGE 2096; CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 2097; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 2098 %tmp3 = fcmp ult <2 x float> %A, zeroinitializer 2099 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2100 ret <2 x i32> %tmp4 2101} 2102 2103define <4 x i32> @fcmultz4xfloat(<4 x float> %A) { 2104; CHECK-LABEL: fcmultz4xfloat: 2105; CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 2106; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2107 %tmp3 = fcmp ult <4 x float> %A, zeroinitializer 2108 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2109 ret <4 x i32> %tmp4 2110} 2111 2112define <2 x i64> @fcmultz2xdouble(<2 x double> %A) { 2113; CHECK-LABEL: fcmultz2xdouble: 2114; CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 2115; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2116 %tmp3 = fcmp ult <2 x double> %A, zeroinitializer 2117 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2118 ret <2 x i64> %tmp4 2119} 2120 2121 2122define <2 x i32> @fcmulez2xfloat(<2 x float> %A) { 2123; CHECK-LABEL: fcmulez2xfloat: 2124; ULE with zero = !OGT 2125; CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 2126; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 2127 %tmp3 = fcmp ule <2 x float> %A, zeroinitializer 2128 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2129 ret <2 x i32> %tmp4 2130} 2131 2132define <4 x i32> @fcmulez4xfloat(<4 x float> %A) { 2133; CHECK-LABEL: fcmulez4xfloat: 2134; ULE with zero = !OGT 2135; CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 2136; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2137 %tmp3 = fcmp ule <4 x float> %A, zeroinitializer 2138 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2139 ret <4 x i32> %tmp4 2140} 2141 2142define <2 x i64> @fcmulez2xdouble(<2 x double> %A) { 2143; CHECK-LABEL: fcmulez2xdouble: 2144; ULE with zero = !OGT 2145; CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 2146; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2147 %tmp3 = fcmp ule <2 x double> %A, zeroinitializer 2148 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2149 ret <2 x i64> %tmp4 2150} 2151 2152define <2 x i32> @fcmunez2xfloat(<2 x float> %A) { 2153; CHECK-LABEL: fcmunez2xfloat: 2154; UNE with zero = !OEQ with zero 2155; CHECK: fcmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 2156; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 2157 %tmp3 = fcmp une <2 x float> %A, zeroinitializer 2158 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2159 ret <2 x i32> %tmp4 2160} 2161 2162define <4 x i32> @fcmunez4xfloat(<4 x float> %A) { 2163; CHECK-LABEL: fcmunez4xfloat: 2164; UNE with zero = !OEQ with zero 2165; CHECK: fcmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 2166; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2167 %tmp3 = fcmp une <4 x float> %A, zeroinitializer 2168 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2169 ret <4 x i32> %tmp4 2170} 2171define <2 x i64> @fcmunez2xdouble(<2 x double> %A) { 2172; CHECK-LABEL: fcmunez2xdouble: 2173; UNE with zero = !OEQ with zero 2174; CHECK: fcmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 2175; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2176 %tmp3 = fcmp une <2 x double> %A, zeroinitializer 2177 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2178 ret <2 x i64> %tmp4 2179} 2180 2181 2182define <2 x i32> @fcmunoz2xfloat(<2 x float> %A) { 2183; CHECK-LABEL: fcmunoz2xfloat: 2184; UNO with zero = !ORD = !(OLT | OGE) 2185; CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 2186; CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 2187; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 2188; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 2189 %tmp3 = fcmp uno <2 x float> %A, zeroinitializer 2190 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2191 ret <2 x i32> %tmp4 2192} 2193 2194define <4 x i32> @fcmunoz4xfloat(<4 x float> %A) { 2195; CHECK-LABEL: fcmunoz4xfloat: 2196; UNO with zero = !ORD = !(OLT | OGE) 2197; CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 2198; CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 2199; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2200; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2201 %tmp3 = fcmp uno <4 x float> %A, zeroinitializer 2202 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2203 ret <4 x i32> %tmp4 2204} 2205 2206define <2 x i64> @fcmunoz2xdouble(<2 x double> %A) { 2207; CHECK-LABEL: fcmunoz2xdouble: 2208; UNO with zero = !ORD = !(OLT | OGE) 2209; CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 2210; CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 2211; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2212; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2213 %tmp3 = fcmp uno <2 x double> %A, zeroinitializer 2214 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2215 ret <2 x i64> %tmp4 2216 2217} 2218