1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
3
4; Odd+Even divisors
5define <4 x i32> @test_srem_odd_even(<4 x i32> %X) nounwind {
6; CHECK-LABEL: test_srem_odd_even:
7; CHECK:       // %bb.0:
8; CHECK-NEXT:    adrp x8, .LCPI0_0
9; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI0_0]
10; CHECK-NEXT:    adrp x8, .LCPI0_1
11; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI0_1]
12; CHECK-NEXT:    adrp x8, .LCPI0_2
13; CHECK-NEXT:    smull2 v3.2d, v0.4s, v1.4s
14; CHECK-NEXT:    smull v1.2d, v0.2s, v1.2s
15; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v3.4s
16; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI0_2]
17; CHECK-NEXT:    adrp x8, .LCPI0_3
18; CHECK-NEXT:    mla v1.4s, v0.4s, v2.4s
19; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI0_3]
20; CHECK-NEXT:    neg v3.4s, v3.4s
21; CHECK-NEXT:    sshl v3.4s, v1.4s, v3.4s
22; CHECK-NEXT:    usra v3.4s, v1.4s, #31
23; CHECK-NEXT:    mls v0.4s, v3.4s, v2.4s
24; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
25; CHECK-NEXT:    movi v1.4s, #1
26; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
27; CHECK-NEXT:    ret
28  %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 25, i32 100>
29  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
30  %ret = zext <4 x i1> %cmp to <4 x i32>
31  ret <4 x i32> %ret
32}
33
34;==============================================================================;
35
36; One all-ones divisor in odd divisor
37define <4 x i32> @test_srem_odd_allones_eq(<4 x i32> %X) nounwind {
38; CHECK-LABEL: test_srem_odd_allones_eq:
39; CHECK:       // %bb.0:
40; CHECK-NEXT:    adrp x10, .LCPI1_0
41; CHECK-NEXT:    mov w8, #52429
42; CHECK-NEXT:    mov w9, #39321
43; CHECK-NEXT:    ldr q1, [x10, :lo12:.LCPI1_0]
44; CHECK-NEXT:    movk w8, #52428, lsl #16
45; CHECK-NEXT:    movk w9, #6553, lsl #16
46; CHECK-NEXT:    dup v2.4s, w8
47; CHECK-NEXT:    dup v3.4s, w9
48; CHECK-NEXT:    mla v3.4s, v0.4s, v2.4s
49; CHECK-NEXT:    cmhs v0.4s, v1.4s, v3.4s
50; CHECK-NEXT:    movi v1.4s, #1
51; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
52; CHECK-NEXT:    ret
53  %srem = srem <4 x i32> %X, <i32 5, i32 5, i32 4294967295, i32 5>
54  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
55  %ret = zext <4 x i1> %cmp to <4 x i32>
56  ret <4 x i32> %ret
57}
58define <4 x i32> @test_srem_odd_allones_ne(<4 x i32> %X) nounwind {
59; CHECK-LABEL: test_srem_odd_allones_ne:
60; CHECK:       // %bb.0:
61; CHECK-NEXT:    adrp x10, .LCPI2_0
62; CHECK-NEXT:    mov w8, #52429
63; CHECK-NEXT:    mov w9, #39321
64; CHECK-NEXT:    ldr q1, [x10, :lo12:.LCPI2_0]
65; CHECK-NEXT:    movk w8, #52428, lsl #16
66; CHECK-NEXT:    movk w9, #6553, lsl #16
67; CHECK-NEXT:    dup v2.4s, w8
68; CHECK-NEXT:    dup v3.4s, w9
69; CHECK-NEXT:    mla v3.4s, v0.4s, v2.4s
70; CHECK-NEXT:    cmhi v0.4s, v3.4s, v1.4s
71; CHECK-NEXT:    movi v1.4s, #1
72; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
73; CHECK-NEXT:    ret
74  %srem = srem <4 x i32> %X, <i32 5, i32 5, i32 4294967295, i32 5>
75  %cmp = icmp ne <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
76  %ret = zext <4 x i1> %cmp to <4 x i32>
77  ret <4 x i32> %ret
78}
79
80; One all-ones divisor in even divisor
81define <4 x i32> @test_srem_even_allones_eq(<4 x i32> %X) nounwind {
82; CHECK-LABEL: test_srem_even_allones_eq:
83; CHECK:       // %bb.0:
84; CHECK-NEXT:    adrp x8, .LCPI3_0
85; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI3_0]
86; CHECK-NEXT:    adrp x8, .LCPI3_1
87; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI3_1]
88; CHECK-NEXT:    adrp x8, .LCPI3_2
89; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI3_2]
90; CHECK-NEXT:    adrp x8, .LCPI3_3
91; CHECK-NEXT:    smull2 v4.2d, v0.4s, v1.4s
92; CHECK-NEXT:    smull v1.2d, v0.2s, v1.2s
93; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
94; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI3_3]
95; CHECK-NEXT:    adrp x8, .LCPI3_4
96; CHECK-NEXT:    mla v1.4s, v0.4s, v2.4s
97; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI3_4]
98; CHECK-NEXT:    neg v3.4s, v3.4s
99; CHECK-NEXT:    sshl v3.4s, v1.4s, v3.4s
100; CHECK-NEXT:    ushr v1.4s, v1.4s, #31
101; CHECK-NEXT:    and v1.16b, v1.16b, v4.16b
102; CHECK-NEXT:    add v1.4s, v3.4s, v1.4s
103; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
104; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
105; CHECK-NEXT:    movi v1.4s, #1
106; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
107; CHECK-NEXT:    ret
108  %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 4294967295, i32 14>
109  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
110  %ret = zext <4 x i1> %cmp to <4 x i32>
111  ret <4 x i32> %ret
112}
113define <4 x i32> @test_srem_even_allones_ne(<4 x i32> %X) nounwind {
114; CHECK-LABEL: test_srem_even_allones_ne:
115; CHECK:       // %bb.0:
116; CHECK-NEXT:    adrp x8, .LCPI4_0
117; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI4_0]
118; CHECK-NEXT:    adrp x8, .LCPI4_1
119; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI4_1]
120; CHECK-NEXT:    adrp x8, .LCPI4_2
121; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI4_2]
122; CHECK-NEXT:    adrp x8, .LCPI4_3
123; CHECK-NEXT:    smull2 v4.2d, v0.4s, v1.4s
124; CHECK-NEXT:    smull v1.2d, v0.2s, v1.2s
125; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
126; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI4_3]
127; CHECK-NEXT:    adrp x8, .LCPI4_4
128; CHECK-NEXT:    mla v1.4s, v0.4s, v2.4s
129; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI4_4]
130; CHECK-NEXT:    neg v3.4s, v3.4s
131; CHECK-NEXT:    sshl v3.4s, v1.4s, v3.4s
132; CHECK-NEXT:    ushr v1.4s, v1.4s, #31
133; CHECK-NEXT:    and v1.16b, v1.16b, v4.16b
134; CHECK-NEXT:    add v1.4s, v3.4s, v1.4s
135; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
136; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
137; CHECK-NEXT:    mvn v0.16b, v0.16b
138; CHECK-NEXT:    movi v1.4s, #1
139; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
140; CHECK-NEXT:    ret
141  %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 4294967295, i32 14>
142  %cmp = icmp ne <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
143  %ret = zext <4 x i1> %cmp to <4 x i32>
144  ret <4 x i32> %ret
145}
146
147; One all-ones divisor in odd+even divisor
148define <4 x i32> @test_srem_odd_even_allones_eq(<4 x i32> %X) nounwind {
149; CHECK-LABEL: test_srem_odd_even_allones_eq:
150; CHECK:       // %bb.0:
151; CHECK-NEXT:    adrp x8, .LCPI5_0
152; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI5_0]
153; CHECK-NEXT:    adrp x8, .LCPI5_1
154; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI5_1]
155; CHECK-NEXT:    adrp x8, .LCPI5_2
156; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI5_2]
157; CHECK-NEXT:    adrp x8, .LCPI5_3
158; CHECK-NEXT:    smull2 v4.2d, v0.4s, v1.4s
159; CHECK-NEXT:    smull v1.2d, v0.2s, v1.2s
160; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
161; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI5_3]
162; CHECK-NEXT:    adrp x8, .LCPI5_4
163; CHECK-NEXT:    mla v1.4s, v0.4s, v2.4s
164; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI5_4]
165; CHECK-NEXT:    neg v3.4s, v3.4s
166; CHECK-NEXT:    sshl v3.4s, v1.4s, v3.4s
167; CHECK-NEXT:    ushr v1.4s, v1.4s, #31
168; CHECK-NEXT:    and v1.16b, v1.16b, v4.16b
169; CHECK-NEXT:    add v1.4s, v3.4s, v1.4s
170; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
171; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
172; CHECK-NEXT:    movi v1.4s, #1
173; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
174; CHECK-NEXT:    ret
175  %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 4294967295, i32 100>
176  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
177  %ret = zext <4 x i1> %cmp to <4 x i32>
178  ret <4 x i32> %ret
179}
180define <4 x i32> @test_srem_odd_even_allones_ne(<4 x i32> %X) nounwind {
181; CHECK-LABEL: test_srem_odd_even_allones_ne:
182; CHECK:       // %bb.0:
183; CHECK-NEXT:    adrp x8, .LCPI6_0
184; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI6_0]
185; CHECK-NEXT:    adrp x8, .LCPI6_1
186; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI6_1]
187; CHECK-NEXT:    adrp x8, .LCPI6_2
188; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI6_2]
189; CHECK-NEXT:    adrp x8, .LCPI6_3
190; CHECK-NEXT:    smull2 v4.2d, v0.4s, v1.4s
191; CHECK-NEXT:    smull v1.2d, v0.2s, v1.2s
192; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
193; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI6_3]
194; CHECK-NEXT:    adrp x8, .LCPI6_4
195; CHECK-NEXT:    mla v1.4s, v0.4s, v2.4s
196; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI6_4]
197; CHECK-NEXT:    neg v3.4s, v3.4s
198; CHECK-NEXT:    sshl v3.4s, v1.4s, v3.4s
199; CHECK-NEXT:    ushr v1.4s, v1.4s, #31
200; CHECK-NEXT:    and v1.16b, v1.16b, v4.16b
201; CHECK-NEXT:    add v1.4s, v3.4s, v1.4s
202; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
203; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
204; CHECK-NEXT:    mvn v0.16b, v0.16b
205; CHECK-NEXT:    movi v1.4s, #1
206; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
207; CHECK-NEXT:    ret
208  %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 4294967295, i32 100>
209  %cmp = icmp ne <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
210  %ret = zext <4 x i1> %cmp to <4 x i32>
211  ret <4 x i32> %ret
212}
213
214;------------------------------------------------------------------------------;
215
216; One power-of-two divisor in odd divisor
217define <4 x i32> @test_srem_odd_poweroftwo(<4 x i32> %X) nounwind {
218; CHECK-LABEL: test_srem_odd_poweroftwo:
219; CHECK:       // %bb.0:
220; CHECK-NEXT:    adrp x8, .LCPI7_0
221; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI7_0]
222; CHECK-NEXT:    adrp x8, .LCPI7_1
223; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI7_1]
224; CHECK-NEXT:    adrp x8, .LCPI7_2
225; CHECK-NEXT:    smull2 v3.2d, v0.4s, v1.4s
226; CHECK-NEXT:    smull v1.2d, v0.2s, v1.2s
227; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v3.4s
228; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI7_2]
229; CHECK-NEXT:    adrp x8, .LCPI7_3
230; CHECK-NEXT:    mla v1.4s, v0.4s, v2.4s
231; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI7_3]
232; CHECK-NEXT:    neg v3.4s, v3.4s
233; CHECK-NEXT:    sshl v3.4s, v1.4s, v3.4s
234; CHECK-NEXT:    usra v3.4s, v1.4s, #31
235; CHECK-NEXT:    mls v0.4s, v3.4s, v2.4s
236; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
237; CHECK-NEXT:    movi v1.4s, #1
238; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
239; CHECK-NEXT:    ret
240  %srem = srem <4 x i32> %X, <i32 5, i32 5, i32 16, i32 5>
241  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
242  %ret = zext <4 x i1> %cmp to <4 x i32>
243  ret <4 x i32> %ret
244}
245
246; One power-of-two divisor in even divisor
247define <4 x i32> @test_srem_even_poweroftwo(<4 x i32> %X) nounwind {
248; CHECK-LABEL: test_srem_even_poweroftwo:
249; CHECK:       // %bb.0:
250; CHECK-NEXT:    adrp x8, .LCPI8_0
251; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI8_0]
252; CHECK-NEXT:    adrp x8, .LCPI8_1
253; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI8_1]
254; CHECK-NEXT:    smull2 v3.2d, v0.4s, v1.4s
255; CHECK-NEXT:    smull v1.2d, v0.2s, v1.2s
256; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v3.4s
257; CHECK-NEXT:    add v1.4s, v1.4s, v0.4s
258; CHECK-NEXT:    sshr v3.4s, v1.4s, #3
259; CHECK-NEXT:    usra v3.4s, v1.4s, #31
260; CHECK-NEXT:    mls v0.4s, v3.4s, v2.4s
261; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
262; CHECK-NEXT:    movi v1.4s, #1
263; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
264; CHECK-NEXT:    ret
265  %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 16, i32 14>
266  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
267  %ret = zext <4 x i1> %cmp to <4 x i32>
268  ret <4 x i32> %ret
269}
270
271; One power-of-two divisor in odd+even divisor
272define <4 x i32> @test_srem_odd_even_poweroftwo(<4 x i32> %X) nounwind {
273; CHECK-LABEL: test_srem_odd_even_poweroftwo:
274; CHECK:       // %bb.0:
275; CHECK-NEXT:    adrp x8, .LCPI9_0
276; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI9_0]
277; CHECK-NEXT:    adrp x8, .LCPI9_1
278; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI9_1]
279; CHECK-NEXT:    adrp x8, .LCPI9_2
280; CHECK-NEXT:    smull2 v3.2d, v0.4s, v1.4s
281; CHECK-NEXT:    smull v1.2d, v0.2s, v1.2s
282; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v3.4s
283; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI9_2]
284; CHECK-NEXT:    adrp x8, .LCPI9_3
285; CHECK-NEXT:    mla v1.4s, v0.4s, v2.4s
286; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI9_3]
287; CHECK-NEXT:    neg v3.4s, v3.4s
288; CHECK-NEXT:    sshl v3.4s, v1.4s, v3.4s
289; CHECK-NEXT:    usra v3.4s, v1.4s, #31
290; CHECK-NEXT:    mls v0.4s, v3.4s, v2.4s
291; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
292; CHECK-NEXT:    movi v1.4s, #1
293; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
294; CHECK-NEXT:    ret
295  %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 16, i32 100>
296  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
297  %ret = zext <4 x i1> %cmp to <4 x i32>
298  ret <4 x i32> %ret
299}
300
301;------------------------------------------------------------------------------;
302
303; One one divisor in odd divisor
304define <4 x i32> @test_srem_odd_one(<4 x i32> %X) nounwind {
305; CHECK-LABEL: test_srem_odd_one:
306; CHECK:       // %bb.0:
307; CHECK-NEXT:    adrp x10, .LCPI10_0
308; CHECK-NEXT:    mov w8, #52429
309; CHECK-NEXT:    mov w9, #39321
310; CHECK-NEXT:    ldr q1, [x10, :lo12:.LCPI10_0]
311; CHECK-NEXT:    movk w8, #52428, lsl #16
312; CHECK-NEXT:    movk w9, #6553, lsl #16
313; CHECK-NEXT:    dup v2.4s, w8
314; CHECK-NEXT:    dup v3.4s, w9
315; CHECK-NEXT:    mla v3.4s, v0.4s, v2.4s
316; CHECK-NEXT:    cmhs v0.4s, v1.4s, v3.4s
317; CHECK-NEXT:    movi v1.4s, #1
318; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
319; CHECK-NEXT:    ret
320  %srem = srem <4 x i32> %X, <i32 5, i32 5, i32 1, i32 5>
321  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
322  %ret = zext <4 x i1> %cmp to <4 x i32>
323  ret <4 x i32> %ret
324}
325
326; One one divisor in even divisor
327define <4 x i32> @test_srem_even_one(<4 x i32> %X) nounwind {
328; CHECK-LABEL: test_srem_even_one:
329; CHECK:       // %bb.0:
330; CHECK-NEXT:    adrp x8, .LCPI11_0
331; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI11_0]
332; CHECK-NEXT:    adrp x8, .LCPI11_1
333; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI11_1]
334; CHECK-NEXT:    adrp x8, .LCPI11_2
335; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI11_2]
336; CHECK-NEXT:    smull2 v4.2d, v0.4s, v1.4s
337; CHECK-NEXT:    smull v1.2d, v0.2s, v1.2s
338; CHECK-NEXT:    adrp x8, .LCPI11_3
339; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
340; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI11_3]
341; CHECK-NEXT:    neg v2.4s, v2.4s
342; CHECK-NEXT:    add v1.4s, v1.4s, v0.4s
343; CHECK-NEXT:    sshl v2.4s, v1.4s, v2.4s
344; CHECK-NEXT:    ushr v1.4s, v1.4s, #31
345; CHECK-NEXT:    and v1.16b, v1.16b, v3.16b
346; CHECK-NEXT:    add v1.4s, v2.4s, v1.4s
347; CHECK-NEXT:    mls v0.4s, v1.4s, v4.4s
348; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
349; CHECK-NEXT:    movi v1.4s, #1
350; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
351; CHECK-NEXT:    ret
352  %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 1, i32 14>
353  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
354  %ret = zext <4 x i1> %cmp to <4 x i32>
355  ret <4 x i32> %ret
356}
357
358; One one divisor in odd+even divisor
359define <4 x i32> @test_srem_odd_even_one(<4 x i32> %X) nounwind {
360; CHECK-LABEL: test_srem_odd_even_one:
361; CHECK:       // %bb.0:
362; CHECK-NEXT:    adrp x8, .LCPI12_0
363; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI12_0]
364; CHECK-NEXT:    adrp x8, .LCPI12_1
365; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI12_1]
366; CHECK-NEXT:    adrp x8, .LCPI12_2
367; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI12_2]
368; CHECK-NEXT:    adrp x8, .LCPI12_3
369; CHECK-NEXT:    smull2 v4.2d, v0.4s, v1.4s
370; CHECK-NEXT:    smull v1.2d, v0.2s, v1.2s
371; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
372; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI12_3]
373; CHECK-NEXT:    adrp x8, .LCPI12_4
374; CHECK-NEXT:    mla v1.4s, v0.4s, v2.4s
375; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI12_4]
376; CHECK-NEXT:    neg v3.4s, v3.4s
377; CHECK-NEXT:    sshl v3.4s, v1.4s, v3.4s
378; CHECK-NEXT:    ushr v1.4s, v1.4s, #31
379; CHECK-NEXT:    and v1.16b, v1.16b, v4.16b
380; CHECK-NEXT:    add v1.4s, v3.4s, v1.4s
381; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
382; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
383; CHECK-NEXT:    movi v1.4s, #1
384; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
385; CHECK-NEXT:    ret
386  %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 1, i32 100>
387  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
388  %ret = zext <4 x i1> %cmp to <4 x i32>
389  ret <4 x i32> %ret
390}
391
392;------------------------------------------------------------------------------;
393
394; One INT_MIN divisor in odd divisor
395define <4 x i32> @test_srem_odd_INT_MIN(<4 x i32> %X) nounwind {
396; CHECK-LABEL: test_srem_odd_INT_MIN:
397; CHECK:       // %bb.0:
398; CHECK-NEXT:    adrp x8, .LCPI13_0
399; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI13_0]
400; CHECK-NEXT:    adrp x8, .LCPI13_1
401; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI13_1]
402; CHECK-NEXT:    adrp x8, .LCPI13_2
403; CHECK-NEXT:    smull2 v3.2d, v0.4s, v1.4s
404; CHECK-NEXT:    smull v1.2d, v0.2s, v1.2s
405; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v3.4s
406; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI13_2]
407; CHECK-NEXT:    adrp x8, .LCPI13_3
408; CHECK-NEXT:    mla v1.4s, v0.4s, v2.4s
409; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI13_3]
410; CHECK-NEXT:    neg v3.4s, v3.4s
411; CHECK-NEXT:    sshl v3.4s, v1.4s, v3.4s
412; CHECK-NEXT:    usra v3.4s, v1.4s, #31
413; CHECK-NEXT:    mls v0.4s, v3.4s, v2.4s
414; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
415; CHECK-NEXT:    movi v1.4s, #1
416; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
417; CHECK-NEXT:    ret
418  %srem = srem <4 x i32> %X, <i32 5, i32 5, i32 2147483648, i32 5>
419  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
420  %ret = zext <4 x i1> %cmp to <4 x i32>
421  ret <4 x i32> %ret
422}
423
424; One INT_MIN divisor in even divisor
425define <4 x i32> @test_srem_even_INT_MIN(<4 x i32> %X) nounwind {
426; CHECK-LABEL: test_srem_even_INT_MIN:
427; CHECK:       // %bb.0:
428; CHECK-NEXT:    adrp x8, .LCPI14_0
429; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI14_0]
430; CHECK-NEXT:    adrp x8, .LCPI14_1
431; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI14_1]
432; CHECK-NEXT:    adrp x8, .LCPI14_2
433; CHECK-NEXT:    smull2 v3.2d, v0.4s, v1.4s
434; CHECK-NEXT:    smull v1.2d, v0.2s, v1.2s
435; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v3.4s
436; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI14_2]
437; CHECK-NEXT:    adrp x8, .LCPI14_3
438; CHECK-NEXT:    mla v1.4s, v0.4s, v2.4s
439; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI14_3]
440; CHECK-NEXT:    neg v3.4s, v3.4s
441; CHECK-NEXT:    sshl v3.4s, v1.4s, v3.4s
442; CHECK-NEXT:    usra v3.4s, v1.4s, #31
443; CHECK-NEXT:    mls v0.4s, v3.4s, v2.4s
444; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
445; CHECK-NEXT:    movi v1.4s, #1
446; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
447; CHECK-NEXT:    ret
448  %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 2147483648, i32 14>
449  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
450  %ret = zext <4 x i1> %cmp to <4 x i32>
451  ret <4 x i32> %ret
452}
453
454; One INT_MIN divisor in odd+even divisor
455define <4 x i32> @test_srem_odd_even_INT_MIN(<4 x i32> %X) nounwind {
456; CHECK-LABEL: test_srem_odd_even_INT_MIN:
457; CHECK:       // %bb.0:
458; CHECK-NEXT:    adrp x8, .LCPI15_0
459; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI15_0]
460; CHECK-NEXT:    adrp x8, .LCPI15_1
461; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI15_1]
462; CHECK-NEXT:    adrp x8, .LCPI15_2
463; CHECK-NEXT:    smull2 v3.2d, v0.4s, v1.4s
464; CHECK-NEXT:    smull v1.2d, v0.2s, v1.2s
465; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v3.4s
466; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI15_2]
467; CHECK-NEXT:    adrp x8, .LCPI15_3
468; CHECK-NEXT:    mla v1.4s, v0.4s, v2.4s
469; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI15_3]
470; CHECK-NEXT:    neg v3.4s, v3.4s
471; CHECK-NEXT:    sshl v3.4s, v1.4s, v3.4s
472; CHECK-NEXT:    usra v3.4s, v1.4s, #31
473; CHECK-NEXT:    mls v0.4s, v3.4s, v2.4s
474; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
475; CHECK-NEXT:    movi v1.4s, #1
476; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
477; CHECK-NEXT:    ret
478  %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 2147483648, i32 100>
479  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
480  %ret = zext <4 x i1> %cmp to <4 x i32>
481  ret <4 x i32> %ret
482}
483
484;==============================================================================;
485
486; One all-ones divisor and power-of-two divisor divisor in odd divisor
487define <4 x i32> @test_srem_odd_allones_and_poweroftwo(<4 x i32> %X) nounwind {
488; CHECK-LABEL: test_srem_odd_allones_and_poweroftwo:
489; CHECK:       // %bb.0:
490; CHECK-NEXT:    adrp x8, .LCPI16_0
491; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI16_0]
492; CHECK-NEXT:    adrp x8, .LCPI16_1
493; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI16_1]
494; CHECK-NEXT:    adrp x8, .LCPI16_2
495; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI16_2]
496; CHECK-NEXT:    adrp x8, .LCPI16_3
497; CHECK-NEXT:    smull2 v4.2d, v0.4s, v1.4s
498; CHECK-NEXT:    smull v1.2d, v0.2s, v1.2s
499; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
500; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI16_3]
501; CHECK-NEXT:    adrp x8, .LCPI16_4
502; CHECK-NEXT:    mla v1.4s, v0.4s, v2.4s
503; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI16_4]
504; CHECK-NEXT:    neg v3.4s, v3.4s
505; CHECK-NEXT:    sshl v3.4s, v1.4s, v3.4s
506; CHECK-NEXT:    ushr v1.4s, v1.4s, #31
507; CHECK-NEXT:    and v1.16b, v1.16b, v4.16b
508; CHECK-NEXT:    add v1.4s, v3.4s, v1.4s
509; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
510; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
511; CHECK-NEXT:    movi v1.4s, #1
512; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
513; CHECK-NEXT:    ret
514  %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 5>
515  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
516  %ret = zext <4 x i1> %cmp to <4 x i32>
517  ret <4 x i32> %ret
518}
519
520; One all-ones divisor and power-of-two divisor divisor in even divisor
521define <4 x i32> @test_srem_even_allones_and_poweroftwo(<4 x i32> %X) nounwind {
522; CHECK-LABEL: test_srem_even_allones_and_poweroftwo:
523; CHECK:       // %bb.0:
524; CHECK-NEXT:    adrp x8, .LCPI17_0
525; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI17_0]
526; CHECK-NEXT:    adrp x8, .LCPI17_1
527; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI17_1]
528; CHECK-NEXT:    adrp x8, .LCPI17_2
529; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI17_2]
530; CHECK-NEXT:    adrp x8, .LCPI17_3
531; CHECK-NEXT:    smull2 v4.2d, v0.4s, v1.4s
532; CHECK-NEXT:    smull v1.2d, v0.2s, v1.2s
533; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
534; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI17_3]
535; CHECK-NEXT:    adrp x8, .LCPI17_4
536; CHECK-NEXT:    mla v1.4s, v0.4s, v2.4s
537; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI17_4]
538; CHECK-NEXT:    neg v3.4s, v3.4s
539; CHECK-NEXT:    sshl v3.4s, v1.4s, v3.4s
540; CHECK-NEXT:    ushr v1.4s, v1.4s, #31
541; CHECK-NEXT:    and v1.16b, v1.16b, v4.16b
542; CHECK-NEXT:    add v1.4s, v3.4s, v1.4s
543; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
544; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
545; CHECK-NEXT:    movi v1.4s, #1
546; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
547; CHECK-NEXT:    ret
548  %srem = srem <4 x i32> %X, <i32 14, i32 4294967295, i32 16, i32 14>
549  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
550  %ret = zext <4 x i1> %cmp to <4 x i32>
551  ret <4 x i32> %ret
552}
553
554; One all-ones divisor and power-of-two divisor divisor in odd+even divisor
555define <4 x i32> @test_srem_odd_even_allones_and_poweroftwo(<4 x i32> %X) nounwind {
556; CHECK-LABEL: test_srem_odd_even_allones_and_poweroftwo:
557; CHECK:       // %bb.0:
558; CHECK-NEXT:    adrp x8, .LCPI18_0
559; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI18_0]
560; CHECK-NEXT:    adrp x8, .LCPI18_1
561; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI18_1]
562; CHECK-NEXT:    adrp x8, .LCPI18_2
563; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI18_2]
564; CHECK-NEXT:    adrp x8, .LCPI18_3
565; CHECK-NEXT:    smull2 v4.2d, v0.4s, v1.4s
566; CHECK-NEXT:    smull v1.2d, v0.2s, v1.2s
567; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
568; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI18_3]
569; CHECK-NEXT:    adrp x8, .LCPI18_4
570; CHECK-NEXT:    mla v1.4s, v0.4s, v2.4s
571; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI18_4]
572; CHECK-NEXT:    neg v3.4s, v3.4s
573; CHECK-NEXT:    sshl v3.4s, v1.4s, v3.4s
574; CHECK-NEXT:    ushr v1.4s, v1.4s, #31
575; CHECK-NEXT:    and v1.16b, v1.16b, v4.16b
576; CHECK-NEXT:    add v1.4s, v3.4s, v1.4s
577; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
578; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
579; CHECK-NEXT:    movi v1.4s, #1
580; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
581; CHECK-NEXT:    ret
582  %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 100>
583  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
584  %ret = zext <4 x i1> %cmp to <4 x i32>
585  ret <4 x i32> %ret
586}
587
588;------------------------------------------------------------------------------;
589
590; One all-ones divisor and one one divisor in odd divisor
591define <4 x i32> @test_srem_odd_allones_and_one(<4 x i32> %X) nounwind {
592; CHECK-LABEL: test_srem_odd_allones_and_one:
593; CHECK:       // %bb.0:
594; CHECK-NEXT:    adrp x10, .LCPI19_0
595; CHECK-NEXT:    mov w8, #52429
596; CHECK-NEXT:    mov w9, #39321
597; CHECK-NEXT:    ldr q1, [x10, :lo12:.LCPI19_0]
598; CHECK-NEXT:    movk w8, #52428, lsl #16
599; CHECK-NEXT:    movk w9, #6553, lsl #16
600; CHECK-NEXT:    dup v2.4s, w8
601; CHECK-NEXT:    dup v3.4s, w9
602; CHECK-NEXT:    mla v3.4s, v0.4s, v2.4s
603; CHECK-NEXT:    cmhs v0.4s, v1.4s, v3.4s
604; CHECK-NEXT:    movi v1.4s, #1
605; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
606; CHECK-NEXT:    ret
607  %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 1, i32 5>
608  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
609  %ret = zext <4 x i1> %cmp to <4 x i32>
610  ret <4 x i32> %ret
611}
612
613; One all-ones divisor and one one divisor in even divisor
614define <4 x i32> @test_srem_even_allones_and_one(<4 x i32> %X) nounwind {
615; CHECK-LABEL: test_srem_even_allones_and_one:
616; CHECK:       // %bb.0:
617; CHECK-NEXT:    adrp x8, .LCPI20_0
618; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI20_0]
619; CHECK-NEXT:    adrp x8, .LCPI20_1
620; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI20_1]
621; CHECK-NEXT:    adrp x8, .LCPI20_2
622; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI20_2]
623; CHECK-NEXT:    adrp x8, .LCPI20_3
624; CHECK-NEXT:    smull2 v4.2d, v0.4s, v1.4s
625; CHECK-NEXT:    smull v1.2d, v0.2s, v1.2s
626; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
627; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI20_3]
628; CHECK-NEXT:    adrp x8, .LCPI20_4
629; CHECK-NEXT:    mla v1.4s, v0.4s, v2.4s
630; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI20_4]
631; CHECK-NEXT:    neg v3.4s, v3.4s
632; CHECK-NEXT:    sshl v3.4s, v1.4s, v3.4s
633; CHECK-NEXT:    ushr v1.4s, v1.4s, #31
634; CHECK-NEXT:    and v1.16b, v1.16b, v4.16b
635; CHECK-NEXT:    add v1.4s, v3.4s, v1.4s
636; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
637; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
638; CHECK-NEXT:    movi v1.4s, #1
639; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
640; CHECK-NEXT:    ret
641  %srem = srem <4 x i32> %X, <i32 14, i32 4294967295, i32 1, i32 14>
642  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
643  %ret = zext <4 x i1> %cmp to <4 x i32>
644  ret <4 x i32> %ret
645}
646
647; One all-ones divisor and one one divisor in odd+even divisor
648define <4 x i32> @test_srem_odd_even_allones_and_one(<4 x i32> %X) nounwind {
649; CHECK-LABEL: test_srem_odd_even_allones_and_one:
650; CHECK:       // %bb.0:
651; CHECK-NEXT:    adrp x8, .LCPI21_0
652; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI21_0]
653; CHECK-NEXT:    adrp x8, .LCPI21_1
654; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI21_1]
655; CHECK-NEXT:    adrp x8, .LCPI21_2
656; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI21_2]
657; CHECK-NEXT:    adrp x8, .LCPI21_3
658; CHECK-NEXT:    smull2 v4.2d, v0.4s, v1.4s
659; CHECK-NEXT:    smull v1.2d, v0.2s, v1.2s
660; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
661; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI21_3]
662; CHECK-NEXT:    adrp x8, .LCPI21_4
663; CHECK-NEXT:    mla v1.4s, v0.4s, v2.4s
664; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI21_4]
665; CHECK-NEXT:    neg v3.4s, v3.4s
666; CHECK-NEXT:    sshl v3.4s, v1.4s, v3.4s
667; CHECK-NEXT:    ushr v1.4s, v1.4s, #31
668; CHECK-NEXT:    and v1.16b, v1.16b, v4.16b
669; CHECK-NEXT:    add v1.4s, v3.4s, v1.4s
670; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
671; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
672; CHECK-NEXT:    movi v1.4s, #1
673; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
674; CHECK-NEXT:    ret
675  %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 1, i32 100>
676  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
677  %ret = zext <4 x i1> %cmp to <4 x i32>
678  ret <4 x i32> %ret
679}
680
681;------------------------------------------------------------------------------;
682
683; One power-of-two divisor divisor and one divisor in odd divisor
684define <4 x i32> @test_srem_odd_poweroftwo_and_one(<4 x i32> %X) nounwind {
685; CHECK-LABEL: test_srem_odd_poweroftwo_and_one:
686; CHECK:       // %bb.0:
687; CHECK-NEXT:    adrp x8, .LCPI22_0
688; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI22_0]
689; CHECK-NEXT:    adrp x8, .LCPI22_1
690; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI22_1]
691; CHECK-NEXT:    adrp x8, .LCPI22_2
692; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI22_2]
693; CHECK-NEXT:    adrp x8, .LCPI22_3
694; CHECK-NEXT:    smull2 v4.2d, v0.4s, v1.4s
695; CHECK-NEXT:    smull v1.2d, v0.2s, v1.2s
696; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
697; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI22_3]
698; CHECK-NEXT:    adrp x8, .LCPI22_4
699; CHECK-NEXT:    mla v1.4s, v0.4s, v2.4s
700; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI22_4]
701; CHECK-NEXT:    neg v3.4s, v3.4s
702; CHECK-NEXT:    sshl v3.4s, v1.4s, v3.4s
703; CHECK-NEXT:    ushr v1.4s, v1.4s, #31
704; CHECK-NEXT:    and v1.16b, v1.16b, v4.16b
705; CHECK-NEXT:    add v1.4s, v3.4s, v1.4s
706; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
707; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
708; CHECK-NEXT:    movi v1.4s, #1
709; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
710; CHECK-NEXT:    ret
711  %srem = srem <4 x i32> %X, <i32 5, i32 16, i32 1, i32 5>
712  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
713  %ret = zext <4 x i1> %cmp to <4 x i32>
714  ret <4 x i32> %ret
715}
716
717; One power-of-two divisor divisor and one divisor in even divisor
718define <4 x i32> @test_srem_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
719; CHECK-LABEL: test_srem_even_poweroftwo_and_one:
720; CHECK:       // %bb.0:
721; CHECK-NEXT:    adrp x8, .LCPI23_0
722; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI23_0]
723; CHECK-NEXT:    adrp x8, .LCPI23_1
724; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI23_1]
725; CHECK-NEXT:    adrp x8, .LCPI23_2
726; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI23_2]
727; CHECK-NEXT:    smull2 v4.2d, v0.4s, v1.4s
728; CHECK-NEXT:    smull v1.2d, v0.2s, v1.2s
729; CHECK-NEXT:    adrp x8, .LCPI23_3
730; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
731; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI23_3]
732; CHECK-NEXT:    neg v2.4s, v2.4s
733; CHECK-NEXT:    add v1.4s, v1.4s, v0.4s
734; CHECK-NEXT:    sshl v2.4s, v1.4s, v2.4s
735; CHECK-NEXT:    ushr v1.4s, v1.4s, #31
736; CHECK-NEXT:    and v1.16b, v1.16b, v3.16b
737; CHECK-NEXT:    add v1.4s, v2.4s, v1.4s
738; CHECK-NEXT:    mls v0.4s, v1.4s, v4.4s
739; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
740; CHECK-NEXT:    movi v1.4s, #1
741; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
742; CHECK-NEXT:    ret
743  %srem = srem <4 x i32> %X, <i32 14, i32 16, i32 1, i32 14>
744  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
745  %ret = zext <4 x i1> %cmp to <4 x i32>
746  ret <4 x i32> %ret
747}
748
749; One power-of-two divisor divisor and one divisor in odd+even divisor
750define <4 x i32> @test_srem_odd_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
751; CHECK-LABEL: test_srem_odd_even_poweroftwo_and_one:
752; CHECK:       // %bb.0:
753; CHECK-NEXT:    adrp x8, .LCPI24_0
754; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI24_0]
755; CHECK-NEXT:    adrp x8, .LCPI24_1
756; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI24_1]
757; CHECK-NEXT:    adrp x8, .LCPI24_2
758; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI24_2]
759; CHECK-NEXT:    adrp x8, .LCPI24_3
760; CHECK-NEXT:    smull2 v4.2d, v0.4s, v1.4s
761; CHECK-NEXT:    smull v1.2d, v0.2s, v1.2s
762; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
763; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI24_3]
764; CHECK-NEXT:    adrp x8, .LCPI24_4
765; CHECK-NEXT:    mla v1.4s, v0.4s, v2.4s
766; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI24_4]
767; CHECK-NEXT:    neg v3.4s, v3.4s
768; CHECK-NEXT:    sshl v3.4s, v1.4s, v3.4s
769; CHECK-NEXT:    ushr v1.4s, v1.4s, #31
770; CHECK-NEXT:    and v1.16b, v1.16b, v4.16b
771; CHECK-NEXT:    add v1.4s, v3.4s, v1.4s
772; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
773; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
774; CHECK-NEXT:    movi v1.4s, #1
775; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
776; CHECK-NEXT:    ret
777  %srem = srem <4 x i32> %X, <i32 5, i32 16, i32 1, i32 100>
778  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
779  %ret = zext <4 x i1> %cmp to <4 x i32>
780  ret <4 x i32> %ret
781}
782
783;------------------------------------------------------------------------------;
784
785define <4 x i32> @test_srem_odd_allones_and_poweroftwo_and_one(<4 x i32> %X) nounwind {
786; CHECK-LABEL: test_srem_odd_allones_and_poweroftwo_and_one:
787; CHECK:       // %bb.0:
788; CHECK-NEXT:    adrp x8, .LCPI25_0
789; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI25_0]
790; CHECK-NEXT:    adrp x8, .LCPI25_1
791; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI25_1]
792; CHECK-NEXT:    adrp x8, .LCPI25_2
793; CHECK-NEXT:    smull2 v4.2d, v0.4s, v1.4s
794; CHECK-NEXT:    smull v1.2d, v0.2s, v1.2s
795; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
796; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI25_2]
797; CHECK-NEXT:    adrp x8, .LCPI25_3
798; CHECK-NEXT:    mla v1.4s, v0.4s, v2.4s
799; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI25_3]
800; CHECK-NEXT:    neg v4.4s, v4.4s
801; CHECK-NEXT:    movi v3.2d, #0x000000ffffffff
802; CHECK-NEXT:    sshl v4.4s, v1.4s, v4.4s
803; CHECK-NEXT:    ushr v1.4s, v1.4s, #31
804; CHECK-NEXT:    and v1.16b, v1.16b, v3.16b
805; CHECK-NEXT:    add v1.4s, v4.4s, v1.4s
806; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
807; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
808; CHECK-NEXT:    movi v1.4s, #1
809; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
810; CHECK-NEXT:    ret
811  %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 1>
812  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
813  %ret = zext <4 x i1> %cmp to <4 x i32>
814  ret <4 x i32> %ret
815}
816
817define <4 x i32> @test_srem_even_allones_and_poweroftwo_and_one(<4 x i32> %X) nounwind {
818; CHECK-LABEL: test_srem_even_allones_and_poweroftwo_and_one:
819; CHECK:       // %bb.0:
820; CHECK-NEXT:    adrp x8, .LCPI26_0
821; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI26_0]
822; CHECK-NEXT:    adrp x8, .LCPI26_1
823; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI26_1]
824; CHECK-NEXT:    adrp x8, .LCPI26_2
825; CHECK-NEXT:    smull2 v4.2d, v0.4s, v1.4s
826; CHECK-NEXT:    smull v1.2d, v0.2s, v1.2s
827; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
828; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI26_2]
829; CHECK-NEXT:    adrp x8, .LCPI26_3
830; CHECK-NEXT:    mla v1.4s, v0.4s, v2.4s
831; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI26_3]
832; CHECK-NEXT:    neg v4.4s, v4.4s
833; CHECK-NEXT:    movi v3.2d, #0x000000ffffffff
834; CHECK-NEXT:    sshl v4.4s, v1.4s, v4.4s
835; CHECK-NEXT:    ushr v1.4s, v1.4s, #31
836; CHECK-NEXT:    and v1.16b, v1.16b, v3.16b
837; CHECK-NEXT:    add v1.4s, v4.4s, v1.4s
838; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
839; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
840; CHECK-NEXT:    movi v1.4s, #1
841; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
842; CHECK-NEXT:    ret
843  %srem = srem <4 x i32> %X, <i32 14, i32 4294967295, i32 16, i32 1>
844  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
845  %ret = zext <4 x i1> %cmp to <4 x i32>
846  ret <4 x i32> %ret
847}
848