1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s 3 4declare <1 x i8> @llvm.ssub.sat.v1i8(<1 x i8>, <1 x i8>) 5declare <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8>, <2 x i8>) 6declare <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8>, <4 x i8>) 7declare <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8>, <8 x i8>) 8declare <12 x i8> @llvm.ssub.sat.v12i8(<12 x i8>, <12 x i8>) 9declare <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8>, <16 x i8>) 10declare <32 x i8> @llvm.ssub.sat.v32i8(<32 x i8>, <32 x i8>) 11declare <64 x i8> @llvm.ssub.sat.v64i8(<64 x i8>, <64 x i8>) 12 13declare <1 x i16> @llvm.ssub.sat.v1i16(<1 x i16>, <1 x i16>) 14declare <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16>, <2 x i16>) 15declare <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16>, <4 x i16>) 16declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>) 17declare <12 x i16> @llvm.ssub.sat.v12i16(<12 x i16>, <12 x i16>) 18declare <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16>, <16 x i16>) 19declare <32 x i16> @llvm.ssub.sat.v32i16(<32 x i16>, <32 x i16>) 20 21declare <16 x i1> @llvm.ssub.sat.v16i1(<16 x i1>, <16 x i1>) 22declare <16 x i4> @llvm.ssub.sat.v16i4(<16 x i4>, <16 x i4>) 23 24declare <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32>, <2 x i32>) 25declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>) 26declare <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32>, <8 x i32>) 27declare <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32>, <16 x i32>) 28declare <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64>, <2 x i64>) 29declare <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64>, <4 x i64>) 30declare <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64>, <8 x i64>) 31 32declare <4 x i24> @llvm.ssub.sat.v4i24(<4 x i24>, <4 x i24>) 33declare <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128>, <2 x i128>) 34 35 36define <16 x i8> @v16i8(<16 x i8> %x, <16 x i8> %y) nounwind { 37; CHECK-LABEL: v16i8: 38; CHECK: // %bb.0: 39; CHECK-NEXT: sqsub v0.16b, v0.16b, v1.16b 40; CHECK-NEXT: ret 41 %z = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %x, <16 x i8> %y) 42 ret <16 x i8> %z 43} 44 45define <32 x i8> @v32i8(<32 x i8> %x, <32 x i8> %y) nounwind { 46; CHECK-LABEL: v32i8: 47; CHECK: // %bb.0: 48; CHECK-NEXT: sqsub v0.16b, v0.16b, v2.16b 49; CHECK-NEXT: sqsub v1.16b, v1.16b, v3.16b 50; CHECK-NEXT: ret 51 %z = call <32 x i8> @llvm.ssub.sat.v32i8(<32 x i8> %x, <32 x i8> %y) 52 ret <32 x i8> %z 53} 54 55define <64 x i8> @v64i8(<64 x i8> %x, <64 x i8> %y) nounwind { 56; CHECK-LABEL: v64i8: 57; CHECK: // %bb.0: 58; CHECK-NEXT: sqsub v0.16b, v0.16b, v4.16b 59; CHECK-NEXT: sqsub v1.16b, v1.16b, v5.16b 60; CHECK-NEXT: sqsub v2.16b, v2.16b, v6.16b 61; CHECK-NEXT: sqsub v3.16b, v3.16b, v7.16b 62; CHECK-NEXT: ret 63 %z = call <64 x i8> @llvm.ssub.sat.v64i8(<64 x i8> %x, <64 x i8> %y) 64 ret <64 x i8> %z 65} 66 67define <8 x i16> @v8i16(<8 x i16> %x, <8 x i16> %y) nounwind { 68; CHECK-LABEL: v8i16: 69; CHECK: // %bb.0: 70; CHECK-NEXT: sqsub v0.8h, v0.8h, v1.8h 71; CHECK-NEXT: ret 72 %z = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %x, <8 x i16> %y) 73 ret <8 x i16> %z 74} 75 76define <16 x i16> @v16i16(<16 x i16> %x, <16 x i16> %y) nounwind { 77; CHECK-LABEL: v16i16: 78; CHECK: // %bb.0: 79; CHECK-NEXT: sqsub v0.8h, v0.8h, v2.8h 80; CHECK-NEXT: sqsub v1.8h, v1.8h, v3.8h 81; CHECK-NEXT: ret 82 %z = call <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16> %x, <16 x i16> %y) 83 ret <16 x i16> %z 84} 85 86define <32 x i16> @v32i16(<32 x i16> %x, <32 x i16> %y) nounwind { 87; CHECK-LABEL: v32i16: 88; CHECK: // %bb.0: 89; CHECK-NEXT: sqsub v0.8h, v0.8h, v4.8h 90; CHECK-NEXT: sqsub v1.8h, v1.8h, v5.8h 91; CHECK-NEXT: sqsub v2.8h, v2.8h, v6.8h 92; CHECK-NEXT: sqsub v3.8h, v3.8h, v7.8h 93; CHECK-NEXT: ret 94 %z = call <32 x i16> @llvm.ssub.sat.v32i16(<32 x i16> %x, <32 x i16> %y) 95 ret <32 x i16> %z 96} 97 98define void @v8i8(<8 x i8>* %px, <8 x i8>* %py, <8 x i8>* %pz) nounwind { 99; CHECK-LABEL: v8i8: 100; CHECK: // %bb.0: 101; CHECK-NEXT: ldr d0, [x0] 102; CHECK-NEXT: ldr d1, [x1] 103; CHECK-NEXT: sqsub v0.8b, v0.8b, v1.8b 104; CHECK-NEXT: str d0, [x2] 105; CHECK-NEXT: ret 106 %x = load <8 x i8>, <8 x i8>* %px 107 %y = load <8 x i8>, <8 x i8>* %py 108 %z = call <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8> %x, <8 x i8> %y) 109 store <8 x i8> %z, <8 x i8>* %pz 110 ret void 111} 112 113define void @v4i8(<4 x i8>* %px, <4 x i8>* %py, <4 x i8>* %pz) nounwind { 114; CHECK-LABEL: v4i8: 115; CHECK: // %bb.0: 116; CHECK-NEXT: ldrsb w8, [x0] 117; CHECK-NEXT: ldrsb w9, [x1] 118; CHECK-NEXT: ldrsb w10, [x0, #1] 119; CHECK-NEXT: ldrsb w11, [x1, #1] 120; CHECK-NEXT: fmov s0, w8 121; CHECK-NEXT: fmov s1, w9 122; CHECK-NEXT: ldrsb w8, [x0, #2] 123; CHECK-NEXT: ldrsb w9, [x1, #2] 124; CHECK-NEXT: mov v0.h[1], w10 125; CHECK-NEXT: mov v1.h[1], w11 126; CHECK-NEXT: ldrsb w10, [x0, #3] 127; CHECK-NEXT: ldrsb w11, [x1, #3] 128; CHECK-NEXT: mov v0.h[2], w8 129; CHECK-NEXT: mov v1.h[2], w9 130; CHECK-NEXT: mov v0.h[3], w10 131; CHECK-NEXT: mov v1.h[3], w11 132; CHECK-NEXT: shl v1.4h, v1.4h, #8 133; CHECK-NEXT: shl v0.4h, v0.4h, #8 134; CHECK-NEXT: sqsub v0.4h, v0.4h, v1.4h 135; CHECK-NEXT: sshr v0.4h, v0.4h, #8 136; CHECK-NEXT: xtn v0.8b, v0.8h 137; CHECK-NEXT: str s0, [x2] 138; CHECK-NEXT: ret 139 %x = load <4 x i8>, <4 x i8>* %px 140 %y = load <4 x i8>, <4 x i8>* %py 141 %z = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> %x, <4 x i8> %y) 142 store <4 x i8> %z, <4 x i8>* %pz 143 ret void 144} 145 146define void @v2i8(<2 x i8>* %px, <2 x i8>* %py, <2 x i8>* %pz) nounwind { 147; CHECK-LABEL: v2i8: 148; CHECK: // %bb.0: 149; CHECK-NEXT: ldrb w8, [x0] 150; CHECK-NEXT: ldrb w9, [x1] 151; CHECK-NEXT: ldrb w10, [x0, #1] 152; CHECK-NEXT: ldrb w11, [x1, #1] 153; CHECK-NEXT: fmov s0, w8 154; CHECK-NEXT: fmov s1, w9 155; CHECK-NEXT: mov v0.s[1], w10 156; CHECK-NEXT: mov v1.s[1], w11 157; CHECK-NEXT: shl v1.2s, v1.2s, #24 158; CHECK-NEXT: shl v0.2s, v0.2s, #24 159; CHECK-NEXT: sqsub v0.2s, v0.2s, v1.2s 160; CHECK-NEXT: ushr v0.2s, v0.2s, #24 161; CHECK-NEXT: mov w8, v0.s[1] 162; CHECK-NEXT: fmov w9, s0 163; CHECK-NEXT: strb w8, [x2, #1] 164; CHECK-NEXT: strb w9, [x2] 165; CHECK-NEXT: ret 166 %x = load <2 x i8>, <2 x i8>* %px 167 %y = load <2 x i8>, <2 x i8>* %py 168 %z = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %x, <2 x i8> %y) 169 store <2 x i8> %z, <2 x i8>* %pz 170 ret void 171} 172 173define void @v4i16(<4 x i16>* %px, <4 x i16>* %py, <4 x i16>* %pz) nounwind { 174; CHECK-LABEL: v4i16: 175; CHECK: // %bb.0: 176; CHECK-NEXT: ldr d0, [x0] 177; CHECK-NEXT: ldr d1, [x1] 178; CHECK-NEXT: sqsub v0.4h, v0.4h, v1.4h 179; CHECK-NEXT: str d0, [x2] 180; CHECK-NEXT: ret 181 %x = load <4 x i16>, <4 x i16>* %px 182 %y = load <4 x i16>, <4 x i16>* %py 183 %z = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %x, <4 x i16> %y) 184 store <4 x i16> %z, <4 x i16>* %pz 185 ret void 186} 187 188define void @v2i16(<2 x i16>* %px, <2 x i16>* %py, <2 x i16>* %pz) nounwind { 189; CHECK-LABEL: v2i16: 190; CHECK: // %bb.0: 191; CHECK-NEXT: ldrh w8, [x0] 192; CHECK-NEXT: ldrh w9, [x1] 193; CHECK-NEXT: ldrh w10, [x0, #2] 194; CHECK-NEXT: ldrh w11, [x1, #2] 195; CHECK-NEXT: fmov s0, w8 196; CHECK-NEXT: fmov s1, w9 197; CHECK-NEXT: mov v0.s[1], w10 198; CHECK-NEXT: mov v1.s[1], w11 199; CHECK-NEXT: shl v1.2s, v1.2s, #16 200; CHECK-NEXT: shl v0.2s, v0.2s, #16 201; CHECK-NEXT: sqsub v0.2s, v0.2s, v1.2s 202; CHECK-NEXT: ushr v0.2s, v0.2s, #16 203; CHECK-NEXT: mov w8, v0.s[1] 204; CHECK-NEXT: fmov w9, s0 205; CHECK-NEXT: strh w8, [x2, #2] 206; CHECK-NEXT: strh w9, [x2] 207; CHECK-NEXT: ret 208 %x = load <2 x i16>, <2 x i16>* %px 209 %y = load <2 x i16>, <2 x i16>* %py 210 %z = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %x, <2 x i16> %y) 211 store <2 x i16> %z, <2 x i16>* %pz 212 ret void 213} 214 215define <12 x i8> @v12i8(<12 x i8> %x, <12 x i8> %y) nounwind { 216; CHECK-LABEL: v12i8: 217; CHECK: // %bb.0: 218; CHECK-NEXT: sqsub v0.16b, v0.16b, v1.16b 219; CHECK-NEXT: ret 220 %z = call <12 x i8> @llvm.ssub.sat.v12i8(<12 x i8> %x, <12 x i8> %y) 221 ret <12 x i8> %z 222} 223 224define void @v12i16(<12 x i16>* %px, <12 x i16>* %py, <12 x i16>* %pz) nounwind { 225; CHECK-LABEL: v12i16: 226; CHECK: // %bb.0: 227; CHECK-NEXT: ldp q0, q1, [x0] 228; CHECK-NEXT: ldp q3, q2, [x1] 229; CHECK-NEXT: sqsub v1.8h, v1.8h, v2.8h 230; CHECK-NEXT: sqsub v0.8h, v0.8h, v3.8h 231; CHECK-NEXT: str q0, [x2] 232; CHECK-NEXT: str d1, [x2, #16] 233; CHECK-NEXT: ret 234 %x = load <12 x i16>, <12 x i16>* %px 235 %y = load <12 x i16>, <12 x i16>* %py 236 %z = call <12 x i16> @llvm.ssub.sat.v12i16(<12 x i16> %x, <12 x i16> %y) 237 store <12 x i16> %z, <12 x i16>* %pz 238 ret void 239} 240 241define void @v1i8(<1 x i8>* %px, <1 x i8>* %py, <1 x i8>* %pz) nounwind { 242; CHECK-LABEL: v1i8: 243; CHECK: // %bb.0: 244; CHECK-NEXT: ldr b0, [x0] 245; CHECK-NEXT: ldr b1, [x1] 246; CHECK-NEXT: sqsub v0.8b, v0.8b, v1.8b 247; CHECK-NEXT: st1 { v0.b }[0], [x2] 248; CHECK-NEXT: ret 249 %x = load <1 x i8>, <1 x i8>* %px 250 %y = load <1 x i8>, <1 x i8>* %py 251 %z = call <1 x i8> @llvm.ssub.sat.v1i8(<1 x i8> %x, <1 x i8> %y) 252 store <1 x i8> %z, <1 x i8>* %pz 253 ret void 254} 255 256define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind { 257; CHECK-LABEL: v1i16: 258; CHECK: // %bb.0: 259; CHECK-NEXT: ldr h0, [x0] 260; CHECK-NEXT: ldr h1, [x1] 261; CHECK-NEXT: sqsub v0.4h, v0.4h, v1.4h 262; CHECK-NEXT: str h0, [x2] 263; CHECK-NEXT: ret 264 %x = load <1 x i16>, <1 x i16>* %px 265 %y = load <1 x i16>, <1 x i16>* %py 266 %z = call <1 x i16> @llvm.ssub.sat.v1i16(<1 x i16> %x, <1 x i16> %y) 267 store <1 x i16> %z, <1 x i16>* %pz 268 ret void 269} 270 271define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind { 272; CHECK-LABEL: v16i4: 273; CHECK: // %bb.0: 274; CHECK-NEXT: shl v0.16b, v0.16b, #4 275; CHECK-NEXT: shl v1.16b, v1.16b, #4 276; CHECK-NEXT: sshr v0.16b, v0.16b, #4 277; CHECK-NEXT: sshr v1.16b, v1.16b, #4 278; CHECK-NEXT: shl v1.16b, v1.16b, #4 279; CHECK-NEXT: shl v0.16b, v0.16b, #4 280; CHECK-NEXT: sqsub v0.16b, v0.16b, v1.16b 281; CHECK-NEXT: sshr v0.16b, v0.16b, #4 282; CHECK-NEXT: ret 283 %z = call <16 x i4> @llvm.ssub.sat.v16i4(<16 x i4> %x, <16 x i4> %y) 284 ret <16 x i4> %z 285} 286 287define <16 x i1> @v16i1(<16 x i1> %x, <16 x i1> %y) nounwind { 288; CHECK-LABEL: v16i1: 289; CHECK: // %bb.0: 290; CHECK-NEXT: shl v0.16b, v0.16b, #7 291; CHECK-NEXT: shl v1.16b, v1.16b, #7 292; CHECK-NEXT: sshr v0.16b, v0.16b, #7 293; CHECK-NEXT: sshr v1.16b, v1.16b, #7 294; CHECK-NEXT: shl v1.16b, v1.16b, #7 295; CHECK-NEXT: shl v0.16b, v0.16b, #7 296; CHECK-NEXT: sqsub v0.16b, v0.16b, v1.16b 297; CHECK-NEXT: sshr v0.16b, v0.16b, #7 298; CHECK-NEXT: ret 299 %z = call <16 x i1> @llvm.ssub.sat.v16i1(<16 x i1> %x, <16 x i1> %y) 300 ret <16 x i1> %z 301} 302 303define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind { 304; CHECK-LABEL: v2i32: 305; CHECK: // %bb.0: 306; CHECK-NEXT: sqsub v0.2s, v0.2s, v1.2s 307; CHECK-NEXT: ret 308 %z = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %x, <2 x i32> %y) 309 ret <2 x i32> %z 310} 311 312define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind { 313; CHECK-LABEL: v4i32: 314; CHECK: // %bb.0: 315; CHECK-NEXT: sqsub v0.4s, v0.4s, v1.4s 316; CHECK-NEXT: ret 317 %z = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %y) 318 ret <4 x i32> %z 319} 320 321define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind { 322; CHECK-LABEL: v8i32: 323; CHECK: // %bb.0: 324; CHECK-NEXT: sqsub v0.4s, v0.4s, v2.4s 325; CHECK-NEXT: sqsub v1.4s, v1.4s, v3.4s 326; CHECK-NEXT: ret 327 %z = call <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32> %x, <8 x i32> %y) 328 ret <8 x i32> %z 329} 330 331define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind { 332; CHECK-LABEL: v16i32: 333; CHECK: // %bb.0: 334; CHECK-NEXT: sqsub v0.4s, v0.4s, v4.4s 335; CHECK-NEXT: sqsub v1.4s, v1.4s, v5.4s 336; CHECK-NEXT: sqsub v2.4s, v2.4s, v6.4s 337; CHECK-NEXT: sqsub v3.4s, v3.4s, v7.4s 338; CHECK-NEXT: ret 339 %z = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %x, <16 x i32> %y) 340 ret <16 x i32> %z 341} 342 343define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind { 344; CHECK-LABEL: v2i64: 345; CHECK: // %bb.0: 346; CHECK-NEXT: sqsub v0.2d, v0.2d, v1.2d 347; CHECK-NEXT: ret 348 %z = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %x, <2 x i64> %y) 349 ret <2 x i64> %z 350} 351 352define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind { 353; CHECK-LABEL: v4i64: 354; CHECK: // %bb.0: 355; CHECK-NEXT: sqsub v0.2d, v0.2d, v2.2d 356; CHECK-NEXT: sqsub v1.2d, v1.2d, v3.2d 357; CHECK-NEXT: ret 358 %z = call <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64> %x, <4 x i64> %y) 359 ret <4 x i64> %z 360} 361 362define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind { 363; CHECK-LABEL: v8i64: 364; CHECK: // %bb.0: 365; CHECK-NEXT: sqsub v0.2d, v0.2d, v4.2d 366; CHECK-NEXT: sqsub v1.2d, v1.2d, v5.2d 367; CHECK-NEXT: sqsub v2.2d, v2.2d, v6.2d 368; CHECK-NEXT: sqsub v3.2d, v3.2d, v7.2d 369; CHECK-NEXT: ret 370 %z = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> %x, <8 x i64> %y) 371 ret <8 x i64> %z 372} 373 374define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind { 375; CHECK-LABEL: v2i128: 376; CHECK: // %bb.0: 377; CHECK-NEXT: cmp x7, #0 // =0 378; CHECK-NEXT: cset w9, ge 379; CHECK-NEXT: csinc w9, w9, wzr, ne 380; CHECK-NEXT: cmp x3, #0 // =0 381; CHECK-NEXT: cset w10, ge 382; CHECK-NEXT: csinc w10, w10, wzr, ne 383; CHECK-NEXT: cmp w10, w9 384; CHECK-NEXT: cset w9, ne 385; CHECK-NEXT: subs x11, x2, x6 386; CHECK-NEXT: sbcs x12, x3, x7 387; CHECK-NEXT: cmp x12, #0 // =0 388; CHECK-NEXT: cset w13, ge 389; CHECK-NEXT: mov x8, #9223372036854775807 390; CHECK-NEXT: csinc w13, w13, wzr, ne 391; CHECK-NEXT: cinv x14, x8, ge 392; CHECK-NEXT: cmp w10, w13 393; CHECK-NEXT: cset w13, ne 394; CHECK-NEXT: asr x10, x12, #63 395; CHECK-NEXT: tst w9, w13 396; CHECK-NEXT: csel x3, x14, x12, ne 397; CHECK-NEXT: csel x2, x10, x11, ne 398; CHECK-NEXT: cmp x5, #0 // =0 399; CHECK-NEXT: cset w9, ge 400; CHECK-NEXT: csinc w9, w9, wzr, ne 401; CHECK-NEXT: cmp x1, #0 // =0 402; CHECK-NEXT: cset w10, ge 403; CHECK-NEXT: csinc w10, w10, wzr, ne 404; CHECK-NEXT: cmp w10, w9 405; CHECK-NEXT: cset w9, ne 406; CHECK-NEXT: subs x11, x0, x4 407; CHECK-NEXT: sbcs x12, x1, x5 408; CHECK-NEXT: cmp x12, #0 // =0 409; CHECK-NEXT: cset w13, ge 410; CHECK-NEXT: csinc w13, w13, wzr, ne 411; CHECK-NEXT: cinv x8, x8, ge 412; CHECK-NEXT: cmp w10, w13 413; CHECK-NEXT: cset w10, ne 414; CHECK-NEXT: tst w9, w10 415; CHECK-NEXT: asr x9, x12, #63 416; CHECK-NEXT: csel x9, x9, x11, ne 417; CHECK-NEXT: csel x1, x8, x12, ne 418; CHECK-NEXT: fmov d0, x9 419; CHECK-NEXT: mov v0.d[1], x1 420; CHECK-NEXT: fmov x0, d0 421; CHECK-NEXT: ret 422 %z = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %x, <2 x i128> %y) 423 ret <2 x i128> %z 424} 425