1; RUN: llc -aarch64-sve-vector-bits-min=128 -asm-verbose=0 < %s | FileCheck %s -check-prefix=NO_SVE 2; RUN: llc -aarch64-sve-vector-bits-min=256 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK 3; RUN: llc -aarch64-sve-vector-bits-min=384 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK 4; RUN: llc -aarch64-sve-vector-bits-min=512 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512 5; RUN: llc -aarch64-sve-vector-bits-min=640 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512 6; RUN: llc -aarch64-sve-vector-bits-min=768 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512 7; RUN: llc -aarch64-sve-vector-bits-min=896 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512 8; RUN: llc -aarch64-sve-vector-bits-min=1024 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 9; RUN: llc -aarch64-sve-vector-bits-min=1152 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 10; RUN: llc -aarch64-sve-vector-bits-min=1280 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 11; RUN: llc -aarch64-sve-vector-bits-min=1408 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 12; RUN: llc -aarch64-sve-vector-bits-min=1536 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 13; RUN: llc -aarch64-sve-vector-bits-min=1664 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 14; RUN: llc -aarch64-sve-vector-bits-min=1792 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 15; RUN: llc -aarch64-sve-vector-bits-min=1920 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 16; RUN: llc -aarch64-sve-vector-bits-min=2048 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024,VBITS_GE_2048 17 18target triple = "aarch64-unknown-linux-gnu" 19 20; Don't use SVE when its registers are no bigger than NEON. 21; NO_SVE-NOT: z{0-9} 22 23; NOTE: fptrunc operations bigger than NEON are expanded. These tests just 24; ensure we've correctly set the operation action for fixed length vector types 25; that require SVE. They'll be updated to protect their expected code generation 26; when lowering it implemented. 27 28; 29; fptrunc f32 -> f16 30; 31 32define <8 x half> @fptrunc_v8f32_v8f16(<8 x float>* %in) #0 { 33; CHECK-LABEL: fptrunc_v8f32_v8f16: 34; CHECK-COUNT-8: fcvt h{{[0-9]}}, s{{[0-9]}} 35; CHECK-NOT: fcvt 36; CHECK: ret 37 %a = load <8 x float>, <8 x float>* %in 38 %b = fptrunc <8 x float> %a to <8 x half> 39 ret <8 x half> %b 40} 41 42define void @fptrunc_v16f32_v16f16(<16 x float>* %in, <16 x half>* %out) #0 { 43; CHECK-LABEL: fptrunc_v16f32_v16f16: 44; CHECK-COUNT-16: fcvt h{{[0-9]}}, s{{[0-9]}} 45; CHECK-NOT: fcvt 46; CHECK: ret 47 %a = load <16 x float>, <16 x float>* %in 48 %b = fptrunc <16 x float> %a to <16 x half> 49 store <16 x half> %b, <16 x half>* %out 50 ret void 51} 52 53define void @fptrunc_v32f32_v32f16(<32 x float>* %in, <32 x half>* %out) #0 { 54; CHECK-LABEL: fptrunc_v32f32_v32f16: 55; CHECK-COUNT-32: fcvt h{{[0-9]}}, s{{[0-9]}} 56; CHECK-NOT: fcvt 57; CHECK: ret 58 %a = load <32 x float>, <32 x float>* %in 59 %b = fptrunc <32 x float> %a to <32 x half> 60 store <32 x half> %b, <32 x half>* %out 61 ret void 62} 63 64define void @fptrunc_v64f32_v64f16(<64 x float>* %in, <64 x half>* %out) #0 { 65; CHECK-LABEL: fptrunc_v64f32_v64f16: 66; CHECK-COUNT-64: fcvt h{{[0-9]}}, s{{[0-9]}} 67; CHECK-NOT: fcvt 68; CHECK: ret 69 %a = load <64 x float>, <64 x float>* %in 70 %b = fptrunc <64 x float> %a to <64 x half> 71 store <64 x half> %b, <64 x half>* %out 72 ret void 73} 74 75; 76; fptrunc f64 -> f16 77; 78 79define <4 x half> @fptrunc_v4f64_v4f16(<4 x double>* %in) #0 { 80; CHECK-LABEL: fptrunc_v4f64_v4f16: 81; CHECK-COUNT-4: fcvt h{{[0-9]}}, d{{[0-9]}} 82; CHECK-NOT: fcvt 83; CHECK: ret 84 %a = load <4 x double>, <4 x double>* %in 85 %b = fptrunc <4 x double> %a to <4 x half> 86 ret <4 x half> %b 87} 88 89define <8 x half> @fptrunc_v8f64_v8f16(<8 x double>* %in) #0 { 90; CHECK-LABEL: fptrunc_v8f64_v8f16: 91; CHECK-COUNT-8: fcvt h{{[0-9]}}, d{{[0-9]}} 92; CHECK-NOT: fcvt 93; CHECK: ret 94 %a = load <8 x double>, <8 x double>* %in 95 %b = fptrunc <8 x double> %a to <8 x half> 96 ret <8 x half> %b 97} 98 99define void @fptrunc_v16f64_v16f16(<16 x double>* %in, <16 x half>* %out) #0 { 100; CHECK-LABEL: fptrunc_v16f64_v16f16: 101; CHECK-COUNT-16: fcvt h{{[0-9]}}, d{{[0-9]}} 102; CHECK-NOT: fcvt 103; CHECK: ret 104 %a = load <16 x double>, <16 x double>* %in 105 %b = fptrunc <16 x double> %a to <16 x half> 106 store <16 x half> %b, <16 x half>* %out 107 ret void 108} 109 110define void @fptrunc_v32f64_v32f16(<32 x double>* %in, <32 x half>* %out) #0 { 111; CHECK-LABEL: fptrunc_v32f64_v32f16: 112; CHECK-COUNT-32: fcvt h{{[0-9]}}, d{{[0-9]}} 113; CHECK-NOT: fcvt 114; CHECK: ret 115 %a = load <32 x double>, <32 x double>* %in 116 %b = fptrunc <32 x double> %a to <32 x half> 117 store <32 x half> %b, <32 x half>* %out 118 ret void 119} 120 121; 122; fptrunc f64 -> f32 123; 124 125define <4 x float> @fptrunc_v4f64_v4f32(<4 x double>* %in) #0 { 126; CHECK-LABEL: fptrunc_v4f64_v4f32: 127; CHECK-COUNT-4: fcvt s{{[0-9]}}, d{{[0-9]}} 128; CHECK-NOT: fcvt 129; CHECK: ret 130 %a = load <4 x double>, <4 x double>* %in 131 %b = fptrunc <4 x double> %a to <4 x float> 132 ret <4 x float> %b 133} 134 135define void @fptrunc_v8f64_v8f32(<8 x double>* %in, <8 x float>* %out) #0 { 136; CHECK-LABEL: fptrunc_v8f64_v8f32: 137; CHECK-COUNT-8: fcvt s{{[0-9]}}, d{{[0-9]}} 138; CHECK-NOT: fcvt 139; CHECK: ret 140 %a = load <8 x double>, <8 x double>* %in 141 %b = fptrunc <8 x double> %a to <8 x float> 142 store <8 x float> %b, <8 x float>* %out 143 ret void 144} 145 146define void @fptrunc_v16f64_v16f32(<16 x double>* %in, <16 x float>* %out) #0 { 147; CHECK-LABEL: fptrunc_v16f64_v16f32: 148; CHECK-COUNT-16: fcvt s{{[0-9]}}, d{{[0-9]}} 149; CHECK-NOT: fcvt 150; CHECK: ret 151 %a = load <16 x double>, <16 x double>* %in 152 %b = fptrunc <16 x double> %a to <16 x float> 153 store <16 x float> %b, <16 x float>* %out 154 ret void 155} 156 157define void @fptrunc_v32f64_v32f32(<32 x double>* %in, <32 x float>* %out) #0 { 158; CHECK-LABEL: fptrunc_v32f64_v32f32: 159; CHECK-COUNT-32: fcvt s{{[0-9]}}, d{{[0-9]}} 160; CHECK-NOT: fcvt 161; CHECK: ret 162 %a = load <32 x double>, <32 x double>* %in 163 %b = fptrunc <32 x double> %a to <32 x float> 164 store <32 x float> %b, <32 x float>* %out 165 ret void 166} 167 168attributes #0 = { nounwind "target-features"="+sve" } 169