1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s 2; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t 3 4; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it. 5; WARN-NOT: warning 6 7; 8; SVE Arith Vector Immediate Unpredicated CodeGen 9; 10 11; ADD 12define <vscale x 16 x i8> @add_i8_low(<vscale x 16 x i8> %a) { 13; CHECK-LABEL: add_i8_low 14; CHECK: add z0.b, z0.b, #30 15; CHECK-NEXT: ret 16 %elt = insertelement <vscale x 16 x i8> undef, i8 30, i32 0 17 %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer 18 %res = add <vscale x 16 x i8> %a, %splat 19 ret <vscale x 16 x i8> %res 20} 21 22define <vscale x 8 x i16> @add_i16_low(<vscale x 8 x i16> %a) { 23; CHECK-LABEL: add_i16_low 24; CHECK: add z0.h, z0.h, #30 25; CHECK-NEXT: ret 26 %elt = insertelement <vscale x 8 x i16> undef, i16 30, i32 0 27 %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer 28 %res = add <vscale x 8 x i16> %a, %splat 29 ret <vscale x 8 x i16> %res 30} 31 32define <vscale x 8 x i16> @add_i16_high(<vscale x 8 x i16> %a) { 33; CHECK-LABEL: add_i16_high 34; CHECK: add z0.h, z0.h, #1024 35; CHECK-NEXT: ret 36 %elt = insertelement <vscale x 8 x i16> undef, i16 1024, i32 0 37 %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer 38 %res = add <vscale x 8 x i16> %a, %splat 39 ret <vscale x 8 x i16> %res 40} 41 42define <vscale x 4 x i32> @add_i32_low(<vscale x 4 x i32> %a) { 43; CHECK-LABEL: add_i32_low 44; CHECK: add z0.s, z0.s, #30 45; CHECK-NEXT: ret 46 %elt = insertelement <vscale x 4 x i32> undef, i32 30, i32 0 47 %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer 48 %res = add <vscale x 4 x i32> %a, %splat 49 ret <vscale x 4 x i32> %res 50} 51 52define <vscale x 4 x i32> @add_i32_high(<vscale x 4 x i32> %a) { 53; CHECK-LABEL: add_i32_high 54; CHECK: add z0.s, z0.s, #1024 55; CHECK-NEXT: ret 56 %elt = insertelement <vscale x 4 x i32> undef, i32 1024, i32 0 57 %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer 58 %res = add <vscale x 4 x i32> %a, %splat 59 ret <vscale x 4 x i32> %res 60} 61 62define <vscale x 2 x i64> @add_i64_low(<vscale x 2 x i64> %a) { 63; CHECK-LABEL: add_i64_low 64; CHECK: add z0.d, z0.d, #30 65; CHECK-NEXT: ret 66 %elt = insertelement <vscale x 2 x i64> undef, i64 30, i32 0 67 %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 68 %res = add <vscale x 2 x i64> %a, %splat 69 ret <vscale x 2 x i64> %res 70} 71 72define <vscale x 2 x i64> @add_i64_high(<vscale x 2 x i64> %a) { 73; CHECK-LABEL: add_i64_high 74; CHECK: add z0.d, z0.d, #1024 75; CHECK-NEXT: ret 76 %elt = insertelement <vscale x 2 x i64> undef, i64 1024, i32 0 77 %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 78 %res = add <vscale x 2 x i64> %a, %splat 79 ret <vscale x 2 x i64> %res 80} 81 82; SUBR 83define <vscale x 16 x i8> @subr_i8_low(<vscale x 16 x i8> %a) { 84; CHECK-LABEL: subr_i8_low 85; CHECK: subr z0.b, z0.b, #30 86; CHECK-NEXT: ret 87 %elt = insertelement <vscale x 16 x i8> undef, i8 30, i32 0 88 %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer 89 %res = sub <vscale x 16 x i8> %splat, %a 90 ret <vscale x 16 x i8> %res 91} 92 93define <vscale x 8 x i16> @subr_i16_low(<vscale x 8 x i16> %a) { 94; CHECK-LABEL: subr_i16_low 95; CHECK: subr z0.h, z0.h, #30 96; CHECK-NEXT: ret 97 %elt = insertelement <vscale x 8 x i16> undef, i16 30, i32 0 98 %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer 99 %res = sub <vscale x 8 x i16> %splat, %a 100 ret <vscale x 8 x i16> %res 101} 102 103define <vscale x 8 x i16> @subr_i16_high(<vscale x 8 x i16> %a) { 104; CHECK-LABEL: subr_i16_high 105; CHECK: subr z0.h, z0.h, #1024 106; CHECK-NEXT: ret 107 %elt = insertelement <vscale x 8 x i16> undef, i16 1024, i32 0 108 %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer 109 %res = sub <vscale x 8 x i16> %splat, %a 110 ret <vscale x 8 x i16> %res 111} 112 113define <vscale x 4 x i32> @subr_i32_low(<vscale x 4 x i32> %a) { 114; CHECK-LABEL: subr_i32_low 115; CHECK: subr z0.s, z0.s, #30 116; CHECK-NEXT: ret 117 %elt = insertelement <vscale x 4 x i32> undef, i32 30, i32 0 118 %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer 119 %res = sub <vscale x 4 x i32> %splat, %a 120 ret <vscale x 4 x i32> %res 121} 122 123define <vscale x 4 x i32> @subr_i32_high(<vscale x 4 x i32> %a) { 124; CHECK-LABEL: subr_i32_high 125; CHECK: subr z0.s, z0.s, #1024 126; CHECK-NEXT: ret 127 %elt = insertelement <vscale x 4 x i32> undef, i32 1024, i32 0 128 %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer 129 %res = sub <vscale x 4 x i32> %splat, %a 130 ret <vscale x 4 x i32> %res 131} 132 133define <vscale x 2 x i64> @subr_i64_low(<vscale x 2 x i64> %a) { 134; CHECK-LABEL: subr_i64_low 135; CHECK: subr z0.d, z0.d, #30 136; CHECK-NEXT: ret 137 %elt = insertelement <vscale x 2 x i64> undef, i64 30, i32 0 138 %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 139 %res = sub <vscale x 2 x i64> %splat, %a 140 ret <vscale x 2 x i64> %res 141} 142 143define <vscale x 2 x i64> @subr_i64_high(<vscale x 2 x i64> %a) { 144; CHECK-LABEL: subr_i64_high 145; CHECK: subr z0.d, z0.d, #1024 146; CHECK-NEXT: ret 147 %elt = insertelement <vscale x 2 x i64> undef, i64 1024, i32 0 148 %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 149 %res = sub <vscale x 2 x i64> %splat, %a 150 ret <vscale x 2 x i64> %res 151} 152 153; SUB 154define <vscale x 16 x i8> @sub_i8_low(<vscale x 16 x i8> %a) { 155; CHECK-LABEL: sub_i8_low 156; CHECK: sub z0.b, z0.b, #30 157; CHECK-NEXT: ret 158 %elt = insertelement <vscale x 16 x i8> undef, i8 30, i32 0 159 %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer 160 %res = sub <vscale x 16 x i8> %a, %splat 161 ret <vscale x 16 x i8> %res 162} 163 164define <vscale x 8 x i16> @sub_i16_low(<vscale x 8 x i16> %a) { 165; CHECK-LABEL: sub_i16_low 166; CHECK: sub z0.h, z0.h, #30 167; CHECK-NEXT: ret 168 %elt = insertelement <vscale x 8 x i16> undef, i16 30, i32 0 169 %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer 170 %res = sub <vscale x 8 x i16> %a, %splat 171 ret <vscale x 8 x i16> %res 172} 173 174define <vscale x 8 x i16> @sub_i16_high(<vscale x 8 x i16> %a) { 175; CHECK-LABEL: sub_i16_high 176; CHECK: sub z0.h, z0.h, #1024 177; CHECK-NEXT: ret 178 %elt = insertelement <vscale x 8 x i16> undef, i16 1024, i32 0 179 %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer 180 %res = sub <vscale x 8 x i16> %a, %splat 181 ret <vscale x 8 x i16> %res 182} 183 184define <vscale x 4 x i32> @sub_i32_low(<vscale x 4 x i32> %a) { 185; CHECK-LABEL: sub_i32_low 186; CHECK: sub z0.s, z0.s, #30 187; CHECK-NEXT: ret 188 %elt = insertelement <vscale x 4 x i32> undef, i32 30, i32 0 189 %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer 190 %res = sub <vscale x 4 x i32> %a, %splat 191 ret <vscale x 4 x i32> %res 192} 193 194define <vscale x 4 x i32> @sub_i32_high(<vscale x 4 x i32> %a) { 195; CHECK-LABEL: sub_i32_high 196; CHECK: sub z0.s, z0.s, #1024 197; CHECK-NEXT: ret 198 %elt = insertelement <vscale x 4 x i32> undef, i32 1024, i32 0 199 %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer 200 %res = sub <vscale x 4 x i32> %a, %splat 201 ret <vscale x 4 x i32> %res 202} 203 204define <vscale x 2 x i64> @sub_i64_low(<vscale x 2 x i64> %a) { 205; CHECK-LABEL: sub_i64_low 206; CHECK: sub z0.d, z0.d, #30 207; CHECK-NEXT: ret 208 %elt = insertelement <vscale x 2 x i64> undef, i64 30, i32 0 209 %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 210 %res = sub <vscale x 2 x i64> %a, %splat 211 ret <vscale x 2 x i64> %res 212} 213 214define <vscale x 2 x i64> @sub_i64_high(<vscale x 2 x i64> %a) { 215; CHECK-LABEL: sub_i64_high 216; CHECK: sub z0.d, z0.d, #1024 217; CHECK-NEXT: ret 218 %elt = insertelement <vscale x 2 x i64> undef, i64 1024, i32 0 219 %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 220 %res = sub <vscale x 2 x i64> %a, %splat 221 ret <vscale x 2 x i64> %res 222} 223 224; SQADD 225define <vscale x 16 x i8> @sqadd_i8_low(<vscale x 16 x i8> %a) { 226; CHECK-LABEL: sqadd_i8_low 227; CHECK: sqadd z0.b, z0.b, #30 228; CHECK-NEXT: ret 229 %elt = insertelement <vscale x 16 x i8> undef, i8 30, i32 0 230 %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer 231 %res = call <vscale x 16 x i8> @llvm.sadd.sat.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %splat) 232 ret <vscale x 16 x i8> %res 233} 234 235define <vscale x 8 x i16> @sqadd_i16_low(<vscale x 8 x i16> %a) { 236; CHECK-LABEL: sqadd_i16_low 237; CHECK: sqadd z0.h, z0.h, #30 238; CHECK-NEXT: ret 239 %elt = insertelement <vscale x 8 x i16> undef, i16 30, i32 0 240 %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer 241 %res = call <vscale x 8 x i16> @llvm.sadd.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %splat) 242 ret <vscale x 8 x i16> %res 243} 244 245define <vscale x 8 x i16> @sqadd_i16_high(<vscale x 8 x i16> %a) { 246; CHECK-LABEL: sqadd_i16_high 247; CHECK: sqadd z0.h, z0.h, #1024 248; CHECK-NEXT: ret 249 %elt = insertelement <vscale x 8 x i16> undef, i16 1024, i32 0 250 %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer 251 %res = call <vscale x 8 x i16> @llvm.sadd.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %splat) 252 ret <vscale x 8 x i16> %res 253} 254 255define <vscale x 4 x i32> @sqadd_i32_low(<vscale x 4 x i32> %a) { 256; CHECK-LABEL: sqadd_i32_low 257; CHECK: sqadd z0.s, z0.s, #30 258; CHECK-NEXT: ret 259 %elt = insertelement <vscale x 4 x i32> undef, i32 30, i32 0 260 %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer 261 %res = call <vscale x 4 x i32> @llvm.sadd.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %splat) 262 ret <vscale x 4 x i32> %res 263} 264 265define <vscale x 4 x i32> @sqadd_i32_high(<vscale x 4 x i32> %a) { 266; CHECK-LABEL: sqadd_i32_high 267; CHECK: sqadd z0.s, z0.s, #1024 268; CHECK-NEXT: ret 269 %elt = insertelement <vscale x 4 x i32> undef, i32 1024, i32 0 270 %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer 271 %res = call <vscale x 4 x i32> @llvm.sadd.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %splat) 272 ret <vscale x 4 x i32> %res 273} 274 275define <vscale x 2 x i64> @sqadd_i64_low(<vscale x 2 x i64> %a) { 276; CHECK-LABEL: sqadd_i64_low 277; CHECK: sqadd z0.d, z0.d, #30 278; CHECK-NEXT: ret 279 %elt = insertelement <vscale x 2 x i64> undef, i64 30, i32 0 280 %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 281 %res = call <vscale x 2 x i64> @llvm.sadd.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %splat) 282 ret <vscale x 2 x i64> %res 283} 284 285define <vscale x 2 x i64> @sqadd_i64_high(<vscale x 2 x i64> %a) { 286; CHECK-LABEL: sqadd_i64_high 287; CHECK: sqadd z0.d, z0.d, #1024 288; CHECK-NEXT: ret 289 %elt = insertelement <vscale x 2 x i64> undef, i64 1024, i32 0 290 %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 291 %res = call <vscale x 2 x i64> @llvm.sadd.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %splat) 292 ret <vscale x 2 x i64> %res 293} 294 295; UQADD 296define <vscale x 16 x i8> @uqadd_i8_low(<vscale x 16 x i8> %a) { 297; CHECK-LABEL: uqadd_i8_low 298; CHECK: uqadd z0.b, z0.b, #30 299; CHECK-NEXT: ret 300 %elt = insertelement <vscale x 16 x i8> undef, i8 30, i32 0 301 %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer 302 %res = call <vscale x 16 x i8> @llvm.uadd.sat.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %splat) 303 ret <vscale x 16 x i8> %res 304} 305 306define <vscale x 8 x i16> @uqadd_i16_low(<vscale x 8 x i16> %a) { 307; CHECK-LABEL: uqadd_i16_low 308; CHECK: uqadd z0.h, z0.h, #30 309; CHECK-NEXT: ret 310 %elt = insertelement <vscale x 8 x i16> undef, i16 30, i32 0 311 %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer 312 %res = call <vscale x 8 x i16> @llvm.uadd.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %splat) 313 ret <vscale x 8 x i16> %res 314} 315 316define <vscale x 8 x i16> @uqadd_i16_high(<vscale x 8 x i16> %a) { 317; CHECK-LABEL: uqadd_i16_high 318; CHECK: uqadd z0.h, z0.h, #1024 319; CHECK-NEXT: ret 320 %elt = insertelement <vscale x 8 x i16> undef, i16 1024, i32 0 321 %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer 322 %res = call <vscale x 8 x i16> @llvm.uadd.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %splat) 323 ret <vscale x 8 x i16> %res 324} 325 326define <vscale x 4 x i32> @uqadd_i32_low(<vscale x 4 x i32> %a) { 327; CHECK-LABEL: uqadd_i32_low 328; CHECK: uqadd z0.s, z0.s, #30 329; CHECK-NEXT: ret 330 %elt = insertelement <vscale x 4 x i32> undef, i32 30, i32 0 331 %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer 332 %res = call <vscale x 4 x i32> @llvm.uadd.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %splat) 333 ret <vscale x 4 x i32> %res 334} 335 336define <vscale x 4 x i32> @uqadd_i32_high(<vscale x 4 x i32> %a) { 337; CHECK-LABEL: uqadd_i32_high 338; CHECK: uqadd z0.s, z0.s, #1024 339; CHECK-NEXT: ret 340 %elt = insertelement <vscale x 4 x i32> undef, i32 1024, i32 0 341 %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer 342 %res = call <vscale x 4 x i32> @llvm.uadd.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %splat) 343 ret <vscale x 4 x i32> %res 344} 345 346define <vscale x 2 x i64> @uqadd_i64_low(<vscale x 2 x i64> %a) { 347; CHECK-LABEL: uqadd_i64_low 348; CHECK: uqadd z0.d, z0.d, #30 349; CHECK-NEXT: ret 350 %elt = insertelement <vscale x 2 x i64> undef, i64 30, i32 0 351 %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 352 %res = call <vscale x 2 x i64> @llvm.uadd.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %splat) 353 ret <vscale x 2 x i64> %res 354} 355 356define <vscale x 2 x i64> @uqadd_i64_high(<vscale x 2 x i64> %a) { 357; CHECK-LABEL: uqadd_i64_high 358; CHECK: uqadd z0.d, z0.d, #1024 359; CHECK-NEXT: ret 360 %elt = insertelement <vscale x 2 x i64> undef, i64 1024, i32 0 361 %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 362 %res = call <vscale x 2 x i64> @llvm.uadd.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %splat) 363 ret <vscale x 2 x i64> %res 364} 365 366; SQSUB 367define <vscale x 16 x i8> @sqsub_i8_low(<vscale x 16 x i8> %a) { 368; CHECK-LABEL: sqsub_i8_low 369; CHECK: sqsub z0.b, z0.b, #30 370; CHECK-NEXT: ret 371 %elt = insertelement <vscale x 16 x i8> undef, i8 30, i32 0 372 %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer 373 %res = call <vscale x 16 x i8> @llvm.ssub.sat.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %splat) 374 ret <vscale x 16 x i8> %res 375} 376 377define <vscale x 8 x i16> @sqsub_i16_low(<vscale x 8 x i16> %a) { 378; CHECK-LABEL: sqsub_i16_low 379; CHECK: sqsub z0.h, z0.h, #30 380; CHECK-NEXT: ret 381 %elt = insertelement <vscale x 8 x i16> undef, i16 30, i32 0 382 %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer 383 %res = call <vscale x 8 x i16> @llvm.ssub.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %splat) 384 ret <vscale x 8 x i16> %res 385} 386 387define <vscale x 8 x i16> @sqsub_i16_high(<vscale x 8 x i16> %a) { 388; CHECK-LABEL: sqsub_i16_high 389; CHECK: sqsub z0.h, z0.h, #1024 390; CHECK-NEXT: ret 391 %elt = insertelement <vscale x 8 x i16> undef, i16 1024, i32 0 392 %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer 393 %res = call <vscale x 8 x i16> @llvm.ssub.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %splat) 394 ret <vscale x 8 x i16> %res 395} 396 397define <vscale x 4 x i32> @sqsub_i32_low(<vscale x 4 x i32> %a) { 398; CHECK-LABEL: sqsub_i32_low 399; CHECK: sqsub z0.s, z0.s, #30 400; CHECK-NEXT: ret 401 %elt = insertelement <vscale x 4 x i32> undef, i32 30, i32 0 402 %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer 403 %res = call <vscale x 4 x i32> @llvm.ssub.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %splat) 404 ret <vscale x 4 x i32> %res 405} 406 407define <vscale x 4 x i32> @sqsub_i32_high(<vscale x 4 x i32> %a) { 408; CHECK-LABEL: sqsub_i32_high 409; CHECK: sqsub z0.s, z0.s, #1024 410; CHECK-NEXT: ret 411 %elt = insertelement <vscale x 4 x i32> undef, i32 1024, i32 0 412 %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer 413 %res = call <vscale x 4 x i32> @llvm.ssub.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %splat) 414 ret <vscale x 4 x i32> %res 415} 416 417define <vscale x 2 x i64> @sqsub_i64_low(<vscale x 2 x i64> %a) { 418; CHECK-LABEL: sqsub_i64_low 419; CHECK: sqsub z0.d, z0.d, #30 420; CHECK-NEXT: ret 421 %elt = insertelement <vscale x 2 x i64> undef, i64 30, i32 0 422 %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 423 %res = call <vscale x 2 x i64> @llvm.ssub.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %splat) 424 ret <vscale x 2 x i64> %res 425} 426 427define <vscale x 2 x i64> @sqsub_i64_high(<vscale x 2 x i64> %a) { 428; CHECK-LABEL: sqsub_i64_high 429; CHECK: sqsub z0.d, z0.d, #1024 430; CHECK-NEXT: ret 431 %elt = insertelement <vscale x 2 x i64> undef, i64 1024, i32 0 432 %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 433 %res = call <vscale x 2 x i64> @llvm.ssub.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %splat) 434 ret <vscale x 2 x i64> %res 435} 436 437; UQSUB 438define <vscale x 16 x i8> @uqsub_i8_low(<vscale x 16 x i8> %a) { 439; CHECK-LABEL: uqsub_i8_low 440; CHECK: uqsub z0.b, z0.b, #30 441; CHECK-NEXT: ret 442 %elt = insertelement <vscale x 16 x i8> undef, i8 30, i32 0 443 %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer 444 %res = call <vscale x 16 x i8> @llvm.usub.sat.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %splat) 445 ret <vscale x 16 x i8> %res 446} 447 448define <vscale x 8 x i16> @uqsub_i16_low(<vscale x 8 x i16> %a) { 449; CHECK-LABEL: uqsub_i16_low 450; CHECK: uqsub z0.h, z0.h, #30 451; CHECK-NEXT: ret 452 %elt = insertelement <vscale x 8 x i16> undef, i16 30, i32 0 453 %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer 454 %res = call <vscale x 8 x i16> @llvm.usub.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %splat) 455 ret <vscale x 8 x i16> %res 456} 457 458define <vscale x 8 x i16> @uqsub_i16_high(<vscale x 8 x i16> %a) { 459; CHECK-LABEL: uqsub_i16_high 460; CHECK: uqsub z0.h, z0.h, #1024 461; CHECK-NEXT: ret 462 %elt = insertelement <vscale x 8 x i16> undef, i16 1024, i32 0 463 %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer 464 %res = call <vscale x 8 x i16> @llvm.usub.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %splat) 465 ret <vscale x 8 x i16> %res 466} 467 468define <vscale x 4 x i32> @uqsub_i32_low(<vscale x 4 x i32> %a) { 469; CHECK-LABEL: uqsub_i32_low 470; CHECK: uqsub z0.s, z0.s, #30 471; CHECK-NEXT: ret 472 %elt = insertelement <vscale x 4 x i32> undef, i32 30, i32 0 473 %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer 474 %res = call <vscale x 4 x i32> @llvm.usub.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %splat) 475 ret <vscale x 4 x i32> %res 476} 477 478define <vscale x 4 x i32> @uqsub_i32_high(<vscale x 4 x i32> %a) { 479; CHECK-LABEL: uqsub_i32_high 480; CHECK: uqsub z0.s, z0.s, #1024 481; CHECK-NEXT: ret 482 %elt = insertelement <vscale x 4 x i32> undef, i32 1024, i32 0 483 %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer 484 %res = call <vscale x 4 x i32> @llvm.usub.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %splat) 485 ret <vscale x 4 x i32> %res 486} 487 488define <vscale x 2 x i64> @uqsub_i64_low(<vscale x 2 x i64> %a) { 489; CHECK-LABEL: uqsub_i64_low 490; CHECK: uqsub z0.d, z0.d, #30 491; CHECK-NEXT: ret 492 %elt = insertelement <vscale x 2 x i64> undef, i64 30, i32 0 493 %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 494 %res = call <vscale x 2 x i64> @llvm.usub.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %splat) 495 ret <vscale x 2 x i64> %res 496} 497 498define <vscale x 2 x i64> @uqsub_i64_high(<vscale x 2 x i64> %a) { 499; CHECK-LABEL: uqsub_i64_high 500; CHECK: uqsub z0.d, z0.d, #1024 501; CHECK-NEXT: ret 502 %elt = insertelement <vscale x 2 x i64> undef, i64 1024, i32 0 503 %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 504 %res = call <vscale x 2 x i64> @llvm.usub.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %splat) 505 ret <vscale x 2 x i64> %res 506} 507 508declare <vscale x 16 x i8> @llvm.sadd.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) 509declare <vscale x 8 x i16> @llvm.sadd.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) 510declare <vscale x 4 x i32> @llvm.sadd.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) 511declare <vscale x 2 x i64> @llvm.sadd.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) 512declare <vscale x 16 x i8> @llvm.uadd.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) 513declare <vscale x 8 x i16> @llvm.uadd.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) 514declare <vscale x 4 x i32> @llvm.uadd.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) 515declare <vscale x 2 x i64> @llvm.uadd.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) 516declare <vscale x 16 x i8> @llvm.ssub.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) 517declare <vscale x 8 x i16> @llvm.ssub.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) 518declare <vscale x 4 x i32> @llvm.ssub.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) 519declare <vscale x 2 x i64> @llvm.ssub.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) 520declare <vscale x 16 x i8> @llvm.usub.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) 521declare <vscale x 8 x i16> @llvm.usub.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) 522declare <vscale x 4 x i32> @llvm.usub.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) 523declare <vscale x 2 x i64> @llvm.usub.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) 524