1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
2; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
3
4; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
5; WARN-NOT: warning
6
7define <vscale x 16 x i8> @and_pred_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
8; CHECK-LABEL: and_pred_i8:
9; CHECK: and z0.b, p0/m, z0.b, z1.b
10; CHECK-NEXT: ret
11  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.and.nxv2i8(<vscale x 16 x i1> %pg,
12                                                              <vscale x 16 x i8> %a,
13                                                              <vscale x 16 x i8> %b)
14  ret <vscale x 16 x i8> %out
15}
16
17define <vscale x 8 x i16> @and_pred_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
18; CHECK-LABEL: and_pred_i16:
19; CHECK: and z0.h, p0/m, z0.h, z1.h
20; CHECK-NEXT: ret
21  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.and.nxv2i16(<vscale x 8 x i1> %pg,
22                                                               <vscale x 8 x i16> %a,
23                                                               <vscale x 8 x i16> %b)
24  ret <vscale x 8 x i16> %out
25}
26
27define <vscale x 4 x i32> @and_pred_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
28; CHECK-LABEL: and_pred_i32:
29; CHECK: and z0.s, p0/m, z0.s, z1.s
30; CHECK-NEXT: ret
31  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv2i32(<vscale x 4 x i1> %pg,
32                                                               <vscale x 4 x i32> %a,
33                                                               <vscale x 4 x i32> %b)
34  ret <vscale x 4 x i32> %out
35}
36
37define <vscale x 2 x i64> @and_pred_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
38; CHECK-LABEL: and_pred_i64:
39; CHECK: and z0.d, p0/m, z0.d, z1.d
40; CHECK-NEXT: ret
41  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.and.nxv2i64(<vscale x 2 x i1> %pg,
42                                                               <vscale x 2 x i64> %a,
43                                                               <vscale x 2 x i64> %b)
44  ret <vscale x 2 x i64> %out
45}
46
47define <vscale x 16 x i8> @or_pred_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
48; CHECK-LABEL: or_pred_i8:
49; CHECK: orr z0.b, p0/m, z0.b, z1.b
50; CHECK-NEXT: ret
51  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv2i8(<vscale x 16 x i1> %pg,
52                                                              <vscale x 16 x i8> %a,
53                                                              <vscale x 16 x i8> %b)
54  ret <vscale x 16 x i8> %out
55}
56
57define <vscale x 8 x i16> @or_pred_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
58; CHECK-LABEL: or_pred_i16:
59; CHECK: orr z0.h, p0/m, z0.h, z1.h
60; CHECK-NEXT: ret
61  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv2i16(<vscale x 8 x i1> %pg,
62                                                               <vscale x 8 x i16> %a,
63                                                               <vscale x 8 x i16> %b)
64  ret <vscale x 8 x i16> %out
65}
66
67define <vscale x 4 x i32> @or_pred_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
68; CHECK-LABEL: or_pred_i32:
69; CHECK: orr z0.s, p0/m, z0.s, z1.s
70; CHECK-NEXT: ret
71  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv2i32(<vscale x 4 x i1> %pg,
72                                                               <vscale x 4 x i32> %a,
73                                                               <vscale x 4 x i32> %b)
74  ret <vscale x 4 x i32> %out
75}
76
77define <vscale x 2 x i64> @or_pred_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
78; CHECK-LABEL: or_pred_i64:
79; CHECK: orr z0.d, p0/m, z0.d, z1.d
80; CHECK-NEXT: ret
81  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1> %pg,
82                                                               <vscale x 2 x i64> %a,
83                                                               <vscale x 2 x i64> %b)
84  ret <vscale x 2 x i64> %out
85}
86
87define <vscale x 16 x i8> @xor_pred_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
88; CHECK-LABEL: xor_pred_i8:
89; CHECK: eor z0.b, p0/m, z0.b, z1.b
90; CHECK-NEXT: ret
91  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.eor.nxv2i8(<vscale x 16 x i1> %pg,
92                                                              <vscale x 16 x i8> %a,
93                                                              <vscale x 16 x i8> %b)
94  ret <vscale x 16 x i8> %out
95}
96
97define <vscale x 8 x i16> @xor_pred_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
98; CHECK-LABEL: xor_pred_i16:
99; CHECK: eor z0.h, p0/m, z0.h, z1.h
100; CHECK-NEXT: ret
101  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.eor.nxv2i16(<vscale x 8 x i1> %pg,
102                                                               <vscale x 8 x i16> %a,
103                                                               <vscale x 8 x i16> %b)
104  ret <vscale x 8 x i16> %out
105}
106
107define <vscale x 4 x i32> @xor_pred_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
108; CHECK-LABEL: xor_pred_i32:
109; CHECK: eor z0.s, p0/m, z0.s, z1.s
110; CHECK-NEXT: ret
111  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv2i32(<vscale x 4 x i1> %pg,
112                                                               <vscale x 4 x i32> %a,
113                                                               <vscale x 4 x i32> %b)
114  ret <vscale x 4 x i32> %out
115}
116
117define <vscale x 2 x i64> @xor_pred_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
118; CHECK-LABEL: xor_pred_i64:
119; CHECK: eor z0.d, p0/m, z0.d, z1.d
120; CHECK-NEXT: ret
121  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.eor.nxv2i64(<vscale x 2 x i1> %pg,
122                                                               <vscale x 2 x i64> %a,
123                                                               <vscale x 2 x i64> %b)
124  ret <vscale x 2 x i64> %out
125}
126
127define <vscale x 16 x i8> @bic_pred_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
128; CHECK-LABEL: bic_pred_i8:
129; CHECK: bic z0.b, p0/m, z0.b, z1.b
130; CHECK-NEXT: ret
131  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.bic.nxv2i8(<vscale x 16 x i1> %pg,
132                                                              <vscale x 16 x i8> %a,
133                                                              <vscale x 16 x i8> %b)
134  ret <vscale x 16 x i8> %out
135}
136
137define <vscale x 8 x i16> @bic_pred_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
138; CHECK-LABEL: bic_pred_i16:
139; CHECK: bic z0.h, p0/m, z0.h, z1.h
140; CHECK-NEXT: ret
141  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.bic.nxv2i16(<vscale x 8 x i1> %pg,
142                                                               <vscale x 8 x i16> %a,
143                                                               <vscale x 8 x i16> %b)
144  ret <vscale x 8 x i16> %out
145}
146
147
148define <vscale x 4 x i32> @bic_pred_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
149; CHECK-LABEL: bic_pred_i32:
150; CHECK: bic z0.s, p0/m, z0.s, z1.s
151; CHECK-NEXT: ret
152  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.bic.nxv2i32(<vscale x 4 x i1> %pg,
153                                                               <vscale x 4 x i32> %a,
154                                                               <vscale x 4 x i32> %b)
155  ret <vscale x 4 x i32> %out
156}
157
158define <vscale x 2 x i64> @bic_pred_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
159; CHECK-LABEL: bic_pred_i64:
160; CHECK: bic z0.d, p0/m, z0.d, z1.d
161; CHECK-NEXT: ret
162  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.bic.nxv2i64(<vscale x 2 x i1> %pg,
163                                                               <vscale x 2 x i64> %a,
164                                                               <vscale x 2 x i64> %b)
165  ret <vscale x 2 x i64> %out
166}
167
168declare <vscale x 16 x i8> @llvm.aarch64.sve.and.nxv2i8(<vscale x 16 x i1>,<vscale x 16 x i8>,<vscale x 16 x i8>)
169declare <vscale x 8 x i16> @llvm.aarch64.sve.and.nxv2i16(<vscale x 8 x i1>,<vscale x 8 x i16>,<vscale x 8 x i16>)
170declare <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv2i32(<vscale x 4 x i1>,<vscale x 4 x i32>,<vscale x 4 x i32>)
171declare <vscale x 2 x i64> @llvm.aarch64.sve.and.nxv2i64(<vscale x 2 x i1>,<vscale x 2 x i64>,<vscale x 2 x i64>)
172declare <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv2i8(<vscale x 16 x i1>,<vscale x 16 x i8>,<vscale x 16 x i8>)
173declare <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv2i16(<vscale x 8 x i1>,<vscale x 8 x i16>,<vscale x 8 x i16>)
174declare <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv2i32(<vscale x 4 x i1>,<vscale x 4 x i32>,<vscale x 4 x i32>)
175declare <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1>,<vscale x 2 x i64>,<vscale x 2 x i64>)
176declare <vscale x 16 x i8> @llvm.aarch64.sve.eor.nxv2i8(<vscale x 16 x i1>,<vscale x 16 x i8>,<vscale x 16 x i8>)
177declare <vscale x 8 x i16> @llvm.aarch64.sve.eor.nxv2i16(<vscale x 8 x i1>,<vscale x 8 x i16>,<vscale x 8 x i16>)
178declare <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv2i32(<vscale x 4 x i1>,<vscale x 4 x i32>,<vscale x 4 x i32>)
179declare <vscale x 2 x i64> @llvm.aarch64.sve.eor.nxv2i64(<vscale x 2 x i1>,<vscale x 2 x i64>,<vscale x 2 x i64>)
180declare <vscale x 16 x i8> @llvm.aarch64.sve.bic.nxv2i8(<vscale x 16 x i1>,<vscale x 16 x i8>,<vscale x 16 x i8>)
181declare <vscale x 8 x i16> @llvm.aarch64.sve.bic.nxv2i16(<vscale x 8 x i1>,<vscale x 8 x i16>,<vscale x 8 x i16>)
182declare <vscale x 4 x i32> @llvm.aarch64.sve.bic.nxv2i32(<vscale x 4 x i1>,<vscale x 4 x i32>,<vscale x 4 x i32>)
183declare <vscale x 2 x i64> @llvm.aarch64.sve.bic.nxv2i64(<vscale x 2 x i1>,<vscale x 2 x i64>,<vscale x 2 x i64>)
184