1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+f64mm,+bf16 -asm-verbose=0 < %s 2>%t | FileCheck %s
2; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
3
4; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
5; WARN-NOT: warning
6
7;
8; LD1ROB
9;
10
11define <vscale x 16 x i8> @ld1rob_i8(<vscale x 16 x i1> %pg, i8* %a, i64 %index) nounwind {
12; CHECK-LABEL: ld1rob_i8:
13; CHECK-NEXT:  ld1rob { z0.b }, p0/z, [x0, x1]
14; CHECK-NEXT:  ret
15  %base = getelementptr i8, i8* %a, i64 %index
16  %load = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1> %pg, i8* %base)
17  ret <vscale x 16 x i8> %load
18}
19
20;
21; LD1ROH
22;
23
24define <vscale x 8 x i16> @ld1roh_i16(<vscale x 8 x i1> %pg, i16* %a, i64 %index) nounwind {
25; CHECK-LABEL: ld1roh_i16:
26; CHECK-NEXT:  ld1roh { z0.h }, p0/z, [x0, x1, lsl #1]
27; CHECK-NEXT:  ret
28  %base = getelementptr i16, i16* %a, i64 %index
29  %load = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16(<vscale x 8 x i1> %pg, i16* %base)
30  ret <vscale x 8 x i16> %load
31}
32
33define <vscale x 8 x half> @ld1roh_f16(<vscale x 8 x i1> %pg, half* %a, i64 %index) nounwind {
34; CHECK-LABEL: ld1roh_f16:
35; CHECK-NEXT:  ld1roh { z0.h }, p0/z, [x0, x1, lsl #1]
36; CHECK-NEXT:  ret
37  %base = getelementptr half, half* %a, i64 %index
38  %load = call <vscale x 8 x half> @llvm.aarch64.sve.ld1ro.nxv8f16(<vscale x 8 x i1> %pg, half* %base)
39  ret <vscale x 8 x half> %load
40}
41
42; bfloat - requires -mattr=+bf16
43define <vscale x 8 x bfloat> @ld1roh_bf16(<vscale x 8 x i1> %pg, bfloat* %a, i64 %index) nounwind {
44; CHECK-LABEL: ld1roh_bf16:
45; CHECK-NEXT:  ld1roh { z0.h }, p0/z, [x0, x1, lsl #1]
46; CHECK-NEXT:  ret
47  %base = getelementptr bfloat, bfloat* %a, i64 %index
48  %load = call <vscale x 8 x bfloat> @llvm.aarch64.sve.ld1ro.nxv8bf16(<vscale x 8 x i1> %pg, bfloat* %base)
49  ret <vscale x 8 x bfloat> %load
50}
51
52;
53; LD1ROW
54;
55
56define<vscale x 4 x i32> @ld1row_i32(<vscale x 4 x i1> %pg, i32* %a, i64 %index) nounwind {
57; CHECK-LABEL: ld1row_i32:
58; CHECK-NEXT:  ld1row { z0.s }, p0/z, [x0, x1, lsl #2]
59; CHECK-NEXT:  ret
60  %base = getelementptr i32, i32* %a, i64 %index
61  %load = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32(<vscale x 4 x i1> %pg, i32* %base)
62  ret <vscale x 4 x i32> %load
63}
64
65define<vscale x 4 x float> @ld1row_f32(<vscale x 4 x i1> %pg, float* %a, i64 %index) nounwind {
66; CHECK-LABEL: ld1row_f32:
67; CHECK-NEXT:  ld1row { z0.s }, p0/z, [x0, x1, lsl #2]
68; CHECK-NEXT:  ret
69  %base = getelementptr float, float* %a, i64 %index
70  %load = call <vscale x 4 x float> @llvm.aarch64.sve.ld1ro.nxv4f32(<vscale x 4 x i1> %pg, float* %base)
71  ret <vscale x 4 x float> %load
72}
73
74;
75; LD1ROD
76;
77
78define <vscale x 2 x i64> @ld1rod_i64(<vscale x 2 x i1> %pg, i64* %a, i64 %index) nounwind {
79; CHECK-LABEL: ld1rod_i64:
80; CHECK-NEXT:  ld1rod { z0.d }, p0/z, [x0, x1, lsl #3]
81; CHECK-NEXT:  ret
82  %base = getelementptr i64, i64* %a, i64 %index
83  %load = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64(<vscale x 2 x i1> %pg, i64* %base)
84  ret <vscale x 2 x i64> %load
85}
86
87define <vscale x 2 x double> @ld1rod_f64(<vscale x 2 x i1> %pg, double* %a, i64 %index) nounwind {
88; CHECK-LABEL: ld1rod_f64:
89; CHECK-NEXT:  ld1rod { z0.d }, p0/z, [x0, x1, lsl #3]
90; CHECK-NEXT:  ret
91  %base = getelementptr double, double* %a, i64 %index
92  %load = call <vscale x 2 x double> @llvm.aarch64.sve.ld1ro.nxv2f64(<vscale x 2 x i1> %pg, double* %base)
93  ret <vscale x 2 x double> %load
94}
95
96declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1>, i8*)
97
98declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16(<vscale x 8 x i1>, i16*)
99declare <vscale x 8 x half> @llvm.aarch64.sve.ld1ro.nxv8f16(<vscale x 8 x i1>, half*)
100declare <vscale x 8 x bfloat> @llvm.aarch64.sve.ld1ro.nxv8bf16(<vscale x 8 x i1>, bfloat*)
101
102declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32(<vscale x 4 x i1>, i32*)
103declare <vscale x 4 x float> @llvm.aarch64.sve.ld1ro.nxv4f32(<vscale x 4 x i1>, float*)
104
105declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64(<vscale x 2 x i1>, i64*)
106declare <vscale x 2 x double> @llvm.aarch64.sve.ld1ro.nxv2f64(<vscale x 2 x i1>, double*)
107